From: maxime.ripard@free-electrons.com (Maxime Ripard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/8] clk: sunxi: factors: Add m_start parameters
Date: Fri, 15 May 2015 09:43:14 +0200 [thread overview]
Message-ID: <20150515074314.GQ4004@lukather> (raw)
In-Reply-To: <CAGb2v669fsz_pA+B0r8efp0BMxY-D86qfLuGQCqK1POuu9PmxQ@mail.gmail.com>
On Thu, May 14, 2015 at 05:12:07PM +0800, Chen-Yu Tsai wrote:
> On Sat, May 2, 2015 at 7:24 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Some clocks start incrementing the m factor at 0. Add a parameter to handle
> > it just like we did for the N factor.
> >
> > Since the behaviour until now was to assume that the m factor was starting
> > at 1, we also need to fix the other users.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/clk/sunxi/clk-factors.c | 11 ++++++++++-
> > drivers/clk/sunxi/clk-factors.h | 2 ++
> > drivers/clk/sunxi/clk-mod0.c | 2 ++
> > drivers/clk/sunxi/clk-sun8i-mbus.c | 2 ++
> > drivers/clk/sunxi/clk-sun9i-core.c | 6 ++++++
> > drivers/clk/sunxi/clk-sunxi.c | 10 ++++++++++
> > 6 files changed, 32 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
> > index 8c20190a3e9f..100a711c3e3d 100644
> > --- a/drivers/clk/sunxi/clk-factors.c
> > +++ b/drivers/clk/sunxi/clk-factors.c
> > @@ -56,15 +56,24 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
> > /* Get each individual factor if applicable */
> > if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
> > n = FACTOR_GET(config->nshift, config->nwidth, reg);
> > +
> > if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
> > k = FACTOR_GET(config->kshift, config->kwidth, reg);
> > +
> > if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
> > m = FACTOR_GET(config->mshift, config->mwidth, reg);
> > + else
> > + /* Make sure we don't get a division by zero */
> > + m = 1;
>
> What happens when mwidth is valid, m_start = 0, and m = 0?
That's a very good question. A division by zero in the kernel, I'd
say.
But I don't think we can end up in such a case today, and it's
somewhat expected that it will happen, and no clock have looked at can
actually end up in such a case.
> Other than that, this one looks good.
Thanks!
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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next prev parent reply other threads:[~2015-05-15 7:43 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-02 11:24 [PATCH 0/8] clk: sunxi: Add support for the Audio PLL Maxime Ripard
2015-05-02 11:24 ` [PATCH 1/8] clk: sunxi: factors: Add m_start parameters Maxime Ripard
2015-05-14 9:12 ` Chen-Yu Tsai
2015-05-15 7:43 ` Maxime Ripard [this message]
2015-05-15 7:48 ` Chen-Yu Tsai
2015-05-15 8:05 ` Maxime Ripard
2015-05-15 9:11 ` Chen-Yu Tsai
2015-05-15 14:21 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 2/8] clk: sunxi: factors: Add a parameter for N and M zeros Maxime Ripard
2015-05-02 11:24 ` [PATCH 3/8] clk: sunxi: Add a driver for the PLL2 Maxime Ripard
2015-05-14 9:43 ` Chen-Yu Tsai
2015-05-15 7:45 ` Maxime Ripard
2015-05-15 9:15 ` Chen-Yu Tsai
2015-05-15 14:44 ` Maxime Ripard
2015-05-19 7:58 ` Chen-Yu Tsai
2015-05-19 20:53 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 4/8] clk: sunxi: codec clock support Maxime Ripard
2015-05-14 11:03 ` Chen-Yu Tsai
2015-05-15 7:46 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 5/8] clk: sunxi: mod1 " Maxime Ripard
2015-05-14 13:43 ` Chen-Yu Tsai
2015-05-15 7:41 ` Maxime Ripard
2015-05-02 11:24 ` [PATCH 6/8] ARM: sunxi: Add PLL2 support Maxime Ripard
2015-05-02 11:24 ` [PATCH 7/8] ARM: sunxi: Add codec clock support Maxime Ripard
2015-05-14 12:43 ` Chen-Yu Tsai
2015-05-02 11:24 ` [PATCH 8/8] ARM: sun7i: Add mod1 clock nodes Maxime Ripard
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