From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks
Date: Tue, 19 May 2015 16:59:23 +0200 [thread overview]
Message-ID: <20150519145922.GA28018@ulmo> (raw)
In-Reply-To: <1432035567-19008-1-git-send-email-mikko.perttunen@kapsi.fi>
On Tue, May 19, 2015 at 02:39:27PM +0300, Mikko Perttunen wrote:
> This patch allows SoC-specific CAR initialization routines to register
> their own reset_assert and reset_deassert callbacks with the common Tegra
> CAR code. If defined, the common code will call these callbacks when a
> reset control with number >= num_periph_banks * 32 is attempted to be asserted
> or deasserted respectively. Numbers greater than or equal to num_periph_banks * 32
> are used to avoid clashes with low numbers that are automatically mapped to
> standard CAR reset lines.
>
> Each SoC with these special resets should specify the defined reset control
> numbers in a device tree header file.
This is looking pretty good, but I think we can simplify a wee bit
more...
> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
> Acked-by: Michael Turquette <mturquette@linaro.org>
> ---
> drivers/clk/tegra/clk.c | 39 +++++++++++++++++++++++++++++++--------
> drivers/clk/tegra/clk.h | 3 +++
> 2 files changed, 34 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index 41cd87c..c093ed9 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -49,7 +49,6 @@
> #define RST_DEVICES_L 0x004
> #define RST_DEVICES_H 0x008
> #define RST_DEVICES_U 0x00C
> -#define RST_DFLL_DVCO 0x2F4
> #define RST_DEVICES_V 0x358
> #define RST_DEVICES_W 0x35C
> #define RST_DEVICES_X 0x28C
> @@ -79,6 +78,11 @@ static struct clk **clks;
> static int clk_num;
> static struct clk_onecell_data clk_data;
>
> +/* Handlers for SoC-specific reset lines */
> +static int (*special_reset_assert)(unsigned long);
> +static int (*special_reset_deassert)(unsigned long);
> +static int special_reset_num;
I think we can get rid of this if we...
> +
> static struct tegra_clk_periph_regs periph_regs[] = {
> [0] = {
> .enb_reg = CLK_OUT_ENB_L,
> @@ -152,19 +156,29 @@ static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
> */
> tegra_read_chipid();
>
> - writel_relaxed(BIT(id % 32),
> - clk_base + periph_regs[id / 32].rst_set_reg);
> + if (id < periph_banks * 32) {
> + writel_relaxed(BIT(id % 32),
> + clk_base + periph_regs[id / 32].rst_set_reg);
> + return 0;
> + } else if (id < periph_banks * 32 + special_reset_num) {
> + return special_reset_assert(id);
> + }
... pass id - periph_banks * 32 into special_reset_assert(). Oh, but
then...
> @@ -286,10 +300,19 @@ void __init tegra_add_of_provider(struct device_node *np)
> of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>
> rst_ctlr.of_node = np;
> - rst_ctlr.nr_resets = periph_banks * 32;
> + rst_ctlr.nr_resets = periph_banks * 32 + special_reset_num;
... this is no longer going to work. We could keep special_reset_num,
though obviously it should be an unsigned int and renamed to
num_special_reset, yet still pass the relative ID into the SoC-specific
callbacks, after all that's what they care about and each implementation
would have to subtract periph_banks * 32 anyway.
> reset_controller_register(&rst_ctlr);
> }
>
> +void __init tegra_init_special_resets(int num,
> + int (*assert)(unsigned long),
> + int (*deassert)(unsigned long))
> +{
> + special_reset_num = num;
> + special_reset_assert = assert;
> + special_reset_deassert = deassert;
> +}
> +
I think we could possibly improve this interface somewhat by turning it
upside-down, that is, make SoC-specific drivers call this in a helper
fashion. But this is good enough for now, I can always take a stab at
refactoring if I get bored.
Thierry
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 819 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150519/08befaa1/attachment.sig>
next prev parent reply other threads:[~2015-05-19 14:59 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-13 14:58 [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 01/17] clk: tegra: Add binding for the Tegra124 DFLL clocksource Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 02/17] clk: tegra: Add library for the DFLL clock source (open-loop mode) Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 03/17] clk: tegra: Add closed loop support for the DFLL Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 04/17] clk: tegra: Add functions for parsing CVB tables Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 05/17] clk: tegra: Introduce ability for SoC-specific reset control callbacks Mikko Perttunen
2015-05-19 11:39 ` [PATCH v10 " Mikko Perttunen
2015-05-19 11:46 ` Mikko Perttunen
2015-05-19 14:59 ` Thierry Reding [this message]
2015-05-19 15:06 ` Mikko Perttunen
2015-05-19 15:22 ` Thierry Reding
2015-05-20 6:27 ` [PATCH v11 " Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 06/17] clk: tegra: Add DFLL DVCO reset control for Tegra124 Mikko Perttunen
2015-05-19 11:43 ` [PATCH v10 " Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 07/17] clk: tegra: Add Tegra124 DFLL clocksource platform driver Mikko Perttunen
2015-05-26 18:17 ` Kevin Hilman
2015-05-13 14:58 ` [PATCH v9 08/17] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 09/17] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 10/17] ARM: tegra: Add the DFLL to Tegra124 device tree Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1 Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 12/17] cpufreq: tegra124: Add device tree bindings Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 13/17] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 14/17] cpufreq: Add cpufreq driver for Tegra124 Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 15/17] ARM: tegra: Add entries for cpufreq on Tegra124 Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 16/17] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Mikko Perttunen
2015-05-13 14:58 ` [PATCH v9 17/17] ARM: tegra: enable Tegra124 cpufreq driver by default Mikko Perttunen
2015-05-13 22:47 ` [PATCH v9 00/17] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Rafael J. Wysocki
2015-05-14 6:15 ` Mikko Perttunen
2015-05-14 20:15 ` Rafael J. Wysocki
2015-05-15 2:09 ` Viresh Kumar
2015-05-15 5:16 ` Mikko Perttunen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150519145922.GA28018@ulmo \
--to=thierry.reding@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).