L2 Cache enable on i.MX5

L2 Cache enable on i.MX5

[Robert Daniels]

?I recently discovered an issue with an i.MX53 based product where we had an older version of Das U-Boot which disabled the L2 cache on startup but in a later version would re-enable it once the L2 cache was configured. Since we had the version that did not re-enable it, we run our Linux kernel with the L2 cache disabled.

I'd like to have the Linux kernel enable the L2 cache on initialization - where is the correct place to do this? Currently, I've added it to the initialization assembly in arch/arm/boot/compressed/head.S for the decompress kernel loader to get the cache enabled as soon as possible but I wonder if there's a better place.

Once I get things squared away, I can submit this patch to the list to have it added to the kernel.

Thanks,

Robert Daniels



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L2 Cache enable on i.MX5

[Russell King - ARM Linux]

On Wed, Jun 24, 2015 at 05:10:26PM +0000, Robert Daniels wrote:
> I recently discovered an issue with an i.MX53 based product where we had
> an older version of Das U-Boot which disabled the L2 cache on startup but
> in a later version would re-enable it once the L2 cache was configured.

The kernel is supposed to be booted with caches disabled, and in particular,
the L2 cache disabled during the decompressor run.

If the L2 cache is configured, it will enable it during it's boot sequence.

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L2 Cache enable on i.MX5

[Robert Daniels]

>> I recently discovered an issue with an i.MX53 based product where we had
>> an older version of Das U-Boot which disabled the L2 cache on startup but
>> in a later version would re-enable it once the L2 cache was configured.

> The kernel is supposed to be booted with caches disabled, and in particular,
> the L2 cache disabled during the decompressor run.

> If the L2 cache is configured, it will enable it during it's boot sequence.

I see - so the boot loader is not supposed to enable the L2 cache and it should
not be enabled until after the decompressor runs.

In that case, where should the kernel be enabling the L2 cache? I'm using the
3.14 kernel for this i.MX53 product and the L2 cache is definitely not enabled.

I see that there is a imx_init_l2cache defined which is being called by the imx6
and imx35 platform code but it is not being called for the i.mx5... should it?

Thanks,

Robert Daniels

________________________________

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L2 Cache enable on i.MX5

[Russell King - ARM Linux]

On Wed, Jun 24, 2015 at 10:53:01PM +0000, Robert Daniels wrote:
> 
> >> I recently discovered an issue with an i.MX53 based product where we had
> >> an older version of Das U-Boot which disabled the L2 cache on startup but
> >> in a later version would re-enable it once the L2 cache was configured.
> 
> > The kernel is supposed to be booted with caches disabled, and in particular,
> > the L2 cache disabled during the decompressor run.
> 
> > If the L2 cache is configured, it will enable it during it's boot sequence.
> 
> I see - so the boot loader is not supposed to enable the L2 cache and it
> should not be enabled until after the decompressor runs.
> 
> In that case, where should the kernel be enabling the L2 cache? I'm using
> the 3.14 kernel for this i.MX53 product and the L2 cache is definitely not
> enabled.

I don't know, I don't have any knowledge of iMX35 - all I can do is say
what the generic requirements are of the kernel.

The problem with having the L2 cache enabled when calling into the kernel
is that the decompressor knows nothing of the L2 cache, and doesn't
have the capability to do any cache maintanence there, which it would
need to do.  That adds a _lot_ of extra complexity.

> I see that there is a imx_init_l2cache defined which is being called by
> the imx6 and imx35 platform code but it is not being called for the
> i.mx5... should it?

Searching google, I see there was some discussion on this topic back in
2011, which concluded that the kernel should enable the cache.  However,
as it's now four years later, and you've found that the kernel still
does not enable the cache, the conclusion is that the code has never
been submitted.

The kernel also needs to know not only how to enable the L2 cache, but
how to perform cache maintanence on that cache, so things like DMA will
work (it's no good trying to DMA data to a device when it's sitting in
a CPU cache.)

As the information for the iMX5 doesn't seem to be public (or not in
google's index), I'm not sure who could help you.

If you have some ideas about how to deal with this, the place to go
looking for L2 cache support stuff is arch/arm/mm.  If the cache is
significantly different from the others there, it'd be better to
start a new file rather than trying to merge it into cache-l2x0.c.

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L2 Cache enable on i.MX5

[Enrico Weigelt, metux IT consult]

Am 25.06.2015 um 00:53 schrieb Robert Daniels:

Hi,


> In that case, where should the kernel be enabling the L2 cache? I'm using the
> 3.14 kernel for this i.MX53 product and the L2 cache is definitely not enabled.

I'm working on an mx53, too (tqma53 board), but with an 4.1 kernel.
How can I check whether L2 cache is enabled ?

Can you estimate, how much performance gain we can actually get from the
L2 cache (under which kind of workloads) ?


--mtx

--
Enrico Weigelt, metux IT consult
+49-151-27565287
MELAG Medizintechnik oHG Sitz Berlin Registergericht AG Charlottenburg HRA 21333 B

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L2 Cache enable on i.MX5

[Robert Daniels]

> I'm working on an mx53, too (tqma53 board), but with an 4.1 kernel.
> How can I check whether L2 cache is enabled ?

I discovered our problem by comparing the version of Das U-Boot we are using
with the latest from Freescale's repository. In this comparison, I discovered that
there had been a patch introduced to enable the L2 cache.  The L2 cache enable
patch is also in the mainline U-Boot source too so if you check in this file:
arch/arm/cpu/armv7/mx5/lowlevel_init.S
around line 49 you should see a comment about enabling the L2 cache. If it's there
you're good to go.

> Can you estimate, how much performance gain we can actually get from the
> L2 cache (under which kind of workloads) ?

In our testing we are seeing a 1.5x - 2.0x improvement. Of course, this may not
affect you at all - we just got unlucky and get our bootloader at the wrong time.

- Robert

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L2 Cache enable on i.MX5

[Fabio Estevam]

On Wed, Jun 24, 2015 at 7:53 PM, Robert Daniels
<robert.daniels@vantagecontrols.com> wrote:

> I see - so the boot loader is not supposed to enable the L2 cache and it should
> not be enabled until after the decompressor runs.
>
> In that case, where should the kernel be enabling the L2 cache? I'm using the
> 3.14 kernel for this i.MX53 product and the L2 cache is definitely not enabled.
>
> I see that there is a imx_init_l2cache defined which is being called by the imx6
> and imx35 platform code but it is not being called for the i.mx5... should it?

Should we enable the L2 cache like it is done in Barebox?

--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -25,7 +25,13 @@

 static void __init imx53_init_early(void)
 {
+    unsigned int r;
+
     mxc_set_cpu_type(MXC_CPU_MX53);
+
+    __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r));
+    r |= 1 << 1;     /* enable L2 cache */
+    __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r));
 }

 static void __init imx53_dt_init(void)

Regards,

Fabio Estevam