From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow
Date: Fri, 17 Jul 2015 17:47:49 -0700 [thread overview]
Message-ID: <20150718004749.GV30412@codeaurora.org> (raw)
In-Reply-To: <1436517574-17895-2-git-send-email-jamesjj.liao@mediatek.com>
On 07/10, James Liao wrote:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
>
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
>
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-07-18 0:47 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-10 8:39 [PATCH v3 0/3] Fixes for MT8173 PLLs James Liao
2015-07-10 8:39 ` [PATCH v3 1/3] clk: mediatek: Fix PLL registers setting flow James Liao
2015-07-18 0:47 ` Stephen Boyd [this message]
2015-07-10 8:39 ` [PATCH v3 2/3] clk: mediatek: Fix calculation of PLL rate settings James Liao
2015-07-18 0:47 ` Stephen Boyd
2015-07-10 8:39 ` [PATCH v3 3/3] clk: mediatek: Add MT8173 MMPLL change rate support James Liao
2015-07-18 0:47 ` Stephen Boyd
2015-07-13 5:45 ` [PATCH v3 0/3] Fixes for MT8173 PLLs Sascha Hauer
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