[PATCH 0/6] This series adds SMP support for the MediaTek MT6580.

[PATCH 0/6] This series adds SMP support for the MediaTek MT6580.

[Scott Shu]

This patchset adds support SMP on MediaTek MT6580 Cortex-A7 qual core SoC.

This is based on v4.1-rc1 and following patch series:
(1) Yingjoe Chen's "Add SMP bringup support for mt65xx socs" [1]
(2) Mars Cheng's "Add mt6580 basic chip support" [2]
(3) Sascha Hauer's "Mediatek SCPSYS power domain support" [3]

The secondary cores are power off as default on MT6580, this change adds
a new enable-method to turn on power to the cores during booting process.

The System Power Manager (SPM) inside the SCPSYS is for the CPU MTCMOS
power domain control. Please check [3] for more information about SCPSYS.

[1] https://lkml.org/lkml/2015/5/16/33
[2] https://lkml.org/lkml/2015/6/3/113
[3] https://lkml.org/lkml/2015/6/9/172


Scott Shu (6):
  Document: bindings: DT: Add SMP enable method for MT6580 SoC platform
  soc: Mediatek: Add SCPSYS CPU power domain driver
  ARM: mediatek: add smp bringup code
  ARM: Mediatek: enable GPT6 on boot up to make arch timer working for MT6580
  ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file.
  ARM: dts: mt6580: enable basic SMP bringup for MT6580

 Documentation/devicetree/bindings/arm/cpus.txt |   1 +
 arch/arm/boot/dts/mt6580.dtsi                  |  25 +++
 arch/arm/mach-mediatek/Makefile                |   2 +-
 arch/arm/mach-mediatek/generic.h               |  24 +++
 arch/arm/mach-mediatek/hotplug.c               | 229 +++++++++++++++++++++++++
 arch/arm/mach-mediatek/mediatek.c              |   4 +-
 arch/arm/mach-mediatek/platsmp.c               | 113 +++++++++++-
 7 files changed, 395 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-mediatek/generic.h
 create mode 100644 arch/arm/mach-mediatek/hotplug.c

[PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform

[Scott Shu]

For MT6580 SoC platform, the secondary cores are in powered off state
as default, so compared with MT65xx series SoC, one new enable method
is needed. This method using the SPM (System Power Manager) inside
the SCYSYS to control the CPU power.
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index ac2903d..fb80b2e 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -194,6 +194,7 @@ nodes to be present and contain the properties described below.
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"
 			    "marvell,armada-xp-smp"
+			    "mediatek,mt6580-smp"
 			    "mediatek,mt65xx-smp"
 			    "mediatek,mt81xx-tz-smp"
 			    "qcom,gcc-msm8660"
-- 
1.8.1.1.dirty

[PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Scott Shu]

This adds a CPU power domain driver for the Mediatek SCPSYS unit on
MT6580.
---
 arch/arm/mach-mediatek/Makefile  |   2 +-
 arch/arm/mach-mediatek/generic.h |  24 +++++
 arch/arm/mach-mediatek/hotplug.c | 228 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-mediatek/generic.h
 create mode 100644 arch/arm/mach-mediatek/hotplug.c

diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 2116460..b2e4ef5 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1,4 +1,4 @@
 ifeq ($(CONFIG_SMP),y)
-obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
+obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o hotplug.o
 endif
 obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-mediatek/generic.h b/arch/arm/mach-mediatek/generic.h
new file mode 100644
index 0000000..2a0d0c8
--- /dev/null
+++ b/arch/arm/mach-mediatek/generic.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Mediatek Inc.
+ * Author: Scott Shu <scott.shu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MACH_MTK_COMMON__
+#define __MACH_MTK_COMMON__
+
+#include <linux/kernel.h>
+
+int spm_cpu_mtcmos_init(void);
+int spm_cpu_mtcmos_on(int cpu);
+int spm_cpu_mtcmos_off(int cpu, bool wfi);
+
+#endif
diff --git a/arch/arm/mach-mediatek/hotplug.c b/arch/arm/mach-mediatek/hotplug.c
new file mode 100644
index 0000000..be0305d
--- /dev/null
+++ b/arch/arm/mach-mediatek/hotplug.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2015 Mediatek Inc.
+ * Author: Scott Shu <scott.shu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+
+/* SCPSYS registers */
+#define SPM_POWERON_CONFIG_SET		0x0000
+
+#define SPM_CA7_CPU0_PWR_CON		0x0200
+#define SPM_CA7_CPU1_PWR_CON		0x0218
+#define SPM_CA7_CPU2_PWR_CON		0x021c
+#define SPM_CA7_CPU3_PWR_CON		0x0220
+
+#define SPM_CA7_CPU0_L1_PDN		0x025c
+#define SPM_CA7_CPU1_L1_PDN		0x0264
+#define SPM_CA7_CPU2_L1_PDN		0x026c
+#define SPM_CA7_CPU3_L1_PDN		0x0274
+
+#define SPM_PWR_STATUS			0x060c
+#define SPM_PWR_STATUS_2ND		0x0610
+#define SPM_SLEEP_TIMER_STA		0x0720
+
+/*
+ * bit definition in SPM_CA7_CPUx_PWR_CON
+ */
+#define SRAM_ISOINT_B		BIT(6)
+#define SRAM_CKISO		BIT(5)
+#define PWR_CLK_DIS		BIT(4)
+#define PWR_ON_2ND		BIT(3)
+#define PWR_ON			BIT(2)
+#define PWR_ISO			BIT(1)
+#define PWR_RST_B		BIT(0)
+
+/*
+ * bit definition in SPM_CA7_CPUx_L1_PDN
+ */
+#define L1_PDN_ACK		BIT(8)
+#define L1_PDN			BIT(0)
+
+void __iomem *spm_cpu_base;
+
+u32 spm_cpu_pwr_con[4] = {
+	SPM_CA7_CPU0_PWR_CON,
+	SPM_CA7_CPU1_PWR_CON,
+	SPM_CA7_CPU2_PWR_CON,
+	SPM_CA7_CPU3_PWR_CON,
+};
+
+u32 spm_cpu_l1_pdn[4] = {
+	SPM_CA7_CPU0_L1_PDN,
+	SPM_CA7_CPU1_L1_PDN,
+	SPM_CA7_CPU2_L1_PDN,
+	SPM_CA7_CPU3_L1_PDN,
+};
+
+#define SPM_REGWR_EN		(1U << 0)
+#define SPM_PROJECT_CODE	0x0B16
+
+int spm_cpu_mtcmos_on(int cpu)
+{
+	static DEFINE_SPINLOCK(spm_cpu_lock);
+	unsigned long flags;
+	static u32 spmcpu_pwr_con, spmcpu_l1_pdn;
+	unsigned int temp;
+
+	temp = (SPM_PROJECT_CODE << 16) | SPM_REGWR_EN;
+	writel_relaxed(temp, spm_cpu_base + SPM_POWERON_CONFIG_SET);
+
+	spmcpu_pwr_con = spm_cpu_pwr_con[cpu];
+	spmcpu_l1_pdn = spm_cpu_l1_pdn[cpu];
+
+	spin_lock_irqsave(&spm_cpu_lock, flags);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_ON;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	udelay(1);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_ON_2ND;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	while (((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS) &
+		(1U << (13 - cpu))) != (1U << (13 - cpu))) ||
+		((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS_2ND) &
+		(1U << (13 - cpu))) != (1U << (13 - cpu)))) {
+		;
+	}
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_ISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	/* L1 power on */
+	temp = readl_relaxed(spm_cpu_base + spmcpu_l1_pdn);
+	temp &= ~L1_PDN;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_l1_pdn);
+	while ((readl_relaxed(spm_cpu_base + spmcpu_l1_pdn) &
+		L1_PDN_ACK) != 0)
+		;
+
+	udelay(1);
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= SRAM_ISOINT_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~SRAM_CKISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_CLK_DIS;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_RST_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	spin_unlock_irqrestore(&spm_cpu_lock, flags);
+
+	return 0;
+}
+
+int spm_cpu_mtcmos_off(int cpu, bool wfi)
+{
+	static DEFINE_SPINLOCK(spm_cpu_lock);
+	unsigned long flags;
+	static u32 spmcpu_pwr_con, spmcpu_l1_pdn;
+	unsigned int temp;
+
+	temp = (SPM_PROJECT_CODE << 16) | SPM_REGWR_EN;
+	writel_relaxed(temp, spm_cpu_base + SPM_POWERON_CONFIG_SET);
+
+	spmcpu_pwr_con = spm_cpu_pwr_con[cpu];
+	spmcpu_l1_pdn = spm_cpu_l1_pdn[cpu];
+
+	if (wfi) {
+		while ((readl_relaxed(spm_cpu_base + SPM_SLEEP_TIMER_STA) &
+			(1U << (16 + cpu))) == 0)
+			;
+	}
+
+	spin_lock_irqsave(&spm_cpu_lock, flags);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_ISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= SRAM_CKISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~SRAM_ISOINT_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	/* L1 power off */
+	temp = readl_relaxed(spm_cpu_base + spmcpu_l1_pdn);
+	temp |= L1_PDN;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_l1_pdn);
+	while ((readl_relaxed(spm_cpu_base + spmcpu_l1_pdn)
+		& L1_PDN_ACK) != L1_PDN_ACK)
+		;
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_RST_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_CLK_DIS;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_ON;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_ON_2ND;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	while (((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS) &
+		(1U << (13 - cpu))) != 0) ||
+	       ((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS_2ND) &
+		(1U << (13 - cpu))) != 0))
+		;
+
+	spin_unlock_irqrestore(&spm_cpu_lock, flags);
+
+	return 0;
+}
+
+int spm_cpu_mtcmos_init(void)
+{
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "mediatek,mt6580-scpsys");
+	if (!node) {
+		pr_err("Missing mt6580-scpsys node in the device tree\n");
+		return -EINVAL;
+	}
+
+	spm_cpu_base = of_iomap(node, 0);
+	if (!spm_cpu_base) {
+		pr_err("%s: Unable to map I/O memory\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
-- 
1.8.1.1.dirty

[PATCH 3/6] ARM: mediatek: add smp bringup code for MT6580

[Scott Shu]

Add support for cpu enable-method "mediatek,mt6580-smp" for booting
secondary CPUs on MT6580.
---
 arch/arm/mach-mediatek/platsmp.c | 107 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 12fefb3..2985913 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -21,10 +21,15 @@
 #include <linux/of_address.h>
 #include <linux/string.h>
 #include <linux/threads.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+#include "generic.h"
 
 #define MTK_MAX_CPU		8
 #define MTK_SMP_REG_SIZE	0x1000
 
+static DEFINE_SPINLOCK(boot_lock);
+
 struct mtk_smp_boot_info {
 	unsigned long smp_base;
 	unsigned int jump_reg;
@@ -57,6 +62,101 @@ static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
 static void __iomem *mtk_smp_base;
 static const struct mtk_smp_boot_info *mtk_smp_info;
 
+static void __cpuinit write_pen_release(int val)
+{
+	pen_release = val;
+	/* Make sure this is visible to other CPUs */
+	smp_wmb();
+	sync_cache_w(&pen_release);
+}
+
+static int mt6580_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	write_pen_release(cpu);
+
+	/*
+	 * CPU power on control by SPM
+	 */
+	spm_cpu_mtcmos_on(cpu);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		/* Read barrier */
+		smp_rmb();
+
+		if (pen_release == -1)
+			break;
+
+		usleep_range(10, 1000);
+	}
+
+	/*
+	 * Now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return (pen_release != -1 ? -EINVAL : 0);
+}
+
+static void mt6580_secondary_init(unsigned int cpu)
+{
+	/*
+	 * Let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+#define MT6580_INFRACFG_AO	0x10001000
+#define SW_ROM_PD		BIT(31)
+
+static void __init mt6580_smp_prepare_cpus(unsigned int max_cpus)
+{
+	static void __iomem *infracfg_ao_base;
+
+	infracfg_ao_base = ioremap(MT6580_INFRACFG_AO, 0x1000);
+
+	if (!infracfg_ao_base)
+		pr_err("%s: Unable to map I/O memory\n", __func__);
+
+	/* Enable bootrom power down mode */
+	writel_relaxed(readl(infracfg_ao_base + 0x804) | SW_ROM_PD,
+		       infracfg_ao_base + 0x804);
+
+	/* Write the address of slave startup into boot address
+	   register for bootrom power down mode */
+	writel_relaxed(virt_to_phys(secondary_startup_arm),
+		       infracfg_ao_base + 0x800);
+
+	iounmap(infracfg_ao_base);
+
+	/* Initial spm cpu mtcmos memory map */
+	spm_cpu_mtcmos_init();
+}
+
 static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	if (!mtk_smp_base)
@@ -143,3 +243,10 @@ static struct smp_operations mt65xx_smp_ops __initdata = {
 	.smp_boot_secondary = mtk_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(mt65xx_smp, "mediatek,mt65xx-smp", &mt65xx_smp_ops);
+
+static struct smp_operations mt6580_smp_ops __initdata = {
+	.smp_prepare_cpus = mt6580_smp_prepare_cpus,
+	.smp_secondary_init = mt6580_secondary_init,
+	.smp_boot_secondary = mt6580_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(mt6580_smp, "mediatek,mt6580-smp", &mt6580_smp_ops);
-- 
1.8.1.1.dirty

[PATCH 4/6] ARM: Mediatek: enable GPT6 on boot up to make arch timer working for MT6580

[Scott Shu]

We enable GTP6 which ungates the arch timer clock.
---
 arch/arm/mach-mediatek/mediatek.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index 6b38d67..469d332 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -28,7 +28,8 @@ static void __init mediatek_timer_init(void)
 {
 	void __iomem *gpt_base = 0;
 
-	if (of_machine_is_compatible("mediatek,mt6589") ||
+	if (of_machine_is_compatible("mediatek,mt6580") ||
+	    of_machine_is_compatible("mediatek,mt6589") ||
 	    of_machine_is_compatible("mediatek,mt8135") ||
 	    of_machine_is_compatible("mediatek,mt8127")) {
 		/* turn on GPT6 which ungates arch timer clocks */
@@ -46,6 +47,7 @@ static void __init mediatek_timer_init(void)
 };
 
 static const char * const mediatek_board_dt_compat[] = {
+	"mediatek,mt6580",
 	"mediatek,mt6589",
 	"mediatek,mt6592",
 	"mediatek,mt8127",
-- 
1.8.1.1.dirty

[PATCH 5/6] ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file

[Scott Shu]

This adds the SCPSYS device node to the MT6580 dtsi file.
---
 arch/arm/boot/dts/mt6580.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index ae3cdb6..a974830 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -78,6 +78,11 @@
 		compatible = "simple-bus";
 		ranges;
 
+		scpsys: scpsys at 10006000 {
+			compatible = "mediatek,mt6580-scpsys";
+			reg = <0x10006000 0x1000>;
+		};
+
 		timer: timer at 10008000 {
 			compatible = "mediatek,mt6580-timer", "mediatek,mt6577-timer";
 			reg = <0x10008000 0x80>;
-- 
1.8.1.1.dirty

[PATCH 6/6] ARM: dts: mt6580: enable basic SMP bringup for mt6580

[Scott Shu]

Add arch timer node to enable arch-timer support. MT6580 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.

This set cpu enable-method to enable SMP.
---
 arch/arm/boot/dts/mt6580.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index a974830..a7071b38 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -23,26 +23,31 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "mediatek,mt6580-smp";
 
 		cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x0>;
+			clock-frequency = <1700000000>;
 		};
 		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x1>;
+			clock-frequency = <1700000000>;
 		};
 		cpu at 2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x2>;
+			clock-frequency = <1700000000>;
 		};
 		cpu at 3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x3>;
+			clock-frequency = <1700000000>;
 		};
 
 	};
@@ -72,6 +77,21 @@
 		};
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <13000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.8.1.1.dirty

[RESEND PATCH 0/6] This series adds SMP support for the MediaTek MT6580.

[Scott Shu]

This patchset adds support SMP on MediaTek MT6580 Cortex-A7 qual core SoC.

This is based on v4.1-rc1 and following patch series:
(1) Yingjoe Chen's "Add SMP bringup support for mt65xx socs" [1]
(2) Mars Cheng's "Add mt6580 basic chip support" [2]
(3) Sascha Hauer's "Mediatek SCPSYS power domain support" [3]

The secondary cores are power off as default on MT6580, this change adds
a new enable-method to turn on power to the cores during booting process.

The System Power Manager (SPM) inside the SCPSYS is for the CPU MTCMOS
power domain control. Please check [3] for more information about SCPSYS.

[1] https://lkml.org/lkml/2015/5/16/33
[2] https://lkml.org/lkml/2015/6/3/113
[3] https://lkml.org/lkml/2015/6/9/172


Scott Shu (6):
  Document: bindings: DT: Add SMP enable method for MT6580 SoC platform
  soc: Mediatek: Add SCPSYS CPU power domain driver
  ARM: mediatek: add smp bringup code
  ARM: Mediatek: enable GPT6 on boot up to make arch timer working for MT6580
  ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file.
  ARM: dts: mt6580: enable basic SMP bringup for MT6580

 Documentation/devicetree/bindings/arm/cpus.txt |   1 +
 arch/arm/boot/dts/mt6580.dtsi                  |  25 +++
 arch/arm/mach-mediatek/Makefile                |   2 +-
 arch/arm/mach-mediatek/generic.h               |  24 +++
 arch/arm/mach-mediatek/hotplug.c               | 229 +++++++++++++++++++++++++
 arch/arm/mach-mediatek/mediatek.c              |   4 +-
 arch/arm/mach-mediatek/platsmp.c               | 113 +++++++++++-
 7 files changed, 395 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/mach-mediatek/generic.h
 create mode 100644 arch/arm/mach-mediatek/hotplug.c

[RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform

[Scott Shu]

For MT6580 SoC platform, the secondary cores are in powered off state
as default, so compared with MT65xx series SoC, one new enable method
is needed. This method using the SPM (System Power Manager) inside
the SCYSYS to control the CPU power.
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index ac2903d..fb80b2e 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -194,6 +194,7 @@ nodes to be present and contain the properties described below.
 			    "marvell,armada-380-smp"
 			    "marvell,armada-390-smp"
 			    "marvell,armada-xp-smp"
+			    "mediatek,mt6580-smp"
 			    "mediatek,mt65xx-smp"
 			    "mediatek,mt81xx-tz-smp"
 			    "qcom,gcc-msm8660"
-- 
1.8.1.1.dirty

[RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform

[Yingjoe Chen]

On Fri, 2015-06-19 at 02:01 +0800, Scott Shu wrote:
> For MT6580 SoC platform, the secondary cores are in powered off state
> as default, so compared with MT65xx series SoC, one new enable method
> is needed. This method using the SPM (System Power Manager) inside
> the SCYSYS to control the CPU power.
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index ac2903d..fb80b2e 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -194,6 +194,7 @@ nodes to be present and contain the properties described below.
>  			    "marvell,armada-380-smp"
>  			    "marvell,armada-390-smp"
>  			    "marvell,armada-xp-smp"
> +			    "mediatek,mt6580-smp"
>  			    "mediatek,mt65xx-smp"
>  			    "mediatek,mt81xx-tz-smp"
>  			    "qcom,gcc-msm8660"

Hi

It seems we have 3 different kinds of cpu enable method now, and
mt65xx-smp doesn't cover all mt65xx series. So maybe it make sense to
change naming before it got merged.

Short summary for these methods:

mt65xx-smp:    	For mt65xx socs which wakeup all cores at boot.
		Tested on mt6589 by Matthias.
mt6580-smp:     Only first core is alive at boot, so need to wakeup
		other cores using SPM. AFAIK only for mt6580 now.
mt81xx-tz-smp:  For soc which wakeup all cores at boot, and have
		trustzone firmware. Suitable for mt8127, mt8135.

I'm not sure about smp for mt6592, maybe Howard or Scott can comment on
it.

Any suggestion on how we should organize these methods?

Joe.C

[RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform

[Yingjoe Chen]

On Mon, 2015-06-29 at 11:03 +0800, Yingjoe Chen wrote:
> On Fri, 2015-06-19 at 02:01 +0800, Scott Shu wrote:
> > For MT6580 SoC platform, the secondary cores are in powered off state
> > as default, so compared with MT65xx series SoC, one new enable method
> > is needed. This method using the SPM (System Power Manager) inside
> > the SCYSYS to control the CPU power.
> > ---
> >  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> > index ac2903d..fb80b2e 100644
> > --- a/Documentation/devicetree/bindings/arm/cpus.txt
> > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > @@ -194,6 +194,7 @@ nodes to be present and contain the properties described below.
> >  			    "marvell,armada-380-smp"
> >  			    "marvell,armada-390-smp"
> >  			    "marvell,armada-xp-smp"
> > +			    "mediatek,mt6580-smp"
> >  			    "mediatek,mt65xx-smp"
> >  			    "mediatek,mt81xx-tz-smp"
> >  			    "qcom,gcc-msm8660"
> 
> Hi
> 
> It seems we have 3 different kinds of cpu enable method now, and
> mt65xx-smp doesn't cover all mt65xx series. So maybe it make sense to
> change naming before it got merged.
> 
> Short summary for these methods:
> 
> mt65xx-smp:    	For mt65xx socs which wakeup all cores at boot.
> 		Tested on mt6589 by Matthias.
> mt6580-smp:     Only first core is alive at boot, so need to wakeup
> 		other cores using SPM. AFAIK only for mt6580 now.
> mt81xx-tz-smp:  For soc which wakeup all cores at boot, and have
> 		trustzone firmware. Suitable for mt8127, mt8135.


Hi Matthias, Arnd,

Any suggestion on the naming? Is it ok if I just rename mt65xx-smp to
mt6589-smp since that's the only one we tested?

Joe.C

[RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform

[Matthias Brugger]

On Saturday, July 11, 2015 06:38:06 PM Yingjoe Chen wrote:
> On Mon, 2015-06-29 at 11:03 +0800, Yingjoe Chen wrote:
> > On Fri, 2015-06-19 at 02:01 +0800, Scott Shu wrote:
> > > For MT6580 SoC platform, the secondary cores are in powered off state
> > > as default, so compared with MT65xx series SoC, one new enable method
> > > is needed. This method using the SPM (System Power Manager) inside
> > > the SCYSYS to control the CPU power.
> > > ---
> > > 
> > >  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
> > > b/Documentation/devicetree/bindings/arm/cpus.txt index ac2903d..fb80b2e
> > > 100644
> > > --- a/Documentation/devicetree/bindings/arm/cpus.txt
> > > +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> > > @@ -194,6 +194,7 @@ nodes to be present and contain the properties
> > > described below.> > 
> > >  			    "marvell,armada-380-smp"
> > >  			    "marvell,armada-390-smp"
> > >  			    "marvell,armada-xp-smp"
> > > 
> > > +			    "mediatek,mt6580-smp"
> > > 
> > >  			    "mediatek,mt65xx-smp"
> > >  			    "mediatek,mt81xx-tz-smp"
> > >  			    "qcom,gcc-msm8660"
> > 
> > Hi
> > 
> > It seems we have 3 different kinds of cpu enable method now, and
> > mt65xx-smp doesn't cover all mt65xx series. So maybe it make sense to
> > change naming before it got merged.
> > 
> > Short summary for these methods:
> > 
> > mt65xx-smp:    	For mt65xx socs which wakeup all cores at boot.
> > 
> > 		Tested on mt6589 by Matthias.
> > 
> > mt6580-smp:     Only first core is alive at boot, so need to wakeup
> > 
> > 		other cores using SPM. AFAIK only for mt6580 now.
> > 
> > mt81xx-tz-smp:  For soc which wakeup all cores at boot, and have
> > 
> > 		trustzone firmware. Suitable for mt8127, mt8135.
> 
> Hi Matthias, Arnd,
> 
> Any suggestion on the naming? Is it ok if I just rename mt65xx-smp to
> mt6589-smp since that's the only one we tested?
> 

Yes, that's fine for me.

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Scott Shu]

This adds a CPU power domain driver for the Mediatek SCPSYS unit on
MT6580.
---
 arch/arm/mach-mediatek/Makefile  |   2 +-
 arch/arm/mach-mediatek/generic.h |  24 +++++
 arch/arm/mach-mediatek/hotplug.c | 228 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-mediatek/generic.h
 create mode 100644 arch/arm/mach-mediatek/hotplug.c

diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 2116460..b2e4ef5 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -1,4 +1,4 @@
 ifeq ($(CONFIG_SMP),y)
-obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
+obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o hotplug.o
 endif
 obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
diff --git a/arch/arm/mach-mediatek/generic.h b/arch/arm/mach-mediatek/generic.h
new file mode 100644
index 0000000..2a0d0c8
--- /dev/null
+++ b/arch/arm/mach-mediatek/generic.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2015 Mediatek Inc.
+ * Author: Scott Shu <scott.shu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __MACH_MTK_COMMON__
+#define __MACH_MTK_COMMON__
+
+#include <linux/kernel.h>
+
+int spm_cpu_mtcmos_init(void);
+int spm_cpu_mtcmos_on(int cpu);
+int spm_cpu_mtcmos_off(int cpu, bool wfi);
+
+#endif
diff --git a/arch/arm/mach-mediatek/hotplug.c b/arch/arm/mach-mediatek/hotplug.c
new file mode 100644
index 0000000..be0305d
--- /dev/null
+++ b/arch/arm/mach-mediatek/hotplug.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2015 Mediatek Inc.
+ * Author: Scott Shu <scott.shu@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+
+/* SCPSYS registers */
+#define SPM_POWERON_CONFIG_SET		0x0000
+
+#define SPM_CA7_CPU0_PWR_CON		0x0200
+#define SPM_CA7_CPU1_PWR_CON		0x0218
+#define SPM_CA7_CPU2_PWR_CON		0x021c
+#define SPM_CA7_CPU3_PWR_CON		0x0220
+
+#define SPM_CA7_CPU0_L1_PDN		0x025c
+#define SPM_CA7_CPU1_L1_PDN		0x0264
+#define SPM_CA7_CPU2_L1_PDN		0x026c
+#define SPM_CA7_CPU3_L1_PDN		0x0274
+
+#define SPM_PWR_STATUS			0x060c
+#define SPM_PWR_STATUS_2ND		0x0610
+#define SPM_SLEEP_TIMER_STA		0x0720
+
+/*
+ * bit definition in SPM_CA7_CPUx_PWR_CON
+ */
+#define SRAM_ISOINT_B		BIT(6)
+#define SRAM_CKISO		BIT(5)
+#define PWR_CLK_DIS		BIT(4)
+#define PWR_ON_2ND		BIT(3)
+#define PWR_ON			BIT(2)
+#define PWR_ISO			BIT(1)
+#define PWR_RST_B		BIT(0)
+
+/*
+ * bit definition in SPM_CA7_CPUx_L1_PDN
+ */
+#define L1_PDN_ACK		BIT(8)
+#define L1_PDN			BIT(0)
+
+void __iomem *spm_cpu_base;
+
+u32 spm_cpu_pwr_con[4] = {
+	SPM_CA7_CPU0_PWR_CON,
+	SPM_CA7_CPU1_PWR_CON,
+	SPM_CA7_CPU2_PWR_CON,
+	SPM_CA7_CPU3_PWR_CON,
+};
+
+u32 spm_cpu_l1_pdn[4] = {
+	SPM_CA7_CPU0_L1_PDN,
+	SPM_CA7_CPU1_L1_PDN,
+	SPM_CA7_CPU2_L1_PDN,
+	SPM_CA7_CPU3_L1_PDN,
+};
+
+#define SPM_REGWR_EN		(1U << 0)
+#define SPM_PROJECT_CODE	0x0B16
+
+int spm_cpu_mtcmos_on(int cpu)
+{
+	static DEFINE_SPINLOCK(spm_cpu_lock);
+	unsigned long flags;
+	static u32 spmcpu_pwr_con, spmcpu_l1_pdn;
+	unsigned int temp;
+
+	temp = (SPM_PROJECT_CODE << 16) | SPM_REGWR_EN;
+	writel_relaxed(temp, spm_cpu_base + SPM_POWERON_CONFIG_SET);
+
+	spmcpu_pwr_con = spm_cpu_pwr_con[cpu];
+	spmcpu_l1_pdn = spm_cpu_l1_pdn[cpu];
+
+	spin_lock_irqsave(&spm_cpu_lock, flags);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_ON;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	udelay(1);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_ON_2ND;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	while (((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS) &
+		(1U << (13 - cpu))) != (1U << (13 - cpu))) ||
+		((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS_2ND) &
+		(1U << (13 - cpu))) != (1U << (13 - cpu)))) {
+		;
+	}
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_ISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	/* L1 power on */
+	temp = readl_relaxed(spm_cpu_base + spmcpu_l1_pdn);
+	temp &= ~L1_PDN;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_l1_pdn);
+	while ((readl_relaxed(spm_cpu_base + spmcpu_l1_pdn) &
+		L1_PDN_ACK) != 0)
+		;
+
+	udelay(1);
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= SRAM_ISOINT_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~SRAM_CKISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_CLK_DIS;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_RST_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	spin_unlock_irqrestore(&spm_cpu_lock, flags);
+
+	return 0;
+}
+
+int spm_cpu_mtcmos_off(int cpu, bool wfi)
+{
+	static DEFINE_SPINLOCK(spm_cpu_lock);
+	unsigned long flags;
+	static u32 spmcpu_pwr_con, spmcpu_l1_pdn;
+	unsigned int temp;
+
+	temp = (SPM_PROJECT_CODE << 16) | SPM_REGWR_EN;
+	writel_relaxed(temp, spm_cpu_base + SPM_POWERON_CONFIG_SET);
+
+	spmcpu_pwr_con = spm_cpu_pwr_con[cpu];
+	spmcpu_l1_pdn = spm_cpu_l1_pdn[cpu];
+
+	if (wfi) {
+		while ((readl_relaxed(spm_cpu_base + SPM_SLEEP_TIMER_STA) &
+			(1U << (16 + cpu))) == 0)
+			;
+	}
+
+	spin_lock_irqsave(&spm_cpu_lock, flags);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_ISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= SRAM_CKISO;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~SRAM_ISOINT_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	/* L1 power off */
+	temp = readl_relaxed(spm_cpu_base + spmcpu_l1_pdn);
+	temp |= L1_PDN;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_l1_pdn);
+	while ((readl_relaxed(spm_cpu_base + spmcpu_l1_pdn)
+		& L1_PDN_ACK) != L1_PDN_ACK)
+		;
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_RST_B;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp |= PWR_CLK_DIS;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_ON;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	temp = readl_relaxed(spm_cpu_base + spmcpu_pwr_con);
+	temp &= ~PWR_ON_2ND;
+	writel_relaxed(temp, spm_cpu_base + spmcpu_pwr_con);
+
+	while (((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS) &
+		(1U << (13 - cpu))) != 0) ||
+	       ((readl_relaxed(spm_cpu_base + SPM_PWR_STATUS_2ND) &
+		(1U << (13 - cpu))) != 0))
+		;
+
+	spin_unlock_irqrestore(&spm_cpu_lock, flags);
+
+	return 0;
+}
+
+int spm_cpu_mtcmos_init(void)
+{
+	struct device_node *node;
+
+	node = of_find_compatible_node(NULL, NULL, "mediatek,mt6580-scpsys");
+	if (!node) {
+		pr_err("Missing mt6580-scpsys node in the device tree\n");
+		return -EINVAL;
+	}
+
+	spm_cpu_base = of_iomap(node, 0);
+	if (!spm_cpu_base) {
+		pr_err("%s: Unable to map I/O memory\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
-- 
1.8.1.1.dirty

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Sascha Hauer]

Hi Scott,

On Fri, Jun 19, 2015 at 02:01:17AM +0800, Scott Shu wrote:
> This adds a CPU power domain driver for the Mediatek SCPSYS unit on
> MT6580.

This seems to be support for the very same hardware as I am posting
here:

https://lkml.org/lkml/2015/6/22/41

We should consolidate this.

My driver is currently handles all power domains except the CPUs while
yours handles only the CPUs.
I currently haven't looked whether CPUs can just be part of a power
domain aswell, but if that works this would probably be the way to go.

Sascha


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Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Scott Shu]

Hi Sascha,
   I just wonder can we separate the MTCMOS into cpu and non-cpu part? 
Just like qcom's xcc driver, they put cpu related code under
"arch/arm/mach-xxx" but put the others under "driver".

Thanks,
Scott  

On Tue, 2015-06-23 at 07:53 +0200, Sascha Hauer wrote:
> Hi Scott,
> 
> On Fri, Jun 19, 2015 at 02:01:17AM +0800, Scott Shu wrote:
> > This adds a CPU power domain driver for the Mediatek SCPSYS unit on
> > MT6580.
> 
> This seems to be support for the very same hardware as I am posting
> here:
> 
> https://lkml.org/lkml/2015/6/22/41
> 
> We should consolidate this.
> 
> My driver is currently handles all power domains except the CPUs while
> yours handles only the CPUs.
> I currently haven't looked whether CPUs can just be part of a power
> domain aswell, but if that works this would probably be the way to go.
> 
> Sascha
> 
> 

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Scott Shu]

On Tue, 2015-06-23 at 07:53 +0200, Sascha Hauer wrote:
> Hi Scott,
> 
> On Fri, Jun 19, 2015 at 02:01:17AM +0800, Scott Shu wrote:
> > This adds a CPU power domain driver for the Mediatek SCPSYS unit on
> > MT6580.
> 
> This seems to be support for the very same hardware as I am posting
> here:
> 
> https://lkml.org/lkml/2015/6/22/41
> 
> We should consolidate this.
> 
> My driver is currently handles all power domains except the CPUs while
> yours handles only the CPUs.
> I currently haven't looked whether CPUs can just be part of a power
> domain aswell, but if that works this would probably be the way to go.
> 
> Sascha
> 
> 
Hi Sascga,

We had posted new patch set in following link, but still keep our
original framework.
http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001498.html

As we mentioned in the new email thread, the SMP operations (smp_boot_secondary)
will be executed before registering the scpsys_drv driver, so the CPUs power
domain is controlled on arch/arm/mach-$(MACHINE) directory. 

Please kindly provide your comments and suggestion. Thank you very much. 

Best Regards,
Scott Shu

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Sascha Hauer]

On Fri, Jul 24, 2015 at 10:02:03AM +0800, Scott Shu wrote:
> On Tue, 2015-06-23 at 07:53 +0200, Sascha Hauer wrote:
> > Hi Scott,
> > 
> > On Fri, Jun 19, 2015 at 02:01:17AM +0800, Scott Shu wrote:
> > > This adds a CPU power domain driver for the Mediatek SCPSYS unit on
> > > MT6580.
> > 
> > This seems to be support for the very same hardware as I am posting
> > here:
> > 
> > https://lkml.org/lkml/2015/6/22/41
> > 
> > We should consolidate this.
> > 
> > My driver is currently handles all power domains except the CPUs while
> > yours handles only the CPUs.
> > I currently haven't looked whether CPUs can just be part of a power
> > domain aswell, but if that works this would probably be the way to go.
> > 
> > Sascha
> > 
> > 
> Hi Sascga,
> 
> We had posted new patch set in following link, but still keep our
> original framework.
> http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001498.html
> 
> As we mentioned in the new email thread, the SMP operations (smp_boot_secondary)
> will be executed before registering the scpsys_drv driver, so the CPUs power
> domain is controlled on arch/arm/mach-$(MACHINE) directory. 
> 
> Please kindly provide your comments and suggestion. Thank you very much.

I think that instead of explaining why have to duplicate the code you
should rather search for ways how the code can be shared. Yes, we'll
need a second (early) entry point to the driver. Maybe we even have to
create the shared code which is then called from the driver and your
early architecture code.
You'll probably have to do this separation between early code and
regular driver code in your driver anyway, since I bet the MT6580 also
has some power domains which shall be controlled by the regular Linux
power domain code later. Also we probably could control the CPU power
domains for the MT8173 in the SCPSYS driver aswell, we just don't have
to because we use PSCI there. You see we are approaching the same
problem from two different corners. Let's find a way to share the code.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Scott Shu]

On Fri, 2015-07-24 at 07:50 +0200, Sascha Hauer wrote:
> On Fri, Jul 24, 2015 at 10:02:03AM +0800, Scott Shu wrote:
> > On Tue, 2015-06-23 at 07:53 +0200, Sascha Hauer wrote:
> > > Hi Scott,
> > > 
> > > On Fri, Jun 19, 2015 at 02:01:17AM +0800, Scott Shu wrote:
> > > > This adds a CPU power domain driver for the Mediatek SCPSYS unit on
> > > > MT6580.
> > > 
> > > This seems to be support for the very same hardware as I am posting
> > > here:
> > > 
> > > https://lkml.org/lkml/2015/6/22/41
> > > 
> > > We should consolidate this.
> > > 
> > > My driver is currently handles all power domains except the CPUs while
> > > yours handles only the CPUs.
> > > I currently haven't looked whether CPUs can just be part of a power
> > > domain aswell, but if that works this would probably be the way to go.
> > > 
> > > Sascha
> > > 
> > > 
> > Hi Sascga,
> > 
> > We had posted new patch set in following link, but still keep our
> > original framework.
> > http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001498.html
> > 
> > As we mentioned in the new email thread, the SMP operations (smp_boot_secondary)
> > will be executed before registering the scpsys_drv driver, so the CPUs power
> > domain is controlled on arch/arm/mach-$(MACHINE) directory. 
> > 
> > Please kindly provide your comments and suggestion. Thank you very much.
> 
> I think that instead of explaining why have to duplicate the code you
> should rather search for ways how the code can be shared. Yes, we'll
> need a second (early) entry point to the driver. Maybe we even have to
> create the shared code which is then called from the driver and your
> early architecture code.
> You'll probably have to do this separation between early code and
> regular driver code in your driver anyway, since I bet the MT6580 also
> has some power domains which shall be controlled by the regular Linux
> power domain code later. Also we probably could control the CPU power
> domains for the MT8173 in the SCPSYS driver aswell, we just don't have
> to because we use PSCI there. You see we are approaching the same
> problem from two different corners. Let's find a way to share the code.
> 
> Sascha
> 
Hi Sascha,
   Thanks. OK, we move all CPU MTCMOS driver from hotplug.c to
mtk-scpsys.c and the test is passed. Next, we need spend some time to
integrate the code better.

Scott

[RESEND PATCH 2/6] soc: Mediatek: Add SCPSYS CPU power domain driver

[Matthias Brugger]

On Saturday, July 25, 2015 05:13:00 PM Scott Shu wrote:
> On Fri, 2015-07-24 at 07:50 +0200, Sascha Hauer wrote:
> > On Fri, Jul 24, 2015 at 10:02:03AM +0800, Scott Shu wrote:
> > > On Tue, 2015-06-23 at 07:53 +0200, Sascha Hauer wrote:
> > > > Hi Scott,
> > > > 
> > > > On Fri, Jun 19, 2015 at 02:01:17AM +0800, Scott Shu wrote:
> > > > > This adds a CPU power domain driver for the Mediatek SCPSYS unit on
> > > > > MT6580.
> > > > 
> > > > This seems to be support for the very same hardware as I am posting
> > > > here:
> > > > 
> > > > https://lkml.org/lkml/2015/6/22/41
> > > > 
> > > > We should consolidate this.
> > > > 
> > > > My driver is currently handles all power domains except the CPUs while
> > > > yours handles only the CPUs.
> > > > I currently haven't looked whether CPUs can just be part of a power
> > > > domain aswell, but if that works this would probably be the way to go.
> > > > 
> > > > Sascha
> > > 
> > > Hi Sascga,
> > > 
> > > We had posted new patch set in following link, but still keep our
> > > original framework.
> > > http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001498.htm
> > > l
> > > 
> > > As we mentioned in the new email thread, the SMP operations
> > > (smp_boot_secondary) will be executed before registering the scpsys_drv
> > > driver, so the CPUs power domain is controlled on
> > > arch/arm/mach-$(MACHINE) directory.
> > > 
> > > Please kindly provide your comments and suggestion. Thank you very much.
> > 
> > I think that instead of explaining why have to duplicate the code you
> > should rather search for ways how the code can be shared. Yes, we'll
> > need a second (early) entry point to the driver. Maybe we even have to
> > create the shared code which is then called from the driver and your
> > early architecture code.
> > You'll probably have to do this separation between early code and
> > regular driver code in your driver anyway, since I bet the MT6580 also
> > has some power domains which shall be controlled by the regular Linux
> > power domain code later. Also we probably could control the CPU power
> > domains for the MT8173 in the SCPSYS driver aswell, we just don't have
> > to because we use PSCI there. You see we are approaching the same
> > problem from two different corners. Let's find a way to share the code.
> > 
> > Sascha
> 
> Hi Sascha,
>    Thanks. OK, we move all CPU MTCMOS driver from hotplug.c to
> mtk-scpsys.c and the test is passed. Next, we need spend some time to
> integrate the code better.
> 

Good to hear that. We should try to keep mach-mediatek code a little as 
possible.

Cheers,
Matthias

[RESEND PATCH 3/6] ARM: mediatek: add smp bringup code for MT6580

[Scott Shu]

Add support for cpu enable-method "mediatek,mt6580-smp" for booting
secondary CPUs on MT6580.
---
 arch/arm/mach-mediatek/platsmp.c | 107 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 12fefb3..2985913 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -21,10 +21,15 @@
 #include <linux/of_address.h>
 #include <linux/string.h>
 #include <linux/threads.h>
+#include <linux/delay.h>
+#include <asm/cacheflush.h>
+#include "generic.h"
 
 #define MTK_MAX_CPU		8
 #define MTK_SMP_REG_SIZE	0x1000
 
+static DEFINE_SPINLOCK(boot_lock);
+
 struct mtk_smp_boot_info {
 	unsigned long smp_base;
 	unsigned int jump_reg;
@@ -57,6 +62,101 @@ static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
 static void __iomem *mtk_smp_base;
 static const struct mtk_smp_boot_info *mtk_smp_info;
 
+static void __cpuinit write_pen_release(int val)
+{
+	pen_release = val;
+	/* Make sure this is visible to other CPUs */
+	smp_wmb();
+	sync_cache_w(&pen_release);
+}
+
+static int mt6580_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	write_pen_release(cpu);
+
+	/*
+	 * CPU power on control by SPM
+	 */
+	spm_cpu_mtcmos_on(cpu);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		/* Read barrier */
+		smp_rmb();
+
+		if (pen_release == -1)
+			break;
+
+		usleep_range(10, 1000);
+	}
+
+	/*
+	 * Now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return (pen_release != -1 ? -EINVAL : 0);
+}
+
+static void mt6580_secondary_init(unsigned int cpu)
+{
+	/*
+	 * Let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	write_pen_release(-1);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+#define MT6580_INFRACFG_AO	0x10001000
+#define SW_ROM_PD		BIT(31)
+
+static void __init mt6580_smp_prepare_cpus(unsigned int max_cpus)
+{
+	static void __iomem *infracfg_ao_base;
+
+	infracfg_ao_base = ioremap(MT6580_INFRACFG_AO, 0x1000);
+
+	if (!infracfg_ao_base)
+		pr_err("%s: Unable to map I/O memory\n", __func__);
+
+	/* Enable bootrom power down mode */
+	writel_relaxed(readl(infracfg_ao_base + 0x804) | SW_ROM_PD,
+		       infracfg_ao_base + 0x804);
+
+	/* Write the address of slave startup into boot address
+	   register for bootrom power down mode */
+	writel_relaxed(virt_to_phys(secondary_startup_arm),
+		       infracfg_ao_base + 0x800);
+
+	iounmap(infracfg_ao_base);
+
+	/* Initial spm cpu mtcmos memory map */
+	spm_cpu_mtcmos_init();
+}
+
 static int mtk_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	if (!mtk_smp_base)
@@ -143,3 +243,10 @@ static struct smp_operations mt65xx_smp_ops __initdata = {
 	.smp_boot_secondary = mtk_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(mt65xx_smp, "mediatek,mt65xx-smp", &mt65xx_smp_ops);
+
+static struct smp_operations mt6580_smp_ops __initdata = {
+	.smp_prepare_cpus = mt6580_smp_prepare_cpus,
+	.smp_secondary_init = mt6580_secondary_init,
+	.smp_boot_secondary = mt6580_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(mt6580_smp, "mediatek,mt6580-smp", &mt6580_smp_ops);
-- 
1.8.1.1.dirty

[RESEND PATCH 4/6] ARM: Mediatek: enable GPT6 on boot up to make arch timer working for MT6580

[Scott Shu]

We enable GTP6 which ungates the arch timer clock.
---
 arch/arm/mach-mediatek/mediatek.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index 6b38d67..469d332 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -28,7 +28,8 @@ static void __init mediatek_timer_init(void)
 {
 	void __iomem *gpt_base = 0;
 
-	if (of_machine_is_compatible("mediatek,mt6589") ||
+	if (of_machine_is_compatible("mediatek,mt6580") ||
+	    of_machine_is_compatible("mediatek,mt6589") ||
 	    of_machine_is_compatible("mediatek,mt8135") ||
 	    of_machine_is_compatible("mediatek,mt8127")) {
 		/* turn on GPT6 which ungates arch timer clocks */
@@ -46,6 +47,7 @@ static void __init mediatek_timer_init(void)
 };
 
 static const char * const mediatek_board_dt_compat[] = {
+	"mediatek,mt6580",
 	"mediatek,mt6589",
 	"mediatek,mt6592",
 	"mediatek,mt8127",
-- 
1.8.1.1.dirty

[RESEND PATCH 5/6] ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file

[Scott Shu]

This adds the SCPSYS device node to the MT6580 dtsi file.
---
 arch/arm/boot/dts/mt6580.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index ae3cdb6..a974830 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -78,6 +78,11 @@
 		compatible = "simple-bus";
 		ranges;
 
+		scpsys: scpsys at 10006000 {
+			compatible = "mediatek,mt6580-scpsys";
+			reg = <0x10006000 0x1000>;
+		};
+
 		timer: timer at 10008000 {
 			compatible = "mediatek,mt6580-timer", "mediatek,mt6577-timer";
 			reg = <0x10008000 0x80>;
-- 
1.8.1.1.dirty

[RESEND PATCH 6/6] ARM: dts: mt6580: enable basic SMP bringup for mt6580

[Scott Shu]

Add arch timer node to enable arch-timer support. MT6580 firmware
doesn't correctly setup arch-timer frequency and CNTVOFF, add
properties to workaround this.

This set cpu enable-method to enable SMP.
---
 arch/arm/boot/dts/mt6580.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
index a974830..a7071b38 100644
--- a/arch/arm/boot/dts/mt6580.dtsi
+++ b/arch/arm/boot/dts/mt6580.dtsi
@@ -23,26 +23,31 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "mediatek,mt6580-smp";
 
 		cpu at 0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x0>;
+			clock-frequency = <1700000000>;
 		};
 		cpu at 1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x1>;
+			clock-frequency = <1700000000>;
 		};
 		cpu at 2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x2>;
+			clock-frequency = <1700000000>;
 		};
 		cpu at 3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <0x3>;
+			clock-frequency = <1700000000>;
 		};
 
 	};
@@ -72,6 +77,21 @@
 		};
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <13000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
1.8.1.1.dirty

[RESEND PATCH 0/6] This series adds SMP support for the MediaTek MT6580.

[Alexey Klimov]

On Thu, Jun 18, 2015 at 9:01 PM, Scott Shu <scott.shu@mediatek.com> wrote:
> This patchset adds support SMP on MediaTek MT6580 Cortex-A7 qual core SoC.

quad?

> This is based on v4.1-rc1 and following patch series:
> (1) Yingjoe Chen's "Add SMP bringup support for mt65xx socs" [1]
> (2) Mars Cheng's "Add mt6580 basic chip support" [2]
> (3) Sascha Hauer's "Mediatek SCPSYS power domain support" [3]
>
> The secondary cores are power off as default on MT6580, this change adds
> a new enable-method to turn on power to the cores during booting process.
>
> The System Power Manager (SPM) inside the SCPSYS is for the CPU MTCMOS
> power domain control. Please check [3] for more information about SCPSYS.
>
> [1] https://lkml.org/lkml/2015/5/16/33
> [2] https://lkml.org/lkml/2015/6/3/113
> [3] https://lkml.org/lkml/2015/6/9/172
>
>
> Scott Shu (6):
>   Document: bindings: DT: Add SMP enable method for MT6580 SoC platform
>   soc: Mediatek: Add SCPSYS CPU power domain driver
>   ARM: mediatek: add smp bringup code
>   ARM: Mediatek: enable GPT6 on boot up to make arch timer working for MT6580
>   ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file.
>   ARM: dts: mt6580: enable basic SMP bringup for MT6580

Most of your patches are missing Signed-off-by.


-- 
Best regards, Klimov Alexey

[RESEND PATCH 0/6] This series adds SMP support for the MediaTek MT6580.

[Matthias Brugger]

On Friday, June 19, 2015 02:01:15 AM Scott Shu wrote:
> This patchset adds support SMP on MediaTek MT6580 Cortex-A7 qual core SoC.
> 
> This is based on v4.1-rc1 and following patch series:
> (1) Yingjoe Chen's "Add SMP bringup support for mt65xx socs" [1]
> (2) Mars Cheng's "Add mt6580 basic chip support" [2]
> (3) Sascha Hauer's "Mediatek SCPSYS power domain support" [3]
> 
> The secondary cores are power off as default on MT6580, this change adds
> a new enable-method to turn on power to the cores during booting process.
> 
> The System Power Manager (SPM) inside the SCPSYS is for the CPU MTCMOS
> power domain control. Please check [3] for more information about SCPSYS.
> 
> [1] https://lkml.org/lkml/2015/5/16/33
> [2] https://lkml.org/lkml/2015/6/3/113
> [3] https://lkml.org/lkml/2015/6/9/172
> 
> 
> Scott Shu (6):
>   Document: bindings: DT: Add SMP enable method for MT6580 SoC platform
>   soc: Mediatek: Add SCPSYS CPU power domain driver
>   ARM: mediatek: add smp bringup code
>   ARM: Mediatek: enable GPT6 on boot up to make arch timer working for
> MT6580 ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file.
>   ARM: dts: mt6580: enable basic SMP bringup for MT6580
> 
>  Documentation/devicetree/bindings/arm/cpus.txt |   1 +
>  arch/arm/boot/dts/mt6580.dtsi                  |  25 +++
>  arch/arm/mach-mediatek/Makefile                |   2 +-
>  arch/arm/mach-mediatek/generic.h               |  24 +++
>  arch/arm/mach-mediatek/hotplug.c               | 229
> +++++++++++++++++++++++++ arch/arm/mach-mediatek/mediatek.c              | 
>  4 +-
>  arch/arm/mach-mediatek/platsmp.c               | 113 +++++++++++-
>  7 files changed, 395 insertions(+), 3 deletions(-)
>  create mode 100644 arch/arm/mach-mediatek/generic.h
>  create mode 100644 arch/arm/mach-mediatek/hotplug.c


The whole series is missing a Signed-off-by tag, please add them to the next 
version. The Signed-off-by is mandatory for any patch to get accepted.

[RESEND PATCH 0/6] This series adds SMP support for the MediaTek MT6580.

[Scott Shu]

On Fri, 2015-07-24 at 14:59 +0200, Matthias Brugger wrote:
> On Friday, June 19, 2015 02:01:15 AM Scott Shu wrote:
> > This patchset adds support SMP on MediaTek MT6580 Cortex-A7 qual core SoC.
> > 
> > This is based on v4.1-rc1 and following patch series:
> > (1) Yingjoe Chen's "Add SMP bringup support for mt65xx socs" [1]
> > (2) Mars Cheng's "Add mt6580 basic chip support" [2]
> > (3) Sascha Hauer's "Mediatek SCPSYS power domain support" [3]
> > 
> > The secondary cores are power off as default on MT6580, this change adds
> > a new enable-method to turn on power to the cores during booting process.
> > 
> > The System Power Manager (SPM) inside the SCPSYS is for the CPU MTCMOS
> > power domain control. Please check [3] for more information about SCPSYS.
> > 
> > [1] https://lkml.org/lkml/2015/5/16/33
> > [2] https://lkml.org/lkml/2015/6/3/113
> > [3] https://lkml.org/lkml/2015/6/9/172
> > 
> > 
> > Scott Shu (6):
> >   Document: bindings: DT: Add SMP enable method for MT6580 SoC platform
> >   soc: Mediatek: Add SCPSYS CPU power domain driver
> >   ARM: mediatek: add smp bringup code
> >   ARM: Mediatek: enable GPT6 on boot up to make arch timer working for
> > MT6580 ARM: dts: mt6580: Add device nodes to the MT6580 dtsi file.
> >   ARM: dts: mt6580: enable basic SMP bringup for MT6580
> > 
> >  Documentation/devicetree/bindings/arm/cpus.txt |   1 +
> >  arch/arm/boot/dts/mt6580.dtsi                  |  25 +++
> >  arch/arm/mach-mediatek/Makefile                |   2 +-
> >  arch/arm/mach-mediatek/generic.h               |  24 +++
> >  arch/arm/mach-mediatek/hotplug.c               | 229
> > +++++++++++++++++++++++++ arch/arm/mach-mediatek/mediatek.c              | 
> >  4 +-
> >  arch/arm/mach-mediatek/platsmp.c               | 113 +++++++++++-
> >  7 files changed, 395 insertions(+), 3 deletions(-)
> >  create mode 100644 arch/arm/mach-mediatek/generic.h
> >  create mode 100644 arch/arm/mach-mediatek/hotplug.c
> 
> 
> The whole series is missing a Signed-off-by tag, please add them to the next 
> version. The Signed-off-by is mandatory for any patch to get accepted.

Hi Matthias,
   Thanks for reminding me. The new version is in
http://lists.infradead.org/pipermail/linux-mediatek/2015-July/001498.html

Thanks,
Scott Shu