[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Krzysztof Kozlowski]

The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
   ERROR: could not get clock /adc at 126C0000:adc(0)
   exynos-adc 126c0000.adc: failed getting clock, err = -2
   exynos-adc: probe of 126c0000.adc failed with error -2

Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.

The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: <stable@vger.kernel.org>
Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Link: https://lkml.org/lkml/2015/6/11/85

---

Changes since v1:
1. After discussion on LKML this solution was chosen because it smaller,
   simpler, self-contained (one patch to fix issue) and maintains backward
   compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
   valuable comments.
2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC"
   will be used on all Exynos4 boards.
3. Added CC-stable.
---
 drivers/clk/samsung/clk-exynos4.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 714d6ba782c8..f7890bf652e6 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -85,6 +85,7 @@
 #define DIV_PERIL4		0xc560
 #define DIV_PERIL5		0xc564
 #define E4X12_DIV_CAM1		0xc568
+#define E4X12_GATE_BUS_FSYS1	0xc744
 #define GATE_SCLK_CAM		0xc820
 #define GATE_IP_CAM		0xc920
 #define GATE_IP_TV		0xc924
@@ -1095,6 +1096,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
 		0),
 	GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
 		0),
+	GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
 	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
 	GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
 	GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
-- 
1.9.1

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Javier Martinez Canillas]

Hello Krzysztof,

On Fri, Jun 12, 2015 at 3:53 AM, Krzysztof Kozlowski
<k.kozlowski@samsung.com> wrote:
> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
> However TSADC is present only on Exynos4210 so on Trats2 board (with
> Exynos4412 SoC) the exynos-adc driver could not be probed:
>    ERROR: could not get clock /adc at 126C0000:adc(0)
>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>    exynos-adc: probe of 126c0000.adc failed with error -2
>
> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
> Converter is located in different register and it is named in datasheet
> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
> is the same as purpose of TSADC from Exynos4210.
>
> The patch adds gate clock for Exynos4x12 using the proper register so
> backward compatibility is preserved. This fixes the probe of exynos-adc
> driver on Exynos4x12 boards and allows accessing sensors connected to it
> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
>
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: <stable@vger.kernel.org>
> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
> Link: https://lkml.org/lkml/2015/6/11/85
>
> ---
>
> Changes since v1:
> 1. After discussion on LKML this solution was chosen because it smaller,
>    simpler, self-contained (one patch to fix issue) and maintains backward
>    compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
>    valuable comments.
> 2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC"
>    will be used on all Exynos4 boards.
> 3. Added CC-stable.
> ---
>  drivers/clk/samsung/clk-exynos4.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Patch looks good to me.

Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

Best regards,
Javier

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Krzysztof Kozlowski]

2015-06-12 14:46 GMT+09:00 Javier Martinez Canillas <javier@dowhile0.org>:
> Hello Krzysztof,
>
> On Fri, Jun 12, 2015 at 3:53 AM, Krzysztof Kozlowski
> <k.kozlowski@samsung.com> wrote:
>> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
>> However TSADC is present only on Exynos4210 so on Trats2 board (with
>> Exynos4412 SoC) the exynos-adc driver could not be probed:
>>    ERROR: could not get clock /adc at 126C0000:adc(0)
>>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>>    exynos-adc: probe of 126c0000.adc failed with error -2
>>
>> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
>> Converter is located in different register and it is named in datasheet
>> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
>> is the same as purpose of TSADC from Exynos4210.
>>
>> The patch adds gate clock for Exynos4x12 using the proper register so
>> backward compatibility is preserved. This fixes the probe of exynos-adc
>> driver on Exynos4x12 boards and allows accessing sensors connected to it
>> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
>>
>> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>> Cc: <stable@vger.kernel.org>
>> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
>> Link: https://lkml.org/lkml/2015/6/11/85
>>
>> ---
>>
>> Changes since v1:
>> 1. After discussion on LKML this solution was chosen because it smaller,
>>    simpler, self-contained (one patch to fix issue) and maintains backward
>>    compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
>>    valuable comments.
>> 2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC"
>>    will be used on all Exynos4 boards.
>> 3. Added CC-stable.
>> ---
>>  drivers/clk/samsung/clk-exynos4.c | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>
> Patch looks good to me.
>
> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

Hi Tomasz and Sylwester,

Any comments on this version of patch?
Tomasz, you gave me comments on previous version. Are their satisfied?

Best regards,
Krzysztof

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Tomasz Figa]

2015-07-06 13:03 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>:
> 2015-06-12 14:46 GMT+09:00 Javier Martinez Canillas <javier@dowhile0.org>:
>> Hello Krzysztof,
>>
>> On Fri, Jun 12, 2015 at 3:53 AM, Krzysztof Kozlowski
>> <k.kozlowski@samsung.com> wrote:
>>> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
>>> However TSADC is present only on Exynos4210 so on Trats2 board (with
>>> Exynos4412 SoC) the exynos-adc driver could not be probed:
>>>    ERROR: could not get clock /adc at 126C0000:adc(0)
>>>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>>>    exynos-adc: probe of 126c0000.adc failed with error -2
>>>
>>> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
>>> Converter is located in different register and it is named in datasheet
>>> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
>>> is the same as purpose of TSADC from Exynos4210.
>>>
>>> The patch adds gate clock for Exynos4x12 using the proper register so
>>> backward compatibility is preserved. This fixes the probe of exynos-adc
>>> driver on Exynos4x12 boards and allows accessing sensors connected to it
>>> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
>>>
>>> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>> Cc: <stable@vger.kernel.org>
>>> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
>>> Link: https://lkml.org/lkml/2015/6/11/85
>>>
>>> ---
>>>
>>> Changes since v1:
>>> 1. After discussion on LKML this solution was chosen because it smaller,
>>>    simpler, self-contained (one patch to fix issue) and maintains backward
>>>    compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
>>>    valuable comments.
>>> 2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC"
>>>    will be used on all Exynos4 boards.
>>> 3. Added CC-stable.
>>> ---
>>>  drivers/clk/samsung/clk-exynos4.c | 2 ++
>>>  1 file changed, 2 insertions(+)
>>>
>>
>> Patch looks good to me.
>>
>> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>
> Hi Tomasz and Sylwester,
>
> Any comments on this version of patch?
> Tomasz, you gave me comments on previous version. Are their satisfied?

Acked-by: Tomasz Figa <tomasz.figa@gmail.com>

Thanks for pinging.

Best regards,
Tomasz

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Krzysztof Kozlowski]

2015-07-06 14:12 GMT+09:00 Tomasz Figa <tomasz.figa@gmail.com>:
> 2015-07-06 13:03 GMT+09:00 Krzysztof Kozlowski <k.kozlowski@samsung.com>:
>> 2015-06-12 14:46 GMT+09:00 Javier Martinez Canillas <javier@dowhile0.org>:
>>> Hello Krzysztof,
>>>
>>> On Fri, Jun 12, 2015 at 3:53 AM, Krzysztof Kozlowski
>>> <k.kozlowski@samsung.com> wrote:
>>>> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
>>>> However TSADC is present only on Exynos4210 so on Trats2 board (with
>>>> Exynos4412 SoC) the exynos-adc driver could not be probed:
>>>>    ERROR: could not get clock /adc at 126C0000:adc(0)
>>>>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>>>>    exynos-adc: probe of 126c0000.adc failed with error -2
>>>>
>>>> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
>>>> Converter is located in different register and it is named in datasheet
>>>> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
>>>> is the same as purpose of TSADC from Exynos4210.
>>>>
>>>> The patch adds gate clock for Exynos4x12 using the proper register so
>>>> backward compatibility is preserved. This fixes the probe of exynos-adc
>>>> driver on Exynos4x12 boards and allows accessing sensors connected to it
>>>> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
>>>>
>>>> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>>> Cc: <stable@vger.kernel.org>
>>>> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
>>>> Link: https://lkml.org/lkml/2015/6/11/85
>>>>
>>>> ---
>>>>
>>>> Changes since v1:
>>>> 1. After discussion on LKML this solution was chosen because it smaller,
>>>>    simpler, self-contained (one patch to fix issue) and maintains backward
>>>>    compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
>>>>    valuable comments.
>>>> 2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC"
>>>>    will be used on all Exynos4 boards.
>>>> 3. Added CC-stable.
>>>> ---
>>>>  drivers/clk/samsung/clk-exynos4.c | 2 ++
>>>>  1 file changed, 2 insertions(+)
>>>>
>>>
>>> Patch looks good to me.
>>>
>>> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>>
>> Hi Tomasz and Sylwester,
>>
>> Any comments on this version of patch?
>> Tomasz, you gave me comments on previous version. Are their satisfied?
>
> Acked-by: Tomasz Figa <tomasz.figa@gmail.com>

Thanks for ack.

Sylwester, are you gonna to pick it up or this should go through other tree?

Best regards,
Krzysztof

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Sylwester Nawrocki]

On 09/07/15 02:23, Krzysztof Kozlowski wrote:
>>>>>  drivers/clk/samsung/clk-exynos4.c | 2 ++
>>>>> >>>>  1 file changed, 2 insertions(+)
>>>>> >>>>
>>>> >>>
>>>> >>> Patch looks good to me.
>>>> >>>
>>>> >>> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>>> >>
>>> >> Hi Tomasz and Sylwester,
>>> >>
>>> >> Any comments on this version of patch?
>>> >> Tomasz, you gave me comments on previous version. Are their satisfied?
>> >
>> > Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
> Thanks for ack.
> 
> Sylwester, are you gonna to pick it up or this should go through other tree?

I've taken care of this citizen, thanks for the reminder and reviews.

-- 
Regards,
Sylwester

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Stephen Boyd]

On 06/12, Krzysztof Kozlowski wrote:
> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
> However TSADC is present only on Exynos4210 so on Trats2 board (with
> Exynos4412 SoC) the exynos-adc driver could not be probed:
>    ERROR: could not get clock /adc at 126C0000:adc(0)
>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>    exynos-adc: probe of 126c0000.adc failed with error -2
> 
> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
> Converter is located in different register and it is named in datasheet
> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
> is the same as purpose of TSADC from Exynos4210.
> 
> The patch adds gate clock for Exynos4x12 using the proper register so
> backward compatibility is preserved. This fixes the probe of exynos-adc
> driver on Exynos4x12 boards and allows accessing sensors connected to it
> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
> 
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: <stable@vger.kernel.org>
> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
> Link: https://lkml.org/lkml/2015/6/11/85
> 

Did you want clk maintainers to apply this? The To: list is not
helping so I'm not sure what's going on and it seems to have
slipped through the cracks.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Krzysztof Kozlowski]

On 22.07.2015 07:42, Stephen Boyd wrote:
> On 06/12, Krzysztof Kozlowski wrote:
>> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
>> However TSADC is present only on Exynos4210 so on Trats2 board (with
>> Exynos4412 SoC) the exynos-adc driver could not be probed:
>>    ERROR: could not get clock /adc at 126C0000:adc(0)
>>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>>    exynos-adc: probe of 126c0000.adc failed with error -2
>>
>> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
>> Converter is located in different register and it is named in datasheet
>> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
>> is the same as purpose of TSADC from Exynos4210.
>>
>> The patch adds gate clock for Exynos4x12 using the proper register so
>> backward compatibility is preserved. This fixes the probe of exynos-adc
>> driver on Exynos4x12 boards and allows accessing sensors connected to it
>> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
>>
>> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>> Cc: <stable@vger.kernel.org>
>> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
>> Link: https://lkml.org/lkml/2015/6/11/85
>>
> 
> Did you want clk maintainers to apply this? The To: list is not
> helping so I'm not sure what's going on and it seems to have
> slipped through the cracks.

Thank you for being proactive! I appreciate this.
Some time ago Sylwester replied that he took care about this patch so I
think this will go through Samsung clock tree.


Sylwester, are you planning to send this as fix for 4.2-rc?

Best regards,
Krzysztof

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Sylwester Nawrocki]

On 07/22/2015 08:41 AM, Krzysztof Kozlowski wrote:
> On 22.07.2015 07:42, Stephen Boyd wrote:
>> >On 06/12, Krzysztof Kozlowski wrote:
[...]
>>> >>Signed-off-by: Krzysztof Kozlowski<k.kozlowski@samsung.com>
>>> >>Cc:<stable@vger.kernel.org>
>>> >>Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
>>> >>Link:https://lkml.org/lkml/2015/6/11/85
>> >
>> >Did you want clk maintainers to apply this? The To: list is not
>> >helping so I'm not sure what's going on and it seems to have
>> >slipped through the cracks.
 >
> Thank you for being proactive! I appreciate this.
> Some time ago Sylwester replied that he took care about this patch so I
> think this will go through Samsung clock tree.
>
> Sylwester, are you planning to send this as fix for 4.2-rc?

I think it qualifies for 4.3, it's not a new regression and will be
backported to -stable anyway.
I would prefer clk maintainers have applied this, otherwise I would
need to make a (questionable) pull request with only one patch, since
all patches except this one after the last merge window were part
of bigger series touching multiple subsystems and applied through
the samsung soc tree.

Thanks,
Sylwester

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Stephen Boyd]

On 07/26, Sylwester Nawrocki wrote:
> On 07/22/2015 08:41 AM, Krzysztof Kozlowski wrote:
> >On 22.07.2015 07:42, Stephen Boyd wrote:
> >>>On 06/12, Krzysztof Kozlowski wrote:
> [...]
> >>>>>Signed-off-by: Krzysztof Kozlowski<k.kozlowski@samsung.com>
> >>>>>Cc:<stable@vger.kernel.org>
> >>>>>Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
> >>>>>Link:https://lkml.org/lkml/2015/6/11/85
> >>>
> >>>Did you want clk maintainers to apply this? The To: list is not
> >>>helping so I'm not sure what's going on and it seems to have
> >>>slipped through the cracks.
> >
> >Thank you for being proactive! I appreciate this.
> >Some time ago Sylwester replied that he took care about this patch so I
> >think this will go through Samsung clock tree.
> >
> >Sylwester, are you planning to send this as fix for 4.2-rc?
> 
> I think it qualifies for 4.3, it's not a new regression and will be
> backported to -stable anyway.
> I would prefer clk maintainers have applied this, otherwise I would
> need to make a (questionable) pull request with only one patch, since
> all patches except this one after the last merge window were part
> of bigger series touching multiple subsystems and applied through
> the samsung soc tree.
> 

Ok. Applied to clk-next.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2] clk: exynos4: Fix wrong clock for Exynos4x12 ADC

[Sylwester Nawrocki]

On 12/06/15 03:53, Krzysztof Kozlowski wrote:
> The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
> However TSADC is present only on Exynos4210 so on Trats2 board (with
> Exynos4412 SoC) the exynos-adc driver could not be probed:
>    ERROR: could not get clock /adc at 126C0000:adc(0)
>    exynos-adc 126c0000.adc: failed getting clock, err = -2
>    exynos-adc: probe of 126c0000.adc failed with error -2
> 
> Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
> Converter is located in different register and it is named in datasheet
> as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
> is the same as purpose of TSADC from Exynos4210.
> 
> The patch adds gate clock for Exynos4x12 using the proper register so
> backward compatibility is preserved. This fixes the probe of exynos-adc
> driver on Exynos4x12 boards and allows accessing sensors connected to it
> on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
> 
> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> Cc: <stable@vger.kernel.org>
> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
> Link: https://lkml.org/lkml/2015/6/11/85

Mike, could you apply this patch directly? I can't seem to find any
more independent patches for clk/samsung pull request.
Alternatively here is a branch you could cherry-pick it from with
all Acked/Reviewed tags:

git://linuxtv.org/snawrocki/samsung.git for-v4.2/clk/fixes-1

--
Regards,
Sylwester

> Changes since v1:
> 1. After discussion on LKML this solution was chosen because it smaller,
>    simpler, self-contained (one patch to fix issue) and maintains backward
>    compatibility. Thanks to Javier Martinez Canillas and Tomasz Figa for
>    valuable comments.
> 2. Dropped patch 2/2 because now it is not needed. The clock id "TSADC"
>    will be used on all Exynos4 boards.
> 3. Added CC-stable.
> ---
>  drivers/clk/samsung/clk-exynos4.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 714d6ba782c8..f7890bf652e6 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -85,6 +85,7 @@
>  #define DIV_PERIL4		0xc560
>  #define DIV_PERIL5		0xc564
>  #define E4X12_DIV_CAM1		0xc568
> +#define E4X12_GATE_BUS_FSYS1	0xc744
>  #define GATE_SCLK_CAM		0xc820
>  #define GATE_IP_CAM		0xc920
>  #define GATE_IP_TV		0xc924
> @@ -1095,6 +1096,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
>  		0),
>  	GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
>  		0),
> +	GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
>  	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
>  	GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
>  	GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
> 


-- 
Sylwester Nawrocki
Samsung R&D Institute Poland