From mboxrd@z Thu Jan  1 00:00:00 1970
From: shawnguo@kernel.org (Shawn Guo)
Date: Wed, 5 Aug 2015 20:56:50 +0800
Subject: [PATCH v2 2/4] ARM: imx6ul: add fec MAC refrence clock and phy
 fixup init
In-Reply-To: <1438068642-6876-3-git-send-email-b38611@freescale.com>
References: <1438068642-6876-1-git-send-email-b38611@freescale.com>
 <1438068642-6876-3-git-send-email-b38611@freescale.com>
Message-ID: <20150805125650.GL12927@tiger>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On Tue, Jul 28, 2015 at 03:30:40PM +0800, Fugang Duan wrote:
> Add FEC MAC refrence clock init.
> Add phy fixup init for i.MX6ul 14x14 evk board that installs KSZ8081 phy.
> For the phy, there needs extra phy fixup for MII and RMII mode.
> 
> Signed-off-by: Fugang Duan <b38611@freescale.com>
> ---
>  arch/arm/mach-imx/mach-imx6ul.c | 43 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 43 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
> index f206506..0d81152 100644
> --- a/arch/arm/mach-imx/mach-imx6ul.c
> +++ b/arch/arm/mach-imx/mach-imx6ul.c
> @@ -7,11 +7,53 @@
>   */
>  #include <linux/irqchip.h>
>  #include <linux/of_platform.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
> +#include <linux/micrel_phy.h>

'm' should go above 'o', right?  I fixed the ordering and applied the
whole series.

Shawn

> +#include <linux/phy.h>
> +#include <linux/regmap.h>
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
>  
>  #include "common.h"
>  
> +static void __init imx6ul_enet_clk_init(void)
> +{
> +	struct regmap *gpr;
> +
> +	gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
> +	if (!IS_ERR(gpr))
> +		regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
> +				   IMX6UL_GPR1_ENET_CLK_OUTPUT);
> +	else
> +		pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
> +
> +}
> +
> +static int ksz8081_phy_fixup(struct phy_device *dev)
> +{
> +	if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
> +		phy_write(dev, 0x1f, 0x8110);
> +		phy_write(dev, 0x16, 0x201);
> +	} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
> +		phy_write(dev, 0x1f, 0x8190);
> +		phy_write(dev, 0x16, 0x202);
> +	}
> +
> +	return 0;
> +}
> +
> +static void __init imx6ul_enet_phy_init(void)
> +{
> +	phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff, ksz8081_phy_fixup);
> +}
> +
> +static inline void imx6ul_enet_init(void)
> +{
> +	imx6ul_enet_clk_init();
> +	imx6ul_enet_phy_init();
> +}
> +
>  static void __init imx6ul_init_machine(void)
>  {
>  	struct device *parent;
> @@ -21,6 +63,7 @@ static void __init imx6ul_init_machine(void)
>  		pr_warn("failed to initialize soc device\n");
>  
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +	imx6ul_enet_init();
>  	imx_anatop_init();
>  }
>  
> -- 
> 1.9.1
> 
> 
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