IRQ setup on multicore systems (routing, balancing, etc)

[linux@arm.linux.org.uk (Russell King - ARM Linux)]

On Thu, Aug 06, 2015 at 06:14:46PM +0200, Mason wrote:
> It doesn't help that the port I'm working on doesn't follow
> "established guidelines". In this case, interrupt routing is
> hard-coded in the platform code:
> 
> static inline void tangox_enable(struct irq_data *data)
> {
> 	int bit = data->irq - IRQ_CONTROLLER_IRQ_BASE;
> #ifdef ENABLE_INTERRUPT_ON_CPU1
> 	if(route_interrupt_to_cpu1(bit))
> 		tangox_fiq_enable(bit);
> 	else
> #endif
> 		tangox_irq_enable(bit);
> }
> 
> (tangox_enable is called in the .irq_startup struct irq_chip callback.)
> 
> Throw weird naming in the mix (I thought FIQ was reserved for
> the secure world, and my Linux runs in non-secure) and my
> confusion level is up to 11.

Looking at the above code, I must say that it looks like the code is on
some kind of drugs.  The code implies that FIQs are routed to CPU1, which
is obviously a totally insane.  I think I'd be as confused as you over
that.

Are you basing your idea that certain interrupts need to be routed to a
certain CPU on this code, or on practical experience?  It may be better
to experiment with the hardware to find out what's possible rather than
rely on hacky undocumented code such as the above.

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.