From mboxrd@z Thu Jan  1 00:00:00 1970
From: will.deacon@arm.com (Will Deacon)
Date: Tue, 18 Aug 2015 13:44:48 +0100
Subject: [PATCH V3] iommu/arm-smmu-v2: ThunderX mis-extends 64bit registers
In-Reply-To: <1439853235-12162-1-git-send-email-tchalamarla@caviumnetworks.com>
References: <1439853235-12162-1-git-send-email-tchalamarla@caviumnetworks.com>
Message-ID: <20150818124448.GA13507@arm.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi Tirumalesh,

On Tue, Aug 18, 2015 at 12:13:55AM +0100, tchalamarla at caviumnetworks.com wrote:
> From: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
> 
> The SMMU architecture defines two different behaviors when 64-bit
> registers are written with 32-bit writes.  The first behavior causes
> zero extension into the upper 32-bits.  The second behavior splits a
> 64-bit register into "normal" 32-bit register pairs.
> 
> On some buggy implementations, registers incorrectly zero extended
> when they should instead behave as normal 32-bit register pairs.
> 
> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
> 
> Changes from V2:
> 	- removed unused definitions
> 
> Changes from V1:
> 	- Introduced smmu_writeq
> ---
>  drivers/iommu/arm-smmu.c | 57 +++++++++++++++++++++++++-----------------------
>  1 file changed, 30 insertions(+), 27 deletions(-)

I'm happy with this, but it doesn't apply against mainline or my tree.
Please can you rebase it onto something more recent, preferably my
iommu/devel branch?

Thanks,

Will