From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS
Date: Tue, 6 Oct 2015 11:06:17 -0700 [thread overview]
Message-ID: <20151006180617.GE12338@codeaurora.org> (raw)
In-Reply-To: <1444032393-13433-3-git-send-email-gabriel.fernandez@linaro.org>
On 10/05, Gabriel Fernandez wrote:
> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
> static struct clk * __init clkgen_pll_register(const char *parent_name,
> struct clkgen_pll_data *pll_data,
> void __iomem *reg,
> - const char *clk_name)
> + const char *clk_name, spinlock_t *lock)
Is there a reason we pass lock here but never use it in this
function?
> {
> struct clkgen_pll *pll;
> struct clk *clk;
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-10-06 18:06 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-05 8:06 [PATCH v3 0/4] ST PLL improvement Gabriel Fernandez
2015-10-05 8:06 ` [PATCH v3 1/4] drivers: clk: st: Support for enable/disable in Clockgen PLLs Gabriel Fernandez
2015-10-05 8:06 ` [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation for DVFS Gabriel Fernandez
2015-10-06 18:06 ` Stephen Boyd [this message]
2015-10-07 7:47 ` Gabriel Fernandez
2015-10-05 8:06 ` [PATCH v3 3/4] drivers: clk: st: Correct the pll-type for A9 for stih418 Gabriel Fernandez
2015-10-05 8:06 ` [PATCH v3 4/4] ARM: STi: DT: Add support for stih418 A9 pll Gabriel Fernandez
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