From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] irqchip/gic-v3: Make gic_enable_sre an inline function
Date: Thu, 8 Oct 2015 16:54:04 +0100 [thread overview]
Message-ID: <20151008155404.GN17192@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <1443803874-9566-3-git-send-email-marc.zyngier@arm.com>
On Fri, Oct 02, 2015 at 05:37:51PM +0100, Marc Zyngier wrote:
> +static inline bool gic_enable_sre(void)
> +{
> + u64 val;
> +
> + asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
> + if (val & ICC_SRE_EL1_SRE)
> + return true;
> +
> + val |= ICC_SRE_EL1_SRE;
> + asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));
> + isb();
> + asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
> +
> + return !!(val & ICC_SRE_EL1_SRE);
> +}
I don't think !! is needed ;). Apparently, from ISO C99: "When any
scalar value is converted to _Bool, the result is 0 if the value
compares equal to 0; otherwise, the result is 1."
--
Catalin
next prev parent reply other threads:[~2015-10-08 15:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-02 16:37 [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode Marc Zyngier
2015-10-02 16:37 ` [PATCH 1/5] arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3 sysregs Marc Zyngier
2015-10-02 16:37 ` [PATCH 2/5] irqchip/gic-v3: Make gic_enable_sre an inline function Marc Zyngier
2015-10-08 15:54 ` Catalin Marinas [this message]
2015-10-08 16:02 ` Marc Zyngier
2015-10-02 16:37 ` [PATCH 3/5] arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF Marc Zyngier
2015-10-02 16:37 ` [PATCH 4/5] irqchip/gic: Warn if GICv3 system registers are enabled Marc Zyngier
2015-10-02 16:37 ` [PATCH 5/5] arm64: Update booting requirements for GICv3 in GICv2 mode Marc Zyngier
2015-10-08 15:56 ` [PATCH 0/5] arm64: Allow booting with " Catalin Marinas
2015-10-08 16:09 ` Marc Zyngier
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