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From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 09/24] arm64: Keep track of CPU feature registers
Date: Thu, 15 Oct 2015 11:36:12 +0100	[thread overview]
Message-ID: <20151015103611.GK4239@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <1444756952-31145-10-git-send-email-suzuki.poulose@arm.com>

Hi Suzuki,

Some minor comments below.

On Tue, Oct 13, 2015 at 06:22:17PM +0100, Suzuki K. Poulose wrote:
> This patch adds an infrastructure to keep track of the CPU feature
> registers on the system. For each register, the infrastructure keeps
> track of the system wide safe value of the feature bits. Also, tracks
> the which fields of a register should be matched strictly across all
> the CPUs on the system for the SANITY check infrastructure.
> 
> The feature bits are classified as one of SCALAR_MIN, SCALAR_MAX and DISCRETE
> depending on the implication of the possible values. This information
> is used to decide the safe value for a feature.
> 
> LOWER_SAFE  - The smaller value is safer
> HIGHER_SAFE - The bigger value is safer
> EXACT       - We can't decide between the two, so a predefined safe_value is used.

The "SCALAR..." etc. in the comment needs updating.

> +#define FTR_STRICT	true
> +#define FTR_NONSTRICT	false

Please add a comment on what STRICT/NONSTRICT mean.

> +static inline u64 ftr_mask(struct arm64_ftr_bits *ftrp)
> +{
> +	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
> +}
> +
> +static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
> +{
> +	return cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width);
> +}

Slightly inconsistent naming: since you are prefixing everything with
arm64_, do the same for ftr_mask.

> +static struct arm64_ftr_reg arm64_ftr_regs[] = {
> +
> +	/* This array should be always kept in the ascending order of id  */

Do we have a sanity check somewhere? You could also call sort() on this
array and we wouldn't have to worry.

> +/*
> + * get_arm64_sys_reg - Lookup a feature register entry using its
> + * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
> + * ascending order, we use binary search to find a matching entry.
> + *
> + * returns - Upon success,  matching ftr_reg entry for id.
> + *         - NULL on failure. It is upto the caller to decide
> + *	     the impact of a failure.
> + */
> +static struct arm64_ftr_reg* get_arm64_sys_reg(u32 sys_id)

Nitpick: the * near the function name.

Also rename it to get_arm64_ftr_reg() to match the actual return type.

-- 
Catalin

  reply	other threads:[~2015-10-15 10:36 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-13 17:22 [PATCH v3 00/24] arm64: Consolidate CPU feature handling Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 01/24] arm64: Make the CPU information more clear Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 02/24] arm64: Delay ELF HWCAP initialisation until all CPUs are up Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 03/24] arm64: Delay cpuinfo_store_boot_cpu Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 04/24] arm64: Move cpu feature detection code Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 05/24] arm64: Move mixed endian support detection Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 06/24] arm64: Move /proc/cpuinfo handling code Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 07/24] arm64: Define helper for sys_reg id manipulation Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 08/24] arm64: Handle width of a cpuid feature Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 09/24] arm64: Keep track of CPU feature registers Suzuki K. Poulose
2015-10-15 10:36   ` Catalin Marinas [this message]
2015-10-15 10:45     ` Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 10/24] arm64: Consolidate CPU Sanity check to CPU Feature infrastructure Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 11/24] arm64: Read system wide CPUID value Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 12/24] arm64: Cleanup mixed endian support detection Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 13/24] arm64: Populate cpuinfo after notify_cpu_starting Suzuki K. Poulose
2015-10-15 10:54   ` Catalin Marinas
2015-10-15 13:23     ` Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 14/24] arm64: Delay cpu feature capability checks Suzuki K. Poulose
2015-10-17 22:56   ` kbuild test robot
2015-10-19  9:41     ` Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 15/24] arm64: Make use of system wide " Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 16/24] arm64: Cleanup HWCAP handling Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 17/24] arm64: Move FP/ASIMD hwcap handling to common code Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 18/24] arm64/debug: Make use of the system wide safe value Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 19/24] arm64/kvm: Make use of the system wide safe values Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 20/24] arm64: Documentation - Expose CPU feature registers Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 21/24] arm64: Add helper to decode register from instruction Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 22/24] arm64: cpufeature: Track the user visible fields Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 23/24] arm64: Expose feature registers by emulating MRS Suzuki K. Poulose
2015-10-13 17:22 ` [PATCH v3 24/24] arm64: cpuinfo: Expose MIDR_EL1 and REVIDR_EL1 to sysfs Suzuki K. Poulose
2015-10-14  9:03   ` Suzuki K. Poulose
2015-10-16 15:13 ` [PATCH v3 00/24] arm64: Consolidate CPU feature handling Dave Martin
2015-10-16 15:32   ` Suzuki K. Poulose
2015-10-16 15:42     ` Dave Martin
2015-10-25  8:06 ` Siddhesh Poyarekar
2015-10-27 18:09   ` Suzuki K. Poulose
2015-10-28  8:53     ` Siddhesh Poyarekar

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