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From: robh@kernel.org (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/10] dt-bindings: nxp: add description of wakeup controller on LPC32xx
Date: Fri, 20 Nov 2015 10:55:07 -0600	[thread overview]
Message-ID: <20151120165507.GA12088@rob-hp-laptop> (raw)
In-Reply-To: <1447982925-30138-3-git-send-email-vz@mleia.com>

On Fri, Nov 20, 2015 at 03:28:37AM +0200, Vladimir Zapolskiy wrote:
> NXP LPC32xx has three wakeup controllers of two types, this
> descriptions defines DT bindings of wakeup controllers connected to
> MIC, SIC1 and SIC2 interrupt controllers.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
>  .../bindings/arm/nxp/nxp,lpc3220-wakeup.txt        | 41 ++++++++++++++++++++++
>  1 file changed, 41 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt b/Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt
> new file mode 100644
> index 0000000..803728f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/nxp/nxp,lpc3220-wakeup.txt
> @@ -0,0 +1,41 @@
> +NXP LPC32xx Wakeup Controller
> +
> +Required properties:
> +- compatible: should be "nxp,lpc3220-wakeup"
> +- reg:  should contain wakeup controller registers location and length
> +- #wakeup-cells: must be 2, the first cell describes wakeup source on
> +  the controller, the second cell is a hardware interrupt number on IC.

This probably needs to be done differently. For one, we already have a 
common property "wakeup-source" with different meaning.

Marc, Is there an example of using stacked irqdomain and mapping of irq 
numbers to wakeup numbers?

Rob

> +
> +Examples:
> +
> +	/* System Control Block */
> +	scb {
> +		compatible = "simple-bus";
> +		ranges = <0x0 0x040004000 0x00001000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		wakeup_int: wakeup-controller at 20 {
> +			compatible = "nxp,lpc3220-wakeup";
> +			reg = <0x20 0x10>;
> +			#wakeup-cells = <2>;
> +		};
> +
> +		wakeup_pin: wakeup-controller at 30 {
> +			compatible = "nxp,lpc3220-wakeup";
> +			reg = <0x30 0x10>;
> +			#wakeup-cells = <2>;
> +		};
> +	};
> +
> +	/* Main Interrupt Controller */
> +	mic: interrupt-controller at 40008000 {
> +		compatible = "nxp,lpc3220-mic";
> +		reg = <0x40008000 0x4000>;
> +		interrupt-controller;
> +		interrupt-controller-name = "mic";
> +		#interrupt-cells = <2>;
> +
> +		wakeup-sources = <&wakeup_int 7 29>,
> +				 <&wakeup_int 25 27>;
> +	};
> -- 
> 2.1.4
> 

  reply	other threads:[~2015-11-20 16:55 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-20  1:28 [PATCH 00/10] irqchip: lpc32xx: add LPC32xx irqchip driver Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 01/10] dt-bindings: create arm/nxp folder and move LPC32xx SoC description to it Vladimir Zapolskiy
2015-11-20 16:43   ` Rob Herring
2015-11-20  1:28 ` [PATCH 02/10] dt-bindings: nxp: add description of wakeup controller on LPC32xx Vladimir Zapolskiy
2015-11-20 16:55   ` Rob Herring [this message]
2015-11-20  1:28 ` [PATCH 03/10] dt-bindings: interrupt-controllers: add description of SIC1 and SIC2 Vladimir Zapolskiy
2015-11-20 16:58   ` Rob Herring
2015-11-20 17:52     ` Vladimir Zapolskiy
2015-11-20 18:02       ` Marc Zyngier
2015-11-20 18:16         ` Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 04/10] arm: lpc32xx: add wakeup platform driver Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 05/10] arm: dts: lpc32xx: assign interrupt types Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 06/10] arm: dts: lpc32xx: add description of IC wakeup controllers Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 07/10] arm: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 08/10] irqchip: add LPC32xx interrupt controller driver Vladimir Zapolskiy
2015-11-20 10:56   ` Marc Zyngier
2015-11-20  1:28 ` [PATCH 09/10] irqchip: lpc32xx: add option to wakeup from an interrupt Vladimir Zapolskiy
2015-11-20  1:28 ` [PATCH 10/10] arm: dts: lpc32xx: enable SIC1 and SIC2 by default Vladimir Zapolskiy
     [not found] ` <loom.20160210T204046-649@post.gmane.org>
2016-04-04 17:37   ` [PATCH 00/10] irqchip: lpc32xx: add LPC32xx irqchip driver Sylvain Lemieux
2016-04-05  1:24     ` Vladimir Zapolskiy

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