From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: ti: omap5+: dpll: implement errata i810
Date: Mon, 30 Nov 2015 11:35:38 -0800 [thread overview]
Message-ID: <20151130193538.GJ11298@codeaurora.org> (raw)
In-Reply-To: <1448894605-30097-1-git-send-email-t-kristo@ti.com>
On 11/30, Tero Kristo wrote:
> Errata i810 states that DPLL controller can get stuck while transitioning
> to a power saving state, while its M/N ratio is being re-programmed.
>
> As a workaround, before re-programming the M/N ratio, SW has to ensure
> the DPLL cannot start an idle state transition. SW can disable DPLL
> idling by setting the DPLL AUTO_DPLL_MODE=0 or keeping a clock request
> active by setting a dependent clock domain in SW_WKUP.
>
> This errata impacts OMAP5 and DRA7 chips, so enable the errata for these.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-11-30 19:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-30 14:43 [PATCH] clk: ti: omap5+: dpll: implement errata i810 Tero Kristo
2015-11-30 19:35 ` Stephen Boyd [this message]
2015-12-03 16:48 ` Tony Lindgren
2015-12-11 8:43 ` Tero Kristo
2015-12-11 16:55 ` Tony Lindgren
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