From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] clk: sunxi: pll2: Fix clock running too fast
Date: Wed, 2 Dec 2015 23:31:23 -0800 [thread overview]
Message-ID: <20151203073123.GD14699@codeaurora.org> (raw)
In-Reply-To: <1448968492-28979-1-git-send-email-maxime.ripard@free-electrons.com>
On 12/01, Maxime Ripard wrote:
> Contrary to what the datasheet says, the pre divider doesn't seem to be
> incremented by one in the PLL2, but just uses the value from the register,
> with 0 being a bypass.
>
> This fixes the audio playing too fast.
>
> Since we now have the same pre-divider flags, and the only difference with
> the A10 is the post-divider offset, also remove the structure to just pass
> the offset as an argument.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
Applied to clk-fixes + I added the Fixes tag.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2015-12-03 7:31 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-01 11:14 [PATCH v2] clk: sunxi: pll2: Fix clock running too fast Maxime Ripard
2015-12-03 7:31 ` Stephen Boyd [this message]
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