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From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
Date: Wed, 9 Dec 2015 08:23:18 +0000	[thread overview]
Message-ID: <20151209082318.0de1d861@arm.com> (raw)
In-Reply-To: <5667DA61.8080106@huawei.com>

On Wed, 9 Dec 2015 15:38:09 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:

> 
> 
> On 2015/12/8 23:43, Marc Zyngier wrote:
> > On 08/12/15 12:47, Shannon Zhao wrote:
> >> From: Shannon Zhao <shannon.zhao@linaro.org>
> >> +/**
> >> + * kvm_pmu_get_counter_value - get PMU counter value
> >> + * @vcpu: The vcpu pointer
> >> + * @select_idx: The counter index
> >> + */
> >> +u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
> >> +{
> >> +	u64 counter, enabled, running;
> >> +	struct kvm_pmu *pmu = &vcpu->arch.pmu;
> >> +	struct kvm_pmc *pmc = &pmu->pmc[select_idx];
> >> +
> >> +	if (!vcpu_mode_is_32bit(vcpu))
> >> +		counter = vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + select_idx);
> >> +	else
> >> +		counter = vcpu_cp15(vcpu, c14_PMEVCNTR0 + select_idx);
> >> +
> >> +	if (pmc->perf_event)
> >> +		counter += perf_event_read_value(pmc->perf_event, &enabled,
> >> +						 &running);
> >> +
> >> +	return counter & pmc->bitmask;
> > 
> > This one confused me for a while. Is it the case that you return
> > whatever is in the vcpu view of the counter, plus anything that perf
> > itself has counted? If so, I'd appreciate a comment here...
> > 
> Yes, the real counter value is the current counter value plus the value
> perf event counts. I'll add a comment.
> 
> >> +}
> >> +
> >> +static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u32 select_idx)
> >> +{
> >> +	if (!vcpu_mode_is_32bit(vcpu))
> >> +		return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &
> >> +		       (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) >> select_idx);
> > 
> > This looks wrong. Shouldn't it be:
> > 
> > return ((vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &&
> >         (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & (1 << select_idx)));
> > 
> >> +	else
> >> +		return (vcpu_sys_reg(vcpu, c9_PMCR) & ARMV8_PMCR_E) &
> >> +		       (vcpu_sys_reg(vcpu, c9_PMCNTENSET) >> select_idx);
> >> +}
> > 
> > Also, I don't really see why we need to check the 32bit version, which
> > has the exact same content.
> > 
> >> +
> >> +static inline struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
> >> +{
> >> +	struct kvm_pmu *pmu;
> >> +	struct kvm_vcpu_arch *vcpu_arch;
> >> +
> >> +	pmc -= pmc->idx;
> >> +	pmu = container_of(pmc, struct kvm_pmu, pmc[0]);
> >> +	vcpu_arch = container_of(pmu, struct kvm_vcpu_arch, pmu);
> >> +	return container_of(vcpu_arch, struct kvm_vcpu, arch);
> >> +}
> >> +
> >> +/**
> >> + * kvm_pmu_stop_counter - stop PMU counter
> >> + * @pmc: The PMU counter pointer
> >> + *
> >> + * If this counter has been configured to monitor some event, release it here.
> >> + */
> >> +static void kvm_pmu_stop_counter(struct kvm_pmc *pmc)
> >> +{
> >> +	struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
> >> +	u64 counter;
> >> +
> >> +	if (pmc->perf_event) {
> >> +		counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
> >> +		if (!vcpu_mode_is_32bit(vcpu))
> >> +			vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + pmc->idx) = counter;
> >> +		else
> >> +			vcpu_cp15(vcpu, c14_PMEVCNTR0 + pmc->idx) = counter;
> > 
> > Same thing - we don't need to make a difference between 32 and 64bit.
> > 
> So it's fine to drop all the vcpu_mode_is_32bit(vcpu) check of this
> series? The only one we should take care is the PMCCNTR, right?

Yes, mostly. As long as you only reason on the 64bit register set,
you're pretty safe, and that in turn solves all kind of ugly endianness
issues.

> >> +
> >> +		perf_event_release_kernel(pmc->perf_event);
> >> +		pmc->perf_event = NULL;
> >> +	}
> >> +}
> >> +
> >> +/**
> >> + * kvm_pmu_set_counter_event_type - set selected counter to monitor some event
> >> + * @vcpu: The vcpu pointer
> >> + * @data: The data guest writes to PMXEVTYPER_EL0
> >> + * @select_idx: The number of selected counter
> >> + *
> >> + * When OS accesses PMXEVTYPER_EL0, that means it wants to set a PMC to count an
> >> + * event with given hardware event number. Here we call perf_event API to
> >> + * emulate this action and create a kernel perf event for it.
> >> + */
> >> +void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
> >> +				    u32 select_idx)
> >> +{
> >> +	struct kvm_pmu *pmu = &vcpu->arch.pmu;
> >> +	struct kvm_pmc *pmc = &pmu->pmc[select_idx];
> >> +	struct perf_event *event;
> >> +	struct perf_event_attr attr;
> >> +	u32 eventsel;
> >> +	u64 counter;
> >> +
> >> +	kvm_pmu_stop_counter(pmc);
> > 
> > Wait. I didn't realize this before, but you have the vcpu right here.
> > Why don't you pass it as a parameter to kvm_pmu_stop_counter and avoid
> > the kvm_pmc_to_vcpu thing altogether?
> > 
> Yeah, we could pass vcpu as a parameter for this function. But the
> kvm_pmc_to_vcpu helper is also used in kvm_pmu_perf_overflow() and
> within kvm_pmu_perf_overflow it needs the pmc->idx, we couldn't pass
> vcpu as a parameter, so this helper is necessary for kvm_pmu_perf_overflow.

OK. Then keep the helper with kvm_pmu_perf_overflow, and pass the the
vcpu as a parameter to the leaf functions.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

  reply	other threads:[~2015-12-09  8:23 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-08 12:47 [PATCH v6 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-12-08 13:37   ` Marc Zyngier
2015-12-08 13:53     ` Will Deacon
2015-12-08 14:10       ` Marc Zyngier
2015-12-08 14:14         ` Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 04/21] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 05/21] KVM: ARM64: Add reset and access handlers for PMSELR register Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register Shannon Zhao
2015-12-08 14:23   ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-12-08 15:43   ` Marc Zyngier
2015-12-09  7:38     ` Shannon Zhao
2015-12-09  8:23       ` Marc Zyngier [this message]
2015-12-08 12:47 ` [PATCH v6 08/21] KVM: ARM64: Add access handler for PMEVTYPERn and PMCCFILTR register Shannon Zhao
2015-12-08 16:17   ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 09/21] KVM: ARM64: Add access handler for PMXEVTYPER register Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 10/21] KVM: ARM64: Add access handler for PMEVCNTRn and PMCCNTR register Shannon Zhao
2015-12-08 16:30   ` Marc Zyngier
2015-12-10 11:36     ` Shannon Zhao
2015-12-10 12:07       ` Marc Zyngier
2015-12-10 13:23         ` Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 11/21] KVM: ARM64: Add access handler for PMXEVCNTR register Shannon Zhao
2015-12-08 16:33   ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 12/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-12-08 16:42   ` Marc Zyngier
2015-12-09  8:35     ` Shannon Zhao
2015-12-09  8:56       ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 13/21] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 14/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-12-08 16:59   ` Marc Zyngier
2015-12-09  8:47     ` Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 15/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register Shannon Zhao
2015-12-08 17:03   ` Marc Zyngier
2015-12-09  9:18     ` Shannon Zhao
2015-12-09  9:49       ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 16/21] KVM: ARM64: Add reset and access handlers for PMSWINC register Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 17/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-12-08 17:36   ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 18/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-12-08 17:37   ` Marc Zyngier
2015-12-08 12:47 ` [PATCH v6 19/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 20/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-12-08 12:47 ` [PATCH v6 21/21] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-12-08 17:43   ` Marc Zyngier
2015-12-08 17:56 ` [PATCH v6 00/21] KVM: ARM64: Add guest PMU support Marc Zyngier

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