* [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported
@ 2015-11-16 8:48 pmallapp at broadcom.com
2015-11-17 17:46 ` Will Deacon
0 siblings, 1 reply; 5+ messages in thread
From: pmallapp at broadcom.com @ 2015-11-16 8:48 UTC (permalink / raw)
To: linux-arm-kernel
From: Prem Mallappa <pmallapp@broadcom.com>
Also fix the STALLD check.
Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
---
drivers/iommu/arm-smmu-v3.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index ed409cb..804671c 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -38,7 +38,9 @@
#define IDR0_ST_LVL_SHIFT 27
#define IDR0_ST_LVL_MASK 0x3
#define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT)
-#define IDR0_STALL_MODEL (3 << 24)
+#define IDR0_STALL_SHIFT 24
+#define IDR0_STALL_MODEL_STALL 0x0
+#define IDR0_STALL_MODEL_FORCE 0x2
#define IDR0_TTENDIAN_SHIFT 21
#define IDR0_TTENDIAN_MASK 0x3
#define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT)
@@ -1051,12 +1053,14 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
STRTAB_STE_1_S1C_CACHE_WBRA
<< STRTAB_STE_1_S1COR_SHIFT |
STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT |
- STRTAB_STE_1_S1STALLD |
#ifdef CONFIG_PCI_ATS
STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
#endif
STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
+ if (smmu->features & ARM_SMMU_FEAT_STALLS)
+ dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
+
val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK
<< STRTAB_STE_0_S1CTXPTR_SHIFT) |
STRTAB_STE_0_CFG_S1_TRANS;
@@ -2483,8 +2487,14 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu)
dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n",
coherent ? "true" : "false");
- if (reg & IDR0_STALL_MODEL)
+ switch ((reg >> IDR0_STALL_SHIFT) & 0x3) {
+ case IDR0_STALL_MODEL_STALL:
+ case IDR0_STALL_MODEL_FORCE:
smmu->features |= ARM_SMMU_FEAT_STALLS;
+ break;
+ default:
+ break;
+ }
if (reg & IDR0_S1P)
smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
--
2.6.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported
2015-11-16 8:48 [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported pmallapp at broadcom.com
@ 2015-11-17 17:46 ` Will Deacon
2015-11-24 5:30 ` Prem (Premachandra) Mallappa
0 siblings, 1 reply; 5+ messages in thread
From: Will Deacon @ 2015-11-17 17:46 UTC (permalink / raw)
To: linux-arm-kernel
Hi Prem,
Thanks for the patch. Just a few minor comments...
On Mon, Nov 16, 2015 at 02:18:20PM +0530, pmallapp at broadcom.com wrote:
> From: Prem Mallappa <pmallapp@broadcom.com>
>
> Also fix the STALLD check.
Can you extend the commit message please to explain that it is ILLEGAL
to set STE.S1STALLD to 1 if stage 1 is enabled and either the stall or
terminate models are not supported?
> Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
> ---
> drivers/iommu/arm-smmu-v3.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index ed409cb..804671c 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -38,7 +38,9 @@
> #define IDR0_ST_LVL_SHIFT 27
> #define IDR0_ST_LVL_MASK 0x3
> #define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT)
> -#define IDR0_STALL_MODEL (3 << 24)
> +#define IDR0_STALL_SHIFT 24
To keep the style consistent, can you also add IDR0_STALL_MASK please...
> +#define IDR0_STALL_MODEL_STALL 0x0
> +#define IDR0_STALL_MODEL_FORCE 0x2
... and shift these guys left by IDR0_STALL_SHIFT?
>
> #define IDR0_TTENDIAN_SHIFT 21
> #define IDR0_TTENDIAN_MASK 0x3
> #define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT)
> @@ -1051,12 +1053,14 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
> STRTAB_STE_1_S1C_CACHE_WBRA
> << STRTAB_STE_1_S1COR_SHIFT |
> STRTAB_STE_1_S1C_SH_ISH << STRTAB_STE_1_S1CSH_SHIFT |
> - STRTAB_STE_1_S1STALLD |
> #ifdef CONFIG_PCI_ATS
> STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
> #endif
> STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
>
> + if (smmu->features & ARM_SMMU_FEAT_STALLS)
> + dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
> +
> val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK
> << STRTAB_STE_0_S1CTXPTR_SHIFT) |
> STRTAB_STE_0_CFG_S1_TRANS;
> @@ -2483,8 +2487,14 @@ static int arm_smmu_device_probe(struct arm_smmu_device *smmu)
> dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n",
> coherent ? "true" : "false");
>
> - if (reg & IDR0_STALL_MODEL)
> + switch ((reg >> IDR0_STALL_SHIFT) & 0x3) {
Then structure this more like the TTENDIAN code:
switch (reg & IDR0_STALL_MASK << IDR0_STALL_SHIFT) {
> + case IDR0_STALL_MODEL_STALL:
> + case IDR0_STALL_MODEL_FORCE:
> smmu->features |= ARM_SMMU_FEAT_STALLS;
> + break;
> + default:
> + break;
> + }
I think you can drop the default case, or does GCC complain?
Will
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported
2015-11-17 17:46 ` Will Deacon
@ 2015-11-24 5:30 ` Prem (Premachandra) Mallappa
2015-12-11 19:53 ` Will Deacon
0 siblings, 1 reply; 5+ messages in thread
From: Prem (Premachandra) Mallappa @ 2015-11-24 5:30 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Will Deacon [mailto:will.deacon at arm.com]
> Sent: 17 November 2015 11:17 PM
> To: Prem (Premachandra) Mallappa
> Cc: iommu at lists.linux-foundation.org; linux-arm-kernel at lists.infradead.org;
> Jayachandran Chandrashekaran Nair
> Subject: Re: [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when
> supported
>
> Hi Prem,
>
> Thanks for the patch. Just a few minor comments...
>
> On Mon, Nov 16, 2015 at 02:18:20PM +0530, pmallapp at broadcom.com
> wrote:
> > From: Prem Mallappa <pmallapp@broadcom.com>
> >
> > Also fix the STALLD check.
>
> Can you extend the commit message please to explain that it is ILLEGAL to
> set STE.S1STALLD to 1 if stage 1 is enabled and either the stall or terminate
> models are not supported?
>
> > Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
> > ---
> > drivers/iommu/arm-smmu-v3.c | 16 +++++++++++++---
> > 1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-
> v3.c
> > index ed409cb..804671c 100644
> > --- a/drivers/iommu/arm-smmu-v3.c
> > +++ b/drivers/iommu/arm-smmu-v3.c
> > @@ -38,7 +38,9 @@
> > #define IDR0_ST_LVL_SHIFT 27
> > #define IDR0_ST_LVL_MASK 0x3
> > #define IDR0_ST_LVL_2LVL (1 << IDR0_ST_LVL_SHIFT)
> > -#define IDR0_STALL_MODEL (3 << 24)
> > +#define IDR0_STALL_SHIFT 24
>
> To keep the style consistent, can you also add IDR0_STALL_MASK please...
>
> > +#define IDR0_STALL_MODEL_STALL 0x0
> > +#define IDR0_STALL_MODEL_FORCE 0x2
>
> ... and shift these guys left by IDR0_STALL_SHIFT?
>
> >
> > #define IDR0_TTENDIAN_SHIFT 21
> > #define IDR0_TTENDIAN_MASK 0x3
> > #define IDR0_TTENDIAN_LE (2 << IDR0_TTENDIAN_SHIFT)
> > @@ -1051,12 +1053,14 @@ static void arm_smmu_write_strtab_ent(struct
> arm_smmu_device *smmu, u32 sid,
> > STRTAB_STE_1_S1C_CACHE_WBRA
> > << STRTAB_STE_1_S1COR_SHIFT |
> > STRTAB_STE_1_S1C_SH_ISH <<
> STRTAB_STE_1_S1CSH_SHIFT |
> > - STRTAB_STE_1_S1STALLD |
> > #ifdef CONFIG_PCI_ATS
> > STRTAB_STE_1_EATS_TRANS <<
> STRTAB_STE_1_EATS_SHIFT | #endif
> > STRTAB_STE_1_STRW_NSEL1 <<
> STRTAB_STE_1_STRW_SHIFT);
> >
> > + if (smmu->features & ARM_SMMU_FEAT_STALLS)
> > + dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
> > +
> > val |= (ste->s1_cfg->cdptr_dma &
> STRTAB_STE_0_S1CTXPTR_MASK
> > << STRTAB_STE_0_S1CTXPTR_SHIFT) |
> > STRTAB_STE_0_CFG_S1_TRANS;
> > @@ -2483,8 +2487,14 @@ static int arm_smmu_device_probe(struct
> arm_smmu_device *smmu)
> > dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-
> coherent property (%s)\n",
> > coherent ? "true" : "false");
> >
> > - if (reg & IDR0_STALL_MODEL)
> > + switch ((reg >> IDR0_STALL_SHIFT) & 0x3) {
>
> Then structure this more like the TTENDIAN code:
>
> switch (reg & IDR0_STALL_MASK << IDR0_STALL_SHIFT) {
>
> > + case IDR0_STALL_MODEL_STALL:
> > + case IDR0_STALL_MODEL_FORCE:
> > smmu->features |= ARM_SMMU_FEAT_STALLS;
> > + break;
> > + default:
> > + break;
> > + }
>
> I think you can drop the default case, or does GCC complain?
>
> Will
Thanks for comments, I was on holiday, I'll send updated patch along with 2 more soon.
/Prem
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported
2015-11-24 5:30 ` Prem (Premachandra) Mallappa
@ 2015-12-11 19:53 ` Will Deacon
2015-12-12 5:31 ` Prem (Premachandra) Mallappa
0 siblings, 1 reply; 5+ messages in thread
From: Will Deacon @ 2015-12-11 19:53 UTC (permalink / raw)
To: linux-arm-kernel
Hi Prem,
On Tue, Nov 24, 2015 at 05:30:37AM +0000, Prem (Premachandra) Mallappa wrote:
> Thanks for comments, I was on holiday, I'll send updated patch along with
> 2 more soon.
Any update on this patch?
Cheers,
Will
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported
2015-12-11 19:53 ` Will Deacon
@ 2015-12-12 5:31 ` Prem (Premachandra) Mallappa
0 siblings, 0 replies; 5+ messages in thread
From: Prem (Premachandra) Mallappa @ 2015-12-12 5:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi Will,
It is ready, in internal review, will be sending it in a day.
/Prem
> -----Original Message-----
> From: Will Deacon [mailto:will.deacon at arm.com]
> Sent: 12 December 2015 01:23 AM
> To: Prem (Premachandra) Mallappa
> Cc: iommu at lists.linux-foundation.org; linux-arm-kernel at lists.infradead.org;
> Jayachandran Chandrashekaran Nair
> Subject: Re: [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when
> supported
>
> Hi Prem,
>
> On Tue, Nov 24, 2015 at 05:30:37AM +0000, Prem (Premachandra) Mallappa
> wrote:
> > Thanks for comments, I was on holiday, I'll send updated patch along with
> > 2 more soon.
>
> Any update on this patch?
>
> Cheers,
>
> Will
^ permalink raw reply [flat|nested] 5+ messages in thread
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2015-11-16 8:48 [PATCH] IOMMU: arm-smmu-v3: Use STE.S1STALLD only when supported pmallapp at broadcom.com
2015-11-17 17:46 ` Will Deacon
2015-11-24 5:30 ` Prem (Premachandra) Mallappa
2015-12-11 19:53 ` Will Deacon
2015-12-12 5:31 ` Prem (Premachandra) Mallappa
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