From: helgaas@kernel.org (Bjorn Helgaas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 3/5] PCI: qcom: Add Qualcomm PCIe controller driver
Date: Wed, 16 Dec 2015 15:53:04 -0600 [thread overview]
Message-ID: <20151216215304.GB27791@localhost> (raw)
In-Reply-To: <1449149725-27607-4-git-send-email-stanimir.varbanov@linaro.org>
On Thu, Dec 03, 2015 at 03:35:22PM +0200, Stanimir Varbanov wrote:
> From: Stanimir Varbanov <svarbanov@mm-sol.com>
>
> The PCIe driver reuse the Designware common code for host
> and MSI initialization, and also program the Qualcomm
> application specific registers.
>
> Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
> ---
> MAINTAINERS | 7 +
> drivers/pci/host/Kconfig | 10 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-qcom.c | 624 ++++++++++++++++++++++++++++++++++++++++++
> +#define PCIE20_CAP 0x70
> +#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
> +#define PCIE20_CAP_LINKCTRLSTATUS_LINK_UP BIT(29)
This looks like it could be referring to a standard PCIe Capability;
could you use the existing PCI_EXP_LNKSTA and PCI_EXP_LNKSTA_DLLLA
symbols here? And readw() instead of readl()?
> +static int qcom_pcie_enable_link_training(struct qcom_pcie *pcie)
> +{
> + struct device *dev = pcie->dev;
> + u32 val;
> + int ret;
> +
> + /* enable link training */
> + val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
> + val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
> + writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
> +
> + /* wait for up to 100ms for the link to come up */
> + ret = readl_poll_timeout(pcie->elbi + PCIE20_ELBI_SYS_STTS, val,
> + val & XMLH_LINK_UP, LINKUP_DELAY_US,
> + LINKUP_TIMEOUT_US);
> +
> + if (ret < 0 || !dw_pcie_link_up(&pcie->pp)) {
> + dev_err(dev, "link initialization failed\n");
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
This looks a lot like the *_establish_link() functions in other
DesignWare-based drivers. Can you make it look even more similar,
e.g., by renaming it to qcom_pcie_establish_link() and maybe moving
some of the PHY functionality here?
readl_poll_timeout() is nice and avoids the hand-coded timeout loop
the other drivers use. But is there benefit in checking for
XMLH_LINK_UP, or could you simply poll dw_pcie_link_up() like the
others do? If it's sufficient, I'd prefer using dw_pcie_link_up()
by itself because it's a little more generic.
Bjorn
next prev parent reply other threads:[~2015-12-16 21:53 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-03 13:35 [PATCH v4 0/5] Qualcomm PCIe driver and designware fixes Stanimir Varbanov
2015-12-03 13:35 ` [PATCH v4 1/5] PCI: designware: add memory barrier after enabling region Stanimir Varbanov
2015-12-08 9:01 ` Stanimir Varbanov
2015-12-09 4:40 ` Pratyush Anand
2015-12-09 9:52 ` Arnd Bergmann
2015-12-09 10:29 ` Stanimir Varbanov
2015-12-09 10:23 ` Russell King - ARM Linux
2015-12-11 4:05 ` Pratyush Anand
2015-12-11 5:48 ` Jisheng Zhang
2015-12-22 12:36 ` Jingoo Han
2015-12-17 15:45 ` Stanimir Varbanov
2015-12-17 15:51 ` Pratyush Anand
2015-12-03 13:35 ` [PATCH v4 2/5] DT: PCI: qcom: Document PCIe devicetree bindings Stanimir Varbanov
2015-12-03 20:42 ` Rob Herring
2015-12-03 13:35 ` [PATCH v4 3/5] PCI: qcom: Add Qualcomm PCIe controller driver Stanimir Varbanov
2015-12-15 8:24 ` Stanimir Varbanov
2015-12-16 21:17 ` Bjorn Helgaas
2015-12-16 21:53 ` Bjorn Helgaas [this message]
2015-12-17 13:18 ` Stanimir Varbanov
2015-12-17 21:15 ` Bjorn Helgaas
2015-12-03 13:35 ` [PATCH v4 4/5] ARM: dts: apq8064: add pcie devicetree node Stanimir Varbanov
2015-12-03 13:35 ` [PATCH v4 5/5] ARM: dts: ifc6410: enable pcie dt node for this board Stanimir Varbanov
2015-12-17 21:55 ` Bjorn Andersson
2015-12-18 9:57 ` Stanimir Varbanov
2015-12-07 17:33 ` [PATCH v4 0/5] Qualcomm PCIe driver and designware fixes Srinivas Kandagatla
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