* [PATCH] clk: mediatek: Allow changing PLL rate when it is off @ 2016-01-08 8:16 James Liao 2016-01-08 9:15 ` Sascha Hauer 0 siblings, 1 reply; 5+ messages in thread From: James Liao @ 2016-01-08 8:16 UTC (permalink / raw) To: linux-arm-kernel Some modules may need to change its clock rate before turn on it. So changing PLL's rate when it is off should be allowed. This patch removes PLL enabled check before set rate, so that PLLs can set new frequency even if they are off. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> --- drivers/clk/mediatek/clk-pll.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 966cab1..8e31fae 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) { u32 con1, val; - int pll_en; - - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; /* set postdiv */ val = readl(pll->pd_addr); @@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, con1 = readl(pll->base_addr + REG_CON1); - if (pll_en) - con1 |= CON0_PCW_CHG; + con1 |= CON0_PCW_CHG; writel(con1, pll->base_addr + REG_CON1); if (pll->tuner_addr) writel(con1 + 1, pll->tuner_addr); - if (pll_en) - udelay(20); + udelay(20); } /* -- 1.9.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] clk: mediatek: Allow changing PLL rate when it is off 2016-01-08 8:16 [PATCH] clk: mediatek: Allow changing PLL rate when it is off James Liao @ 2016-01-08 9:15 ` Sascha Hauer 2016-01-08 9:48 ` James Liao 0 siblings, 1 reply; 5+ messages in thread From: Sascha Hauer @ 2016-01-08 9:15 UTC (permalink / raw) To: linux-arm-kernel Hi James, On Fri, Jan 08, 2016 at 04:16:37PM +0800, James Liao wrote: > Some modules may need to change its clock rate before turn on it. > So changing PLL's rate when it is off should be allowed. > This patch removes PLL enabled check before set rate, so that > PLLs can set new frequency even if they are off. This sounds like the software refused to change the rate on disabled PLLs, but this is not the case. > > Signed-off-by: James Liao <jamesjj.liao@mediatek.com> > --- > drivers/clk/mediatek/clk-pll.c | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index 966cab1..8e31fae 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c > @@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > int postdiv) > { > u32 con1, val; > - int pll_en; > - > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > /* set postdiv */ > val = readl(pll->pd_addr); > @@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > con1 = readl(pll->base_addr + REG_CON1); > > - if (pll_en) > - con1 |= CON0_PCW_CHG; > + con1 |= CON0_PCW_CHG; This bit is described as "Feedback divide ratio update". To me this sounds like we have to inform the hardware that the PLL registers have been updated. The current code only sets this bit when the PLL is enabled which sounds sane to me. > > writel(con1, pll->base_addr + REG_CON1); > if (pll->tuner_addr) > writel(con1 + 1, pll->tuner_addr); > > - if (pll_en) > - udelay(20); > + udelay(20); We seem to have to wait here until the PLL is really running at the new frequency. Normally we don't have to do this when the PLL is disabled. I'm sure this patch solves a real problem, from looking at it it's just not clear to me what the problem is. Could you clarify this a bit? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] clk: mediatek: Allow changing PLL rate when it is off 2016-01-08 9:15 ` Sascha Hauer @ 2016-01-08 9:48 ` James Liao 2016-01-08 11:21 ` Sascha Hauer 0 siblings, 1 reply; 5+ messages in thread From: James Liao @ 2016-01-08 9:48 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, On Fri, 2016-01-08 at 10:15 +0100, Sascha Hauer wrote: > On Fri, Jan 08, 2016 at 04:16:37PM +0800, James Liao wrote: > > Some modules may need to change its clock rate before turn on it. > > So changing PLL's rate when it is off should be allowed. > > This patch removes PLL enabled check before set rate, so that > > PLLs can set new frequency even if they are off. > > This sounds like the software refused to change the rate on disabled > PLLs, but this is not the case. In fact the major change of this patch is trigger (set) CON0_PCW_CHG no matter PLL is on or not. > > > > Signed-off-by: James Liao <jamesjj.liao@mediatek.com> > > --- > > drivers/clk/mediatek/clk-pll.c | 9 ++------- > > 1 file changed, 2 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > > index 966cab1..8e31fae 100644 > > --- a/drivers/clk/mediatek/clk-pll.c > > +++ b/drivers/clk/mediatek/clk-pll.c > > @@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > int postdiv) > > { > > u32 con1, val; > > - int pll_en; > > - > > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > > > /* set postdiv */ > > val = readl(pll->pd_addr); > > @@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > > > con1 = readl(pll->base_addr + REG_CON1); > > > > - if (pll_en) > > - con1 |= CON0_PCW_CHG; > > + con1 |= CON0_PCW_CHG; > > This bit is described as "Feedback divide ratio update". To me this > sounds like we have to inform the hardware that the PLL registers have > been updated. The current code only sets this bit when the PLL is > enabled which sounds sane to me. > > > > > writel(con1, pll->base_addr + REG_CON1); > > if (pll->tuner_addr) > > writel(con1 + 1, pll->tuner_addr); > > > > - if (pll_en) > > - udelay(20); > > + udelay(20); > > We seem to have to wait here until the PLL is really running at the new > frequency. Normally we don't have to do this when the PLL is disabled. > > I'm sure this patch solves a real problem, from looking at it it's just > not clear to me what the problem is. Could you clarify this a bit? On MT8173 for example, ARMPLL's enable bit can be controlled by other HW. That means ARMPLL may be turned on even if we (CPU / SW) set ARMPLL's enable bit as 0. In this case, SW may want and can still change ARMPLL's rate by changing its pcw and postdiv settings. But without this patch, new pcw setting will not be applied because its enable bit is 0. Best regards, James ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] clk: mediatek: Allow changing PLL rate when it is off 2016-01-08 9:48 ` James Liao @ 2016-01-08 11:21 ` Sascha Hauer 2016-01-11 1:39 ` James Liao 0 siblings, 1 reply; 5+ messages in thread From: Sascha Hauer @ 2016-01-08 11:21 UTC (permalink / raw) To: linux-arm-kernel On Fri, Jan 08, 2016 at 05:48:53PM +0800, James Liao wrote: > Hi Sascha, > > On Fri, 2016-01-08 at 10:15 +0100, Sascha Hauer wrote: > > On Fri, Jan 08, 2016 at 04:16:37PM +0800, James Liao wrote: > > > Some modules may need to change its clock rate before turn on it. > > > So changing PLL's rate when it is off should be allowed. > > > This patch removes PLL enabled check before set rate, so that > > > PLLs can set new frequency even if they are off. > > > > This sounds like the software refused to change the rate on disabled > > PLLs, but this is not the case. > > In fact the major change of this patch is trigger (set) CON0_PCW_CHG no > matter PLL is on or not. > > > > > > > Signed-off-by: James Liao <jamesjj.liao@mediatek.com> > > > --- > > > drivers/clk/mediatek/clk-pll.c | 9 ++------- > > > 1 file changed, 2 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > > > index 966cab1..8e31fae 100644 > > > --- a/drivers/clk/mediatek/clk-pll.c > > > +++ b/drivers/clk/mediatek/clk-pll.c > > > @@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > > int postdiv) > > > { > > > u32 con1, val; > > > - int pll_en; > > > - > > > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > > > > > /* set postdiv */ > > > val = readl(pll->pd_addr); > > > @@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > > > > > con1 = readl(pll->base_addr + REG_CON1); > > > > > > - if (pll_en) > > > - con1 |= CON0_PCW_CHG; > > > + con1 |= CON0_PCW_CHG; > > > > This bit is described as "Feedback divide ratio update". To me this > > sounds like we have to inform the hardware that the PLL registers have > > been updated. The current code only sets this bit when the PLL is > > enabled which sounds sane to me. > > > > > > > > writel(con1, pll->base_addr + REG_CON1); > > > if (pll->tuner_addr) > > > writel(con1 + 1, pll->tuner_addr); > > > > > > - if (pll_en) > > > - udelay(20); > > > + udelay(20); > > > > We seem to have to wait here until the PLL is really running at the new > > frequency. Normally we don't have to do this when the PLL is disabled. > > > > I'm sure this patch solves a real problem, from looking at it it's just > > not clear to me what the problem is. Could you clarify this a bit? > > On MT8173 for example, ARMPLL's enable bit can be controlled by other > HW. That means ARMPLL may be turned on even if we (CPU / SW) set > ARMPLL's enable bit as 0. In this case, SW may want and can still change > ARMPLL's rate by changing its pcw and postdiv settings. But without this > patch, new pcw setting will not be applied because its enable bit is 0. Ok, thanks for explaining. Could you add that to the commit message? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] clk: mediatek: Allow changing PLL rate when it is off 2016-01-08 11:21 ` Sascha Hauer @ 2016-01-11 1:39 ` James Liao 0 siblings, 0 replies; 5+ messages in thread From: James Liao @ 2016-01-11 1:39 UTC (permalink / raw) To: linux-arm-kernel Hi Sascha, On Fri, 2016-01-08 at 12:21 +0100, Sascha Hauer wrote: > On Fri, Jan 08, 2016 at 05:48:53PM +0800, James Liao wrote: > > On Fri, 2016-01-08 at 10:15 +0100, Sascha Hauer wrote: > > > On Fri, Jan 08, 2016 at 04:16:37PM +0800, James Liao wrote: > > > > Some modules may need to change its clock rate before turn on it. > > > > So changing PLL's rate when it is off should be allowed. > > > > This patch removes PLL enabled check before set rate, so that > > > > PLLs can set new frequency even if they are off. > > > > > > This sounds like the software refused to change the rate on disabled > > > PLLs, but this is not the case. > > > > In fact the major change of this patch is trigger (set) CON0_PCW_CHG no > > matter PLL is on or not. > > > > > > > > > > Signed-off-by: James Liao <jamesjj.liao@mediatek.com> > > > > --- > > > > drivers/clk/mediatek/clk-pll.c | 9 ++------- > > > > 1 file changed, 2 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > > > > index 966cab1..8e31fae 100644 > > > > --- a/drivers/clk/mediatek/clk-pll.c > > > > +++ b/drivers/clk/mediatek/clk-pll.c > > > > @@ -91,9 +91,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > > > int postdiv) > > > > { > > > > u32 con1, val; > > > > - int pll_en; > > > > - > > > > - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; > > > > > > > > /* set postdiv */ > > > > val = readl(pll->pd_addr); > > > > @@ -114,15 +111,13 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > > > > > > > > con1 = readl(pll->base_addr + REG_CON1); > > > > > > > > - if (pll_en) > > > > - con1 |= CON0_PCW_CHG; > > > > + con1 |= CON0_PCW_CHG; > > > > > > This bit is described as "Feedback divide ratio update". To me this > > > sounds like we have to inform the hardware that the PLL registers have > > > been updated. The current code only sets this bit when the PLL is > > > enabled which sounds sane to me. > > > > > > > > > > > writel(con1, pll->base_addr + REG_CON1); > > > > if (pll->tuner_addr) > > > > writel(con1 + 1, pll->tuner_addr); > > > > > > > > - if (pll_en) > > > > - udelay(20); > > > > + udelay(20); > > > > > > We seem to have to wait here until the PLL is really running at the new > > > frequency. Normally we don't have to do this when the PLL is disabled. > > > > > > I'm sure this patch solves a real problem, from looking at it it's just > > > not clear to me what the problem is. Could you clarify this a bit? > > > > On MT8173 for example, ARMPLL's enable bit can be controlled by other > > HW. That means ARMPLL may be turned on even if we (CPU / SW) set > > ARMPLL's enable bit as 0. In this case, SW may want and can still change > > ARMPLL's rate by changing its pcw and postdiv settings. But without this > > patch, new pcw setting will not be applied because its enable bit is 0. > > Ok, thanks for explaining. Could you add that to the commit message? OK. I'll send a new patch with these comments. Best regards, James ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-01-11 1:39 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-01-08 8:16 [PATCH] clk: mediatek: Allow changing PLL rate when it is off James Liao 2016-01-08 9:15 ` Sascha Hauer 2016-01-08 9:48 ` James Liao 2016-01-08 11:21 ` Sascha Hauer 2016-01-11 1:39 ` James Liao
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).