[PATCH v2 0/2] SoC: rockchip: support power domain for RK3368

[PATCH v2 0/2] SoC: rockchip: support power domain for RK3368

[zhangqing]

add pd id in rk3368-power.h
modify pm_domains.c to support RK3368 SoC.

zhangqing (2):
  dt-bindings: add power-domain header for RK3368 SoCs
  soc: rockchip: power-domain: Modify power domain driver for rk3368

 drivers/soc/rockchip/pm_domains.c        | 33 ++++++++++++++++++++++++++++++++
 include/dt-bindings/power/rk3368-power.h | 28 +++++++++++++++++++++++++++
 2 files changed, 61 insertions(+)
 create mode 100644 include/dt-bindings/power/rk3368-power.h

-- 
1.9.1

[PATCH v2 1/2] dt-bindings: add power-domain header for RK3368 SoCs

[zhangqing]

According to a description from TRM, add all the power domains.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
---
 include/dt-bindings/power/rk3368-power.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/power/rk3368-power.h

diff --git a/include/dt-bindings/power/rk3368-power.h b/include/dt-bindings/power/rk3368-power.h
new file mode 100644
index 0000000..93633d5
--- /dev/null
+++ b/include/dt-bindings/power/rk3368-power.h
@@ -0,0 +1,28 @@
+#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__
+#define __DT_BINDINGS_POWER_RK3368_POWER_H__
+
+/* VD_CORE */
+#define RK3368_PD_A53_L0	0
+#define RK3368_PD_A53_L1	1
+#define RK3368_PD_A53_L2	2
+#define RK3368_PD_A53_L3	3
+#define RK3368_PD_SCU_L		4
+#define RK3368_PD_A53_B0	5
+#define RK3368_PD_A53_B1	6
+#define RK3368_PD_A53_B2	7
+#define RK3368_PD_A53_B3	8
+#define RK3368_PD_SCU_B		9
+
+/* VD_LOGIC */
+#define RK3368_PD_BUS		10
+#define RK3368_PD_PERI		11
+#define RK3368_PD_VIO		12
+#define RK3368_PD_ALIVE		13
+#define RK3368_PD_VIDEO		14
+#define RK3368_PD_GPU_0		15
+#define RK3368_PD_GPU_1		16
+
+/* VD_PMU */
+#define RK3368_PD_PMU		17
+
+#endif
-- 
1.9.1

[PATCH v2 1/2] dt-bindings: add power-domain header for RK3368 SoCs

[Mark Rutland]

On Fri, Jan 08, 2016 at 10:37:40AM -0800, zhangqing wrote:
> According to a description from TRM, add all the power domains.
> 
> Signed-off-by: zhangqing <zhangqing@rock-chips.com>
> ---
>  include/dt-bindings/power/rk3368-power.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>  create mode 100644 include/dt-bindings/power/rk3368-power.h

You also need to update the related binding file, for the new compatible
string.

Mark.

> 
> diff --git a/include/dt-bindings/power/rk3368-power.h b/include/dt-bindings/power/rk3368-power.h
> new file mode 100644
> index 0000000..93633d5
> --- /dev/null
> +++ b/include/dt-bindings/power/rk3368-power.h
> @@ -0,0 +1,28 @@
> +#ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__
> +#define __DT_BINDINGS_POWER_RK3368_POWER_H__
> +
> +/* VD_CORE */
> +#define RK3368_PD_A53_L0	0
> +#define RK3368_PD_A53_L1	1
> +#define RK3368_PD_A53_L2	2
> +#define RK3368_PD_A53_L3	3
> +#define RK3368_PD_SCU_L		4
> +#define RK3368_PD_A53_B0	5
> +#define RK3368_PD_A53_B1	6
> +#define RK3368_PD_A53_B2	7
> +#define RK3368_PD_A53_B3	8
> +#define RK3368_PD_SCU_B		9
> +
> +/* VD_LOGIC */
> +#define RK3368_PD_BUS		10
> +#define RK3368_PD_PERI		11
> +#define RK3368_PD_VIO		12
> +#define RK3368_PD_ALIVE		13
> +#define RK3368_PD_VIDEO		14
> +#define RK3368_PD_GPU_0		15
> +#define RK3368_PD_GPU_1		16
> +
> +/* VD_PMU */
> +#define RK3368_PD_PMU		17
> +
> +#endif
> -- 
> 1.9.1
> 
> 

[PATCH v2 2/2] soc: rockchip: power-domain: Modify power domain driver for rk3368

[zhangqing]

This driver is modified to support RK3368 SoC.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
---
 drivers/soc/rockchip/pm_domains.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 534c589..6cdffb1 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -18,6 +18,7 @@
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
 #include <dt-bindings/power/rk3288-power.h>
+#include <dt-bindings/power/rk3368-power.h>
 
 struct rockchip_domain_info {
 	int pwr_mask;
@@ -75,6 +76,9 @@ struct rockchip_pmu {
 #define DOMAIN_RK3288(pwr, status, req)		\
 	DOMAIN(pwr, status, req, req, (req) + 16)
 
+#define DOMAIN_RK3368(pwr, status, req)		\
+	DOMAIN(pwr, status, req, (req) + 16, req)
+
 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
 {
 	struct rockchip_pmu *pmu = pd->pmu;
@@ -444,6 +448,14 @@ static const struct rockchip_domain_info rk3288_pm_domains[] = {
 	[RK3288_PD_GPU]		= DOMAIN_RK3288(9, 9, 2),
 };
 
+static const struct rockchip_domain_info rk3368_pm_domains[] = {
+	[RK3368_PD_PERI]	= DOMAIN_RK3368(13, 12, 6),
+	[RK3368_PD_VIO]		= DOMAIN_RK3368(15, 14, 8),
+	[RK3368_PD_VIDEO]	= DOMAIN_RK3368(14, 13, 7),
+	[RK3368_PD_GPU_0]	= DOMAIN_RK3368(16, 15, 2),
+	[RK3368_PD_GPU_1]	= DOMAIN_RK3368(17, 16, 2),
+};
+
 static const struct rockchip_pmu_info rk3288_pmu = {
 	.pwr_offset = 0x08,
 	.status_offset = 0x0c,
@@ -461,11 +473,32 @@ static const struct rockchip_pmu_info rk3288_pmu = {
 	.domain_info = rk3288_pm_domains,
 };
 
+static const struct rockchip_pmu_info rk3368_pmu = {
+	.pwr_offset = 0x0c,
+	.status_offset = 0x10,
+	.req_offset = 0x3c,
+	.idle_offset = 0x40,
+	.ack_offset = 0x40,
+
+	.core_pwrcnt_offset = 0x48,
+	.gpu_pwrcnt_offset = 0x50,
+
+	.core_power_transition_time = 24,
+	.gpu_power_transition_time = 24,
+
+	.num_domains = ARRAY_SIZE(rk3368_pm_domains),
+	.domain_info = rk3368_pm_domains,
+};
+
 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
 	{
 		.compatible = "rockchip,rk3288-power-controller",
 		.data = (void *)&rk3288_pmu,
 	},
+	{
+		.compatible = "rockchip,rk3368-power-controller",
+		.data = (void *)&rk3368_pmu,
+	},
 	{ /* sentinel */ },
 };
 
-- 
1.9.1