From: drjones@redhat.com (Andrew Jones)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function
Date: Thu, 28 Jan 2016 17:31:15 +0100 [thread overview]
Message-ID: <20160128163115.GC3807@hawk.localdomain> (raw)
In-Reply-To: <1453866709-20324-8-git-send-email-zhaoshenglong@huawei.com>
On Wed, Jan 27, 2016 at 11:51:35AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> When we use tools like perf on host, perf passes the event type and the
> id of this event type category to kernel, then kernel will map them to
> hardware event number and write this number to PMU PMEVTYPER<n>_EL0
> register. When getting the event number in KVM, directly use raw event
> type to create a perf_event for it.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm64/include/asm/pmu.h | 3 ++
> arch/arm64/kvm/Makefile | 1 +
> include/kvm/arm_pmu.h | 10 ++++
> virt/kvm/arm/pmu.c | 122 +++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 136 insertions(+)
> create mode 100644 virt/kvm/arm/pmu.c
>
> diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
> index 4406184..2588f9c 100644
> --- a/arch/arm64/include/asm/pmu.h
> +++ b/arch/arm64/include/asm/pmu.h
> @@ -21,6 +21,7 @@
>
> #define ARMV8_MAX_COUNTERS 32
> #define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
> +#define ARMV8_CYCLE_IDX (ARMV8_MAX_COUNTERS - 1)
I'm not sure we want to add this. It's name is wrong, as it's really
PMCNTENSET_EL0.C, and just a few lines above we have the idx defined
already (ARMV8_IDX_CYCLE_COUNTER), but as zero, because
arch/arm64/kernel/perf_event.c maps it that way.
I think we should do the same with the pmc array, i.e. map the cycle
counter to idx zero.
>
> /*
> * Per-CPU PMCR: config reg
> @@ -31,6 +32,8 @@
> #define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
> #define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
> #define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
> +/* Determines which PMCCNTR_EL0 bit generates an overflow */
> +#define ARMV8_PMCR_LC (1 << 6)
> #define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
> #define ARMV8_PMCR_N_MASK 0x1f
> #define ARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
> diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
> index caee9ee..122cff4 100644
> --- a/arch/arm64/kvm/Makefile
> +++ b/arch/arm64/kvm/Makefile
> @@ -26,3 +26,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v2-emul.o
> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
> kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
> +kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
> diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
> index 32fee2d..ee4b15c 100644
> --- a/include/kvm/arm_pmu.h
> +++ b/include/kvm/arm_pmu.h
> @@ -36,11 +36,21 @@ struct kvm_pmu {
> };
>
> #define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
> +u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
> +void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
> + u64 select_idx);
> #else
> struct kvm_pmu {
> };
>
> #define kvm_arm_pmu_v3_ready(v) (false)
> +static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
> + u64 select_idx)
> +{
> + return 0;
> +}
> +static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
> + u64 data, u64 select_idx) {}
> #endif
>
> #endif
> diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
> new file mode 100644
> index 0000000..673ec55
> --- /dev/null
> +++ b/virt/kvm/arm/pmu.c
> @@ -0,0 +1,122 @@
> +/*
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Shannon Zhao <shannon.zhao@linaro.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/kvm.h>
> +#include <linux/kvm_host.h>
> +#include <linux/perf_event.h>
> +#include <asm/kvm_emulate.h>
> +#include <kvm/arm_pmu.h>
> +
> +/**
> + * kvm_pmu_get_counter_value - get PMU counter value
> + * @vcpu: The vcpu pointer
> + * @select_idx: The counter index
> + */
> +u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
> +{
> + u64 counter, reg, enabled, running;
> + struct kvm_pmu *pmu = &vcpu->arch.pmu;
> + struct kvm_pmc *pmc = &pmu->pmc[select_idx];
> +
> + reg = (select_idx == ARMV8_CYCLE_IDX)
> + ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx;
reg = select_idx == 0 ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + select_idx - 1;
> + counter = vcpu_sys_reg(vcpu, reg);
> +
> + /* The real counter value is equal to the value of counter register plus
> + * the value perf event counts.
> + */
> + if (pmc->perf_event)
> + counter += perf_event_read_value(pmc->perf_event, &enabled,
> + &running);
> +
> + return counter & pmc->bitmask;
> +}
> +
> +/**
> + * kvm_pmu_stop_counter - stop PMU counter
> + * @pmc: The PMU counter pointer
> + *
> + * If this counter has been configured to monitor some event, release it here.
> + */
> +static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
> +{
> + u64 counter, reg;
> +
> + if (pmc->perf_event) {
> + counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
> + reg = (pmc->idx == ARMV8_CYCLE_IDX)
> + ? PMCCNTR_EL0 : PMEVCNTR0_EL0 + pmc->idx;
Second need for this reg selection. We should probably create an idx to
reg function.
> + vcpu_sys_reg(vcpu, reg) = counter;
> + perf_event_disable(pmc->perf_event);
> + perf_event_release_kernel(pmc->perf_event);
> + pmc->perf_event = NULL;
> + }
> +}
> +
> +static bool kvm_pmu_counter_is_enabled(struct kvm_vcpu *vcpu, u64 select_idx)
> +{
> + return (vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E) &&
> + (vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx));
> +}
> +
> +/**
> + * kvm_pmu_set_counter_event_type - set selected counter to monitor some event
> + * @vcpu: The vcpu pointer
> + * @data: The data guest writes to PMXEVTYPER_EL0
> + * @select_idx: The number of selected counter
> + *
> + * When OS accesses PMXEVTYPER_EL0, that means it wants to set a PMC to count an
> + * event with given hardware event number. Here we call perf_event API to
> + * emulate this action and create a kernel perf event for it.
> + */
> +void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
> + u64 select_idx)
> +{
> + struct kvm_pmu *pmu = &vcpu->arch.pmu;
> + struct kvm_pmc *pmc = &pmu->pmc[select_idx];
> + struct perf_event *event;
> + struct perf_event_attr attr;
> + u64 eventsel, counter;
> +
> + kvm_pmu_stop_counter(vcpu, pmc);
> + eventsel = data & ARMV8_EVTYPE_EVENT;
> +
> + memset(&attr, 0, sizeof(struct perf_event_attr));
> + attr.type = PERF_TYPE_RAW;
> + attr.size = sizeof(attr);
nit: the memset sizeof could also just use attr to save characters.
Or why not avoid the memset using struct perf_event_attr attr = {...},
like arch/x86/kvm/pmu.c does?
> + attr.pinned = 1;
> + attr.disabled = kvm_pmu_counter_is_enabled(vcpu, select_idx);
hmm.. disabled = enabled ? If we always want it off at set time, then it
should just be '= 1', right?
> + attr.exclude_user = data & ARMV8_EXCLUDE_EL0 ? 1 : 0;
> + attr.exclude_kernel = data & ARMV8_EXCLUDE_EL1 ? 1 : 0;
> + attr.exclude_hv = 1; /* Don't count EL2 events */
> + attr.exclude_host = 1; /* Don't count host events */
> + attr.config = eventsel;
> +
> + counter = kvm_pmu_get_counter_value(vcpu, select_idx);
> + /* The initial sample period (overflow count) of an event. */
> + attr.sample_period = (-counter) & pmc->bitmask;
> +
> + event = perf_event_create_kernel_counter(&attr, -1, current, NULL, pmc);
> + if (IS_ERR(event)) {
> + pr_err_once("kvm: pmu event creation failed %ld\n",
> + PTR_ERR(event));
> + return;
> + }
> +
> + pmc->perf_event = event;
> +}
> --
> 2.0.4
>
>
next prev parent reply other threads:[~2016-01-28 16:31 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-27 3:51 [PATCH v10 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2016-02-10 10:36 ` Will Deacon
2016-01-27 3:51 ` [PATCH v10 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-01-28 15:36 ` Andrew Jones
2016-01-28 20:43 ` Andrew Jones
2016-01-29 2:07 ` Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-01-28 20:10 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-01-28 20:34 ` Andrew Jones
2016-01-29 3:47 ` Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-01-28 16:31 ` Andrew Jones [this message]
2016-01-28 16:45 ` Marc Zyngier
2016-01-28 18:06 ` Will Deacon
2016-01-29 6:14 ` Shannon Zhao
2016-01-29 6:26 ` Shannon Zhao
2016-01-29 10:18 ` Will Deacon
2016-01-29 13:11 ` Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-01-28 20:11 ` Andrew Jones
2016-01-29 1:42 ` Shannon Zhao
2016-01-29 11:25 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-01-28 18:08 ` Andrew Jones
2016-01-28 18:12 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-01-28 18:18 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-01-28 18:37 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-01-28 19:15 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-01-28 19:58 ` Andrew Jones
2016-01-29 7:37 ` Shannon Zhao
2016-01-29 11:08 ` Andrew Jones
2016-01-29 13:17 ` Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-01-28 20:54 ` Andrew Jones
2016-01-27 3:51 ` [PATCH v10 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-01-27 3:51 ` [PATCH v10 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-01-28 21:12 ` Andrew Jones
2016-01-28 21:30 ` [PATCH v10 00/21] KVM: ARM64: Add guest PMU support Andrew Jones
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