[PATCH v3 0/5] pinctrl: sunxi: Add H3 R_PIO controller support

[PATCH v3 0/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Krzysztof Adamski]

This patch series is extension of my original single patch with the same
subject. It adds support for R_PIO so that GPIO port L can be used in H3
based devices. It was tested on OrangePi PC where PL is connected amount
others to an onboard led, a switch, an IR receiver and some VCC
controllers.

Patchset is based on next-20160129.

--- 

Changes since v2:
- fixed apb0 parrent clocks list
- moved binding documentation change to the proper patch
- simplified sunxi_pinctrl_gpio_get according to ChenYu suggestions
- fixed ordering in sunxi binding documentation

Changes since v1:
- splited patch to two separate - dtsi and c files
- added APB0 clocks a parent for R_PIO
- added fix in sunxi_pinctrl_gpio_get for getting pin value when in irq
  mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt


Krzysztof Adamski (5):
  clk: sunxi: Add apb0 gates for H3
  dts: sun8i-h3: Add APB0 related clocks and resets
  pinctrl: sunxi: Add H3 R_PIO controller support
  ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
  pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

 Documentation/devicetree/bindings/clock/sunxi.txt  |   1 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  36 +++++++
 drivers/clk/sunxi/clk-simple-gates.c               |   2 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c         | 106 +++++++++++++++++++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.c              |   5 +-
 8 files changed, 154 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c

-- 
2.1.4

[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Krzysztof Adamski]

This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..751c8b9f0 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -45,6 +45,7 @@ Required properties:
 	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
 	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
 	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
+	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
 	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
 	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
 	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index f4da52b..6753c87 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
 	       sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
+	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
-- 
2.1.4

[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Jean-Francois Moine]

On Thu,  4 Feb 2016 00:33:46 +0100
Krzysztof Adamski <k@japko.eu> wrote:

> This patch adds support for APB0 in H3. It seems to be compatible with
> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> etc).
> 
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..751c8b9f0 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -45,6 +45,7 @@ Required properties:
>  	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
>  	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
>  	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
> +	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
>  	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
>  	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
>  	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> index f4da52b..6753c87 100644
> --- a/drivers/clk/sunxi/clk-simple-gates.c
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
>  	       sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
>  	       sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
> +	       sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
>  	       sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",

It seems that the other compatible strings are there for historical
reasons. Why do you need a new one with such a specific name?

It would have been more sensible to add a generic compatible string as
"allwinner,apb-gates", letting the removal of the other strings for a
later patch...

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Krzysztof Adamski]

On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
>On Thu,  4 Feb 2016 00:33:46 +0100
>Krzysztof Adamski <k@japko.eu> wrote:
>
>> This patch adds support for APB0 in H3. It seems to be compatible with
>> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
>> etc).
>>
>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>>  2 files changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index e59f57b..751c8b9f0 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -45,6 +45,7 @@ Required properties:
>>  	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
>>  	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
>>  	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
>> +	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
>>  	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
>>  	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
>>  	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
>> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> index f4da52b..6753c87 100644
>> --- a/drivers/clk/sunxi/clk-simple-gates.c
>> +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
>>  	       sunxi_simple_gates_init);
>>  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
>>  	       sunxi_simple_gates_init);
>> +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
>> +	       sunxi_simple_gates_init);
>>  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
>>  	       sunxi_simple_gates_init);
>>  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
>
>It seems that the other compatible strings are there for historical
>reasons. Why do you need a new one with such a specific name?
>
>It would have been more sensible to add a generic compatible string as
>"allwinner,apb-gates", letting the removal of the other strings for a
>later patch...

Seems like a good idea but is it possible to remove those binding in 
separate patch? I mean, wouldn't that, in theory, break ABI? Are such 
patches accepted?

[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Maxime Ripard]

Hi,

On Thu, Feb 04, 2016 at 09:56:02PM +0100, Krzysztof Adamski wrote:
> On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
> >On Thu,  4 Feb 2016 00:33:46 +0100
> >Krzysztof Adamski <k@japko.eu> wrote:
> >
> >>This patch adds support for APB0 in H3. It seems to be compatible with
> >>earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> >>etc).
> >>
> >>Signed-off-by: Krzysztof Adamski <k@japko.eu>
> >>---
> >> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> >> drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
> >> 2 files changed, 3 insertions(+)
> >>
> >>diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> >>index e59f57b..751c8b9f0 100644
> >>--- a/Documentation/devicetree/bindings/clock/sunxi.txt
> >>+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> >>@@ -45,6 +45,7 @@ Required properties:
> >> 	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
> >> 	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
> >> 	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
> >>+	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
> >> 	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
> >> 	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
> >> 	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
> >>diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> >>index f4da52b..6753c87 100644
> >>--- a/drivers/clk/sunxi/clk-simple-gates.c
> >>+++ b/drivers/clk/sunxi/clk-simple-gates.c
> >>@@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
> >> 	       sunxi_simple_gates_init);
> >> CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
> >> 	       sunxi_simple_gates_init);
> >>+CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
> >>+	       sunxi_simple_gates_init);
> >> CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
> >> 	       sunxi_simple_gates_init);
> >> CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> >
> >It seems that the other compatible strings are there for historical
> >reasons. Why do you need a new one with such a specific name?
> >
> >It would have been more sensible to add a generic compatible string as
> >"allwinner,apb-gates", letting the removal of the other strings for a
> >later patch...
> 
> Seems like a good idea but is it possible to remove those binding in
> separate patch?

Yeah, you can (and should) do that as a separate patch, that can be
part of the next iteration of this set.

> I mean, wouldn't that, in theory, break ABI? Are such
> patches accepted?

It would, but it doesn't matter.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Maxime Ripard]

Hi,

On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
> On Thu,  4 Feb 2016 00:33:46 +0100
> Krzysztof Adamski <k@japko.eu> wrote:
> 
> > This patch adds support for APB0 in H3. It seems to be compatible with
> > earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> > etc).
> > 
> > Signed-off-by: Krzysztof Adamski <k@japko.eu>
> > ---
> >  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> >  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
> >  2 files changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> > index e59f57b..751c8b9f0 100644
> > --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> > @@ -45,6 +45,7 @@ Required properties:
> >  	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
> >  	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
> >  	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
> > +	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
> >  	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
> >  	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
> >  	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
> > diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> > index f4da52b..6753c87 100644
> > --- a/drivers/clk/sunxi/clk-simple-gates.c
> > +++ b/drivers/clk/sunxi/clk-simple-gates.c
> > @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
> >  	       sunxi_simple_gates_init);
> >  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
> >  	       sunxi_simple_gates_init);
> > +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
> > +	       sunxi_simple_gates_init);
> >  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
> >  	       sunxi_simple_gates_init);
> >  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> 
> It seems that the other compatible strings are there for historical
> reasons. Why do you need a new one with such a specific name?
> 
> It would have been more sensible to add a generic compatible string as
> "allwinner,apb-gates", letting the removal of the other strings for a
> later patch...

Yeah, it's a good idea, and it's probably time that we move to that.

However, I'd like to keep per-soc and per-clocks compatibles in the
DT, in case we need to protect a clock in the future. That doesn't
prevent to have two compatibles thoughe, the specific and the generic.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Krzysztof Adamski]

On Fri, Feb 05, 2016 at 12:11:52PM +0100, Maxime Ripard wrote:
>Hi,
>
>On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
>> On Thu,  4 Feb 2016 00:33:46 +0100
>> Krzysztof Adamski <k@japko.eu> wrote:
>>
>> > This patch adds support for APB0 in H3. It seems to be compatible with
>> > earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
>> > etc).
>> >
>> > Signed-off-by: Krzysztof Adamski <k@japko.eu>
>> > ---
>> >  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> >  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>> >  2 files changed, 3 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> > index e59f57b..751c8b9f0 100644
>> > --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> > +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> > @@ -45,6 +45,7 @@ Required properties:
>> >  	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
>> >  	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
>> >  	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
>> > +	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
>> >  	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
>> >  	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
>> >  	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
>> > diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> > index f4da52b..6753c87 100644
>> > --- a/drivers/clk/sunxi/clk-simple-gates.c
>> > +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> > @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
>> >  	       sunxi_simple_gates_init);
>> >  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
>> >  	       sunxi_simple_gates_init);
>> > +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
>> > +	       sunxi_simple_gates_init);
>> >  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
>> >  	       sunxi_simple_gates_init);
>> >  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
>>
>> It seems that the other compatible strings are there for historical
>> reasons. Why do you need a new one with such a specific name?
>>
>> It would have been more sensible to add a generic compatible string as
>> "allwinner,apb-gates", letting the removal of the other strings for a
>> later patch...
>
>Yeah, it's a good idea, and it's probably time that we move to that.
>
>However, I'd like to keep per-soc and per-clocks compatibles in the
>DT, in case we need to protect a clock in the future. That doesn't
>prevent to have two compatibles thoughe, the specific and the generic.
>

So now I'm not sure what you mean. You suggest that I should keep using 
specific (sun8i_h3_apb0) or change to generic (apb-gates) in my patch? 

[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Maxime Ripard]

On Fri, Feb 05, 2016 at 12:58:37PM +0100, Krzysztof Adamski wrote:
> On Fri, Feb 05, 2016 at 12:11:52PM +0100, Maxime Ripard wrote:
> >Hi,
> >
> >On Thu, Feb 04, 2016 at 03:47:52PM +0100, Jean-Francois Moine wrote:
> >>On Thu,  4 Feb 2016 00:33:46 +0100
> >>Krzysztof Adamski <k@japko.eu> wrote:
> >>
> >>> This patch adds support for APB0 in H3. It seems to be compatible with
> >>> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> >>> etc).
> >>>
> >>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> >>> ---
> >>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> >>>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
> >>>  2 files changed, 3 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> >>> index e59f57b..751c8b9f0 100644
> >>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> >>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> >>> @@ -45,6 +45,7 @@ Required properties:
> >>>  	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
> >>>  	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
> >>>  	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
> >>> +	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
> >>>  	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
> >>>  	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
> >>>  	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
> >>> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> >>> index f4da52b..6753c87 100644
> >>> --- a/drivers/clk/sunxi/clk-simple-gates.c
> >>> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> >>> @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
> >>>  	       sunxi_simple_gates_init);
> >>>  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
> >>>  	       sunxi_simple_gates_init);
> >>> +CLK_OF_DECLARE(sun8i_h3_apb0, "allwinner,sun8i-h3-apb0-gates-clk",
> >>> +	       sunxi_simple_gates_init);
> >>>  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
> >>>  	       sunxi_simple_gates_init);
> >>>  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> >>
> >>It seems that the other compatible strings are there for historical
> >>reasons. Why do you need a new one with such a specific name?
> >>
> >>It would have been more sensible to add a generic compatible string as
> >>"allwinner,apb-gates", letting the removal of the other strings for a
> >>later patch...
> >
> >Yeah, it's a good idea, and it's probably time that we move to that.
> >
> >However, I'd like to keep per-soc and per-clocks compatibles in the
> >DT, in case we need to protect a clock in the future. That doesn't
> >prevent to have two compatibles thoughe, the specific and the generic.
> >
> 
> So now I'm not sure what you mean. You suggest that I should keep using
> specific (sun8i_h3_apb0) or change to generic (apb-gates) in my patch?

Both.

To have something like that:

compatible = "allwinner,sun8i-h3-apb0-gates-clk", "allwinner,sun4i-a10-gates-clk";

sun4i-a10-gates-clk being the generic compatible that we would use,
and we can always match against the h3 specific compatible if we need
to have a different behaviour.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[linux-sunxi] Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Krzysztof Adamski]

On Tue, Feb 09, 2016 at 06:10:40PM +0100, Maxime Ripard wrote:
>> >>It seems that the other compatible strings are there for historical
>> >>reasons. Why do you need a new one with such a specific name?
>> >>
>> >>It would have been more sensible to add a generic compatible string as
>> >>"allwinner,apb-gates", letting the removal of the other strings for a
>> >>later patch...
>> >
>> >Yeah, it's a good idea, and it's probably time that we move to that.
>> >
>> >However, I'd like to keep per-soc and per-clocks compatibles in the
>> >DT, in case we need to protect a clock in the future. That doesn't
>> >prevent to have two compatibles thoughe, the specific and the generic.
>> >
>>
>> So now I'm not sure what you mean. You suggest that I should keep using
>> specific (sun8i_h3_apb0) or change to generic (apb-gates) in my patch?
>
>Both.
>
>To have something like that:
>
>compatible = "allwinner,sun8i-h3-apb0-gates-clk", "allwinner,sun4i-a10-gates-clk";
>
>sun4i-a10-gates-clk being the generic compatible that we would use,
>and we can always match against the h3 specific compatible if we need
>to have a different behaviour.

This seems like a good idea to me but since this is new thing anyways 
(other sunxi SoCs don't do this right now) shouldn't we introduce other
more generic name for generic clock (like "allwinner,apb-gates" 
mentioned earlier, or maybe "allwinner,simple-apb-gates")?

Also, wouldn't this be cleaner if I use only specific compatible string 
right now and provide separate patch that adds generic compatible string 
to all current SoCs at once? The downside of this is that it's easier to 
get merge conflicts unless I wait for applying this patchset.

Best regards,
Krzysztof Adamski

[linux-sunxi] Re: [PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Maxime Ripard]

Hi,

On Wed, Feb 10, 2016 at 08:17:14AM +0100, Krzysztof Adamski wrote:
> On Tue, Feb 09, 2016 at 06:10:40PM +0100, Maxime Ripard wrote:
> >>>>It seems that the other compatible strings are there for historical
> >>>>reasons. Why do you need a new one with such a specific name?
> >>>>
> >>>>It would have been more sensible to add a generic compatible string as
> >>>>"allwinner,apb-gates", letting the removal of the other strings for a
> >>>>later patch...
> >>>
> >>>Yeah, it's a good idea, and it's probably time that we move to that.
> >>>
> >>>However, I'd like to keep per-soc and per-clocks compatibles in the
> >>>DT, in case we need to protect a clock in the future. That doesn't
> >>>prevent to have two compatibles thoughe, the specific and the generic.
> >>>
> >>
> >>So now I'm not sure what you mean. You suggest that I should keep using
> >>specific (sun8i_h3_apb0) or change to generic (apb-gates) in my patch?
> >
> >Both.
> >
> >To have something like that:
> >
> >compatible = "allwinner,sun8i-h3-apb0-gates-clk", "allwinner,sun4i-a10-gates-clk";
> >
> >sun4i-a10-gates-clk being the generic compatible that we would use,
> >and we can always match against the h3 specific compatible if we need
> >to have a different behaviour.
> 
> This seems like a good idea to me but since this is new thing anyways (other
> sunxi SoCs don't do this right now) shouldn't we introduce other
> more generic name for generic clock (like "allwinner,apb-gates" mentioned
> earlier, or maybe "allwinner,simple-apb-gates")?

This is not specific to the APB bus, and the earlier SoC that
introduced those kind of clocks was the A10, hence why I was
suggesting that compatible (since we generally try to use the SoC that
introduced that hardware block in the compatible name).

> Also, wouldn't this be cleaner if I use only specific compatible string
> right now and provide separate patch that adds generic compatible string to
> all current SoCs at once? The downside of this is that it's easier to get
> merge conflicts unless I wait for applying this patchset.

I'd prefer if you added the generic one and were using it in your
subsequent patches. We can always mass convert the existing drivers
later on.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Jean-Francois Moine]

On Fri, 5 Feb 2016 12:11:52 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:

> However, I'd like to keep per-soc and per-clocks compatibles in the
> DT, in case we need to protect a clock in the future.

What do you mean by "protect a clock"?

-- 
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/

[PATCH v3 1/5] clk: sunxi: Add apb0 gates for H3

[Maxime Ripard]

On Sat, Feb 06, 2016 at 11:26:05AM +0100, Jean-Francois Moine wrote:
> On Fri, 5 Feb 2016 12:11:52 +0100
> Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> 
> > However, I'd like to keep per-soc and per-clocks compatibles in the
> > DT, in case we need to protect a clock in the future.
> 
> What do you mean by "protect a clock"?

Prevent it from shutting down.

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 2/5] dts: sun8i-h3: Add APB0 related clocks and resets

[Krzysztof Adamski]

APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.

After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..bb37f52 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -276,6 +276,24 @@
 			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 			clock-output-names = "mbus";
 		};
+
+		apb0: apb0_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&osc24M>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk at 01f01428 {
+			compatible = "allwinner,sun8i-h3-apb0-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>, <1>;
+			clock-output-names = "apb0_pio", "apb0_ir";
+		};
 	};
 
 	soc {
@@ -493,5 +511,11 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		apb0_reset: reset at 01f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
 	};
 };
-- 
2.1.4

[PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Krzysztof Adamski]

H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c         | 106 +++++++++++++++++++++
 4 files changed, 112 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..3e56b16 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -21,6 +21,7 @@ Required properties:
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
+  "allwinner,sun8i-h3-r-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..75a26c9 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -55,6 +55,10 @@ config PINCTRL_SUN8I_H3
 	def_bool MACH_SUN8I
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_H3_R
+	def_bool MACH_SUN8I
+	select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN9I_A80
 	def_bool MACH_SUN9I
 	select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..a5d56f1 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
+obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)	+= pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
new file mode 100644
index 0000000..686ec21
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_twi"),         /* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_twi"),         /* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* MS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* CK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_pwm"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
+	.pins = sun8i_h3_r_pins,
+	.npins = ARRAY_SIZE(sun8i_h3_r_pins),
+	.irq_banks = 1,
+	.pin_base = PL_BASE,
+	.irq_read_needs_mux = true
+};
+
+static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev,
+				  &sun8i_h3_r_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun8i-h3-r-pinctrl", },
+	{}
+};
+
+static struct platform_driver sun8i_h3_r_pinctrl_driver = {
+	.probe	= sun8i_h3_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun8i-h3-r-pinctrl",
+		.of_match_table	= sun8i_h3_r_pinctrl_match,
+	},
+};
+builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
-- 
2.1.4

[PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Chen-Yu Tsai]

On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski <k@japko.eu> wrote:
> H3 has additional PIO controller similar to what we can find on A23.
> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Acked-by: Chen-Yu Tsai <wens@csie.org>

(resent as my mail setup failed to deliver)

[PATCH v3 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Maxime Ripard]

On Thu, Feb 04, 2016 at 12:33:48AM +0100, Krzysztof Adamski wrote:
> H3 has additional PIO controller similar to what we can find on A23.
> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
> 
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH v3 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi

[Krzysztof Adamski]

Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index bb37f52..f618a95 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -517,5 +517,17 @@
 			compatible = "allwinner,sun6i-a31-clock-reset";
 			#reset-cells = <1>;
 		};
+
+		r_pio: pinctrl at 01f02c00 {
+			compatible = "allwinner,sun8i-h3-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>;
+			resets = <&apb0_reset 0>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 	};
 };
-- 
2.1.4

[PATCH v3 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi

[Chen-Yu Tsai]

On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski <k@japko.eu> wrote:
> Add the corresponding device node for R_PIO on H3 to the dtsi. Support
> for the controller was added in earlier commit.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index bb37f52..f618a95 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -517,5 +517,17 @@
>                         compatible = "allwinner,sun6i-a31-clock-reset";
>                         #reset-cells = <1>;
>                 };
> +
> +               r_pio: pinctrl at 01f02c00 {
> +                       compatible = "allwinner,sun8i-h3-r-pinctrl";
> +                       reg = <0x01f02c00 0x400>;
> +                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&apb0_gates 0>;
> +                       resets = <&apb0_reset 0>;
> +                       gpio-controller;
> +                       #gpio-cells = <3>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;

This should be 3: bank number + pin number + flags.
The rest looks good.

(resent as my mail setup failed to deliver)

> +               };
>         };
>  };
> --
> 2.1.4
>

[PATCH v3 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi

[Krzysztof Adamski]

On Fri, Feb 05, 2016 at 05:46:32PM +0800, Chen-Yu Tsai wrote:
>On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski <k@japko.eu> wrote:
>> Add the corresponding device node for R_PIO on H3 to the dtsi. Support
>> for the controller was added in earlier commit.
>>
>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>> ---
>>  arch/arm/boot/dts/sun8i-h3.dtsi | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index bb37f52..f618a95 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -517,5 +517,17 @@
>>                         compatible = "allwinner,sun6i-a31-clock-reset";
>>                         #reset-cells = <1>;
>>                 };
>> +
>> +               r_pio: pinctrl at 01f02c00 {
>> +                       compatible = "allwinner,sun8i-h3-r-pinctrl";
>> +                       reg = <0x01f02c00 0x400>;
>> +                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&apb0_gates 0>;
>> +                       resets = <&apb0_reset 0>;
>> +                       gpio-controller;
>> +                       #gpio-cells = <3>;
>> +                       interrupt-controller;
>> +                       #interrupt-cells = <2>;
>
>This should be 3: bank number + pin number + flags.
>The rest looks good.

Nicly spotted. I took it from pio description in the same file. So 
there's a bug there too.

[PATCH v3 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Krzysztof Adamski]

sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert it to pin number so we won't get
negative value in sunxi_pmx_set.

This was only used on A10 so far, where there is only one GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 7a2465f..96f64a1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -459,15 +459,16 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 	u8 index = sunxi_data_offset(offset);
 	u32 set_mux = pctl->desc->irq_read_needs_mux &&
 			test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
+	u32 pin = offset + chip->base;
 	u32 val;
 
 	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
+		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
 
 	val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 
 	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
+		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 
 	return !!val;
 }
-- 
2.1.4

[PATCH v3 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Chen-Yu Tsai]

On Thu, Feb 4, 2016 at 7:33 AM, Krzysztof Adamski <k@japko.eu> wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
>
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Acked-by: Chen-Yu Tsai <wens@csie.org>

(resent as my mail setup failed to deliver)

[PATCH v3 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Maxime Ripard]

On Thu, Feb 04, 2016 at 12:33:50AM +0100, Krzysztof Adamski wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
> 
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
> 
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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