* [PATCH V3 2/4] mfd: mt6397: int_con and int_status may vary in location
2016-01-27 11:47 [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC John Crispin
@ 2016-01-27 11:47 ` John Crispin
2016-02-10 16:59 ` Lee Jones
2016-01-27 11:47 ` [PATCH V3 3/4] mfd: mt6397: add support for different Slave types John Crispin
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: John Crispin @ 2016-01-27 11:47 UTC (permalink / raw)
To: linux-arm-kernel
MT6323 has the INT_CON and INT_STATUS located at a different position.
Make the registers locations configurable.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mfd/mt6397-core.c | 27 +++++++++++++++++----------
include/linux/mfd/mt6397/core.h | 2 ++
2 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 1749c1c..75ad0fe 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struct irq_data *data)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
- regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
- regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
+ regmap_write(mt6397->regmap, mt6397->int_con[0],
+ mt6397->irq_masks_cur[0]);
+ regmap_write(mt6397->regmap, mt6397->int_con[1],
+ mt6397->irq_masks_cur[1]);
mutex_unlock(&mt6397->irqlock);
}
@@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int irq, void *data)
{
struct mt6397_chip *mt6397 = data;
- mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
- mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
+ mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
+ mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
return IRQ_HANDLED;
}
@@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397_chip *mt6397)
mutex_init(&mt6397->irqlock);
/* Mask all interrupt sources */
- regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
- regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
+ regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
+ regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
@@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct device *dev)
{
struct mt6397_chip *chip = dev_get_drvdata(dev);
- regmap_write(chip->regmap, MT6397_INT_CON0, chip->wake_mask[0]);
- regmap_write(chip->regmap, MT6397_INT_CON1, chip->wake_mask[1]);
+ regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
+ regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
enable_irq_wake(chip->irq);
@@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct device *dev)
{
struct mt6397_chip *chip = dev_get_drvdata(dev);
- regmap_write(chip->regmap, MT6397_INT_CON0, chip->irq_masks_cur[0]);
- regmap_write(chip->regmap, MT6397_INT_CON1, chip->irq_masks_cur[1]);
+ regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
+ regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
disable_irq_wake(chip->irq);
@@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_device *pdev)
return -ENOMEM;
mt6397->dev = &pdev->dev;
+ mt6397->int_con[0] = MT6397_INT_CON0;
+ mt6397->int_con[1] = MT6397_INT_CON1;
+ mt6397->int_status[0] = MT6397_INT_STATUS0;
+ mt6397->int_status[1] = MT6397_INT_STATUS1;
+
/*
* mt6397 MFD is child device of soc pmic wrapper.
* Regmap is set from its parent.
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
index 45b8e8a..d678f52 100644
--- a/include/linux/mfd/mt6397/core.h
+++ b/include/linux/mfd/mt6397/core.h
@@ -60,6 +60,8 @@ struct mt6397_chip {
u16 wake_mask[2];
u16 irq_masks_cur[2];
u16 irq_masks_cache[2];
+ u16 int_con[2];
+ u16 int_status[2];
};
#endif /* __MFD_MT6397_CORE_H__ */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH V3 2/4] mfd: mt6397: int_con and int_status may vary in location
2016-01-27 11:47 ` [PATCH V3 2/4] mfd: mt6397: int_con and int_status may vary in location John Crispin
@ 2016-02-10 16:59 ` Lee Jones
0 siblings, 0 replies; 10+ messages in thread
From: Lee Jones @ 2016-02-10 16:59 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 27 Jan 2016, John Crispin wrote:
> MT6323 has the INT_CON and INT_STATUS located at a different position.
> Make the registers locations configurable.
>
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> drivers/mfd/mt6397-core.c | 27 +++++++++++++++++----------
> include/linux/mfd/mt6397/core.h | 2 ++
> 2 files changed, 19 insertions(+), 10 deletions(-)
Applied, thanks.
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index 1749c1c..75ad0fe 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -69,8 +69,10 @@ static void mt6397_irq_sync_unlock(struct irq_data *data)
> {
> struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
>
> - regmap_write(mt6397->regmap, MT6397_INT_CON0, mt6397->irq_masks_cur[0]);
> - regmap_write(mt6397->regmap, MT6397_INT_CON1, mt6397->irq_masks_cur[1]);
> + regmap_write(mt6397->regmap, mt6397->int_con[0],
> + mt6397->irq_masks_cur[0]);
> + regmap_write(mt6397->regmap, mt6397->int_con[1],
> + mt6397->irq_masks_cur[1]);
>
> mutex_unlock(&mt6397->irqlock);
> }
> @@ -147,8 +149,8 @@ static irqreturn_t mt6397_irq_thread(int irq, void *data)
> {
> struct mt6397_chip *mt6397 = data;
>
> - mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS0, 0);
> - mt6397_irq_handle_reg(mt6397, MT6397_INT_STATUS1, 16);
> + mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
> + mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
>
> return IRQ_HANDLED;
> }
> @@ -177,8 +179,8 @@ static int mt6397_irq_init(struct mt6397_chip *mt6397)
> mutex_init(&mt6397->irqlock);
>
> /* Mask all interrupt sources */
> - regmap_write(mt6397->regmap, MT6397_INT_CON0, 0x0);
> - regmap_write(mt6397->regmap, MT6397_INT_CON1, 0x0);
> + regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
> + regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
>
> mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
> MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
> @@ -203,8 +205,8 @@ static int mt6397_irq_suspend(struct device *dev)
> {
> struct mt6397_chip *chip = dev_get_drvdata(dev);
>
> - regmap_write(chip->regmap, MT6397_INT_CON0, chip->wake_mask[0]);
> - regmap_write(chip->regmap, MT6397_INT_CON1, chip->wake_mask[1]);
> + regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
> + regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
>
> enable_irq_wake(chip->irq);
>
> @@ -215,8 +217,8 @@ static int mt6397_irq_resume(struct device *dev)
> {
> struct mt6397_chip *chip = dev_get_drvdata(dev);
>
> - regmap_write(chip->regmap, MT6397_INT_CON0, chip->irq_masks_cur[0]);
> - regmap_write(chip->regmap, MT6397_INT_CON1, chip->irq_masks_cur[1]);
> + regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
> + regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
>
> disable_irq_wake(chip->irq);
>
> @@ -237,6 +239,11 @@ static int mt6397_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> mt6397->dev = &pdev->dev;
> + mt6397->int_con[0] = MT6397_INT_CON0;
> + mt6397->int_con[1] = MT6397_INT_CON1;
> + mt6397->int_status[0] = MT6397_INT_STATUS0;
> + mt6397->int_status[1] = MT6397_INT_STATUS1;
> +
> /*
> * mt6397 MFD is child device of soc pmic wrapper.
> * Regmap is set from its parent.
> diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
> index 45b8e8a..d678f52 100644
> --- a/include/linux/mfd/mt6397/core.h
> +++ b/include/linux/mfd/mt6397/core.h
> @@ -60,6 +60,8 @@ struct mt6397_chip {
> u16 wake_mask[2];
> u16 irq_masks_cur[2];
> u16 irq_masks_cache[2];
> + u16 int_con[2];
> + u16 int_status[2];
> };
>
> #endif /* __MFD_MT6397_CORE_H__ */
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V3 3/4] mfd: mt6397: add support for different Slave types
2016-01-27 11:47 [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC John Crispin
2016-01-27 11:47 ` [PATCH V3 2/4] mfd: mt6397: int_con and int_status may vary in location John Crispin
@ 2016-01-27 11:47 ` John Crispin
2016-02-10 16:59 ` Lee Jones
2016-01-27 11:47 ` [PATCH V3 4/4] mfd: mt6397: add MT6323 support to MT6397 driver John Crispin
` (3 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: John Crispin @ 2016-01-27 11:47 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/mfd/mt6397-core.c | 58 ++++++++++++++++++++++++++++++++-------------
1 file changed, 41 insertions(+), 17 deletions(-)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 75ad0fe..aa91606 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -24,6 +24,9 @@
#define MT6397_RTC_BASE 0xe000
#define MT6397_RTC_SIZE 0x3e
+#define MT6391_CID_CODE 0x91
+#define MT6397_CID_CODE 0x97
+
static const struct resource mt6397_rtc_resources[] = {
{
.start = MT6397_RTC_BASE,
@@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
static int mt6397_probe(struct platform_device *pdev)
{
int ret;
- struct mt6397_chip *mt6397;
+ unsigned int id;
+ struct mt6397_chip *pmic;
- mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
- if (!mt6397)
+ pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
+ if (!pmic)
return -ENOMEM;
- mt6397->dev = &pdev->dev;
- mt6397->int_con[0] = MT6397_INT_CON0;
- mt6397->int_con[1] = MT6397_INT_CON1;
- mt6397->int_status[0] = MT6397_INT_STATUS0;
- mt6397->int_status[1] = MT6397_INT_STATUS1;
+ pmic->dev = &pdev->dev;
/*
* mt6397 MFD is child device of soc pmic wrapper.
* Regmap is set from its parent.
*/
- mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
- if (!mt6397->regmap)
+ pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!pmic->regmap)
return -ENODEV;
- platform_set_drvdata(pdev, mt6397);
+ platform_set_drvdata(pdev, pmic);
+
+ ret = regmap_read(pmic->regmap, MT6397_CID, &id);
+ if (ret) {
+ dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
+ goto fail_irq;
+ }
+
+ switch (id & 0xff) {
+ case MT6397_CID_CODE:
+ case MT6391_CID_CODE:
+ pmic->int_con[0] = MT6397_INT_CON0;
+ pmic->int_con[1] = MT6397_INT_CON1;
+ pmic->int_status[0] = MT6397_INT_STATUS0;
+ pmic->int_status[1] = MT6397_INT_STATUS1;
+ ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
+ ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
+ break;
+
+ default:
+ dev_err(&pdev->dev, "unsupported chip: %d\n", id);
+ ret = -ENODEV;
+ break;
+ }
- mt6397->irq = platform_get_irq(pdev, 0);
- if (mt6397->irq > 0) {
- ret = mt6397_irq_init(mt6397);
+ pmic->irq = platform_get_irq(pdev, 0);
+ if (pmic->irq > 0) {
+ ret = mt6397_irq_init(pmic);
if (ret)
return ret;
}
- ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
- ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
- if (ret)
+fail_irq:
+ if (ret) {
+ irq_domain_remove(pmic->irq_domain);
dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
+ }
return ret;
}
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH V3 3/4] mfd: mt6397: add support for different Slave types
2016-01-27 11:47 ` [PATCH V3 3/4] mfd: mt6397: add support for different Slave types John Crispin
@ 2016-02-10 16:59 ` Lee Jones
0 siblings, 0 replies; 10+ messages in thread
From: Lee Jones @ 2016-02-10 16:59 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 27 Jan 2016, John Crispin wrote:
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> drivers/mfd/mt6397-core.c | 58 ++++++++++++++++++++++++++++++++-------------
> 1 file changed, 41 insertions(+), 17 deletions(-)
Applied, thanks.
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index 75ad0fe..aa91606 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -24,6 +24,9 @@
> #define MT6397_RTC_BASE 0xe000
> #define MT6397_RTC_SIZE 0x3e
>
> +#define MT6391_CID_CODE 0x91
> +#define MT6397_CID_CODE 0x97
> +
> static const struct resource mt6397_rtc_resources[] = {
> {
> .start = MT6397_RTC_BASE,
> @@ -232,39 +235,60 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
> static int mt6397_probe(struct platform_device *pdev)
> {
> int ret;
> - struct mt6397_chip *mt6397;
> + unsigned int id;
> + struct mt6397_chip *pmic;
>
> - mt6397 = devm_kzalloc(&pdev->dev, sizeof(*mt6397), GFP_KERNEL);
> - if (!mt6397)
> + pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
> + if (!pmic)
> return -ENOMEM;
>
> - mt6397->dev = &pdev->dev;
> - mt6397->int_con[0] = MT6397_INT_CON0;
> - mt6397->int_con[1] = MT6397_INT_CON1;
> - mt6397->int_status[0] = MT6397_INT_STATUS0;
> - mt6397->int_status[1] = MT6397_INT_STATUS1;
> + pmic->dev = &pdev->dev;
>
> /*
> * mt6397 MFD is child device of soc pmic wrapper.
> * Regmap is set from its parent.
> */
> - mt6397->regmap = dev_get_regmap(pdev->dev.parent, NULL);
> - if (!mt6397->regmap)
> + pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
> + if (!pmic->regmap)
> return -ENODEV;
>
> - platform_set_drvdata(pdev, mt6397);
> + platform_set_drvdata(pdev, pmic);
> +
> + ret = regmap_read(pmic->regmap, MT6397_CID, &id);
> + if (ret) {
> + dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
> + goto fail_irq;
> + }
> +
> + switch (id & 0xff) {
> + case MT6397_CID_CODE:
> + case MT6391_CID_CODE:
> + pmic->int_con[0] = MT6397_INT_CON0;
> + pmic->int_con[1] = MT6397_INT_CON1;
> + pmic->int_status[0] = MT6397_INT_STATUS0;
> + pmic->int_status[1] = MT6397_INT_STATUS1;
> + ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
> + ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
> + break;
> +
> + default:
> + dev_err(&pdev->dev, "unsupported chip: %d\n", id);
> + ret = -ENODEV;
> + break;
> + }
>
> - mt6397->irq = platform_get_irq(pdev, 0);
> - if (mt6397->irq > 0) {
> - ret = mt6397_irq_init(mt6397);
> + pmic->irq = platform_get_irq(pdev, 0);
> + if (pmic->irq > 0) {
> + ret = mt6397_irq_init(pmic);
> if (ret)
> return ret;
> }
>
> - ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
> - ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
> - if (ret)
> +fail_irq:
> + if (ret) {
> + irq_domain_remove(pmic->irq_domain);
> dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
> + }
>
> return ret;
> }
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V3 4/4] mfd: mt6397: add MT6323 support to MT6397 driver
2016-01-27 11:47 [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC John Crispin
2016-01-27 11:47 ` [PATCH V3 2/4] mfd: mt6397: int_con and int_status may vary in location John Crispin
2016-01-27 11:47 ` [PATCH V3 3/4] mfd: mt6397: add support for different Slave types John Crispin
@ 2016-01-27 11:47 ` John Crispin
2016-02-10 16:59 ` Lee Jones
2016-02-01 15:41 ` [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC Rob Herring
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: John Crispin @ 2016-01-27 11:47 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: John Crispin <blogic@openwrt.org>
---
Changes in V3
* fix copyright date/author
* use short license text
* reanme the conetxt variable inside the probe function
drivers/mfd/mt6397-core.c | 20 ++
include/linux/mfd/mt6323/core.h | 36 +++
include/linux/mfd/mt6323/registers.h | 408 ++++++++++++++++++++++++++++++++++
3 files changed, 464 insertions(+)
create mode 100644 include/linux/mfd/mt6323/core.h
create mode 100644 include/linux/mfd/mt6323/registers.h
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index aa91606..8234cd3 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -19,11 +19,14 @@
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/mfd/mt6397/core.h>
+#include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6397/registers.h>
+#include <linux/mfd/mt6323/registers.h>
#define MT6397_RTC_BASE 0xe000
#define MT6397_RTC_SIZE 0x3e
+#define MT6323_CID_CODE 0x23
#define MT6391_CID_CODE 0x91
#define MT6397_CID_CODE 0x97
@@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_resources[] = {
},
};
+static const struct mfd_cell mt6323_devs[] = {
+ {
+ .name = "mt6323-regulator",
+ .of_compatible = "mediatek,mt6323-regulator"
+ },
+};
+
static const struct mfd_cell mt6397_devs[] = {
{
.name = "mt6397-rtc",
@@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_device *pdev)
}
switch (id & 0xff) {
+ case MT6323_CID_CODE:
+ pmic->int_con[0] = MT6323_INT_CON0;
+ pmic->int_con[1] = MT6323_INT_CON1;
+ pmic->int_status[0] = MT6323_INT_STATUS0;
+ pmic->int_status[1] = MT6323_INT_STATUS1;
+ ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
+ ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
+ break;
+
case MT6397_CID_CODE:
case MT6391_CID_CODE:
pmic->int_con[0] = MT6397_INT_CON0;
@@ -302,6 +321,7 @@ static int mt6397_remove(struct platform_device *pdev)
static const struct of_device_id mt6397_of_match[] = {
{ .compatible = "mediatek,mt6397" },
+ { .compatible = "mediatek,mt6323" },
{ }
};
MODULE_DEVICE_TABLE(of, mt6397_of_match);
diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
new file mode 100644
index 0000000..06d0ec3
--- /dev/null
+++ b/include/linux/mfd/mt6323/core.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFD_MT6323_CORE_H__
+#define __MFD_MT6323_CORE_H__
+
+enum MT6323_IRQ_STATUS_numbers {
+ MT6323_IRQ_STATUS_SPKL_AB = 0,
+ MT6323_IRQ_STATUS_SPKL,
+ MT6323_IRQ_STATUS_BAT_L,
+ MT6323_IRQ_STATUS_BAT_H,
+ MT6323_IRQ_STATUS_WATCHDOG,
+ MT6323_IRQ_STATUS_PWRKEY,
+ MT6323_IRQ_STATUS_THR_L,
+ MT6323_IRQ_STATUS_THR_H,
+ MT6323_IRQ_STATUS_VBATON_UNDET,
+ MT6323_IRQ_STATUS_BVALID_DET,
+ MT6323_IRQ_STATUS_CHRDET,
+ MT6323_IRQ_STATUS_OV,
+ MT6323_IRQ_STATUS_LDO = 16,
+ MT6323_IRQ_STATUS_FCHRKEY,
+ MT6323_IRQ_STATUS_ACCDET,
+ MT6323_IRQ_STATUS_AUDIO,
+ MT6323_IRQ_STATUS_RTC,
+ MT6323_IRQ_STATUS_VPROC,
+ MT6323_IRQ_STATUS_VSYS,
+ MT6323_IRQ_STATUS_VPA,
+ MT6323_IRQ_STATUS_NR,
+};
+
+#endif /* __MFD_MT6323_CORE_H__ */
diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
new file mode 100644
index 0000000..160f3c0
--- /dev/null
+++ b/include/linux/mfd/mt6323/registers.h
@@ -0,0 +1,408 @@
+/*
+ * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFD_MT6323_REGISTERS_H__
+#define __MFD_MT6323_REGISTERS_H__
+
+/* PMIC Registers */
+#define MT6323_CHR_CON0 0x0000
+#define MT6323_CHR_CON1 0x0002
+#define MT6323_CHR_CON2 0x0004
+#define MT6323_CHR_CON3 0x0006
+#define MT6323_CHR_CON4 0x0008
+#define MT6323_CHR_CON5 0x000A
+#define MT6323_CHR_CON6 0x000C
+#define MT6323_CHR_CON7 0x000E
+#define MT6323_CHR_CON8 0x0010
+#define MT6323_CHR_CON9 0x0012
+#define MT6323_CHR_CON10 0x0014
+#define MT6323_CHR_CON11 0x0016
+#define MT6323_CHR_CON12 0x0018
+#define MT6323_CHR_CON13 0x001A
+#define MT6323_CHR_CON14 0x001C
+#define MT6323_CHR_CON15 0x001E
+#define MT6323_CHR_CON16 0x0020
+#define MT6323_CHR_CON17 0x0022
+#define MT6323_CHR_CON18 0x0024
+#define MT6323_CHR_CON19 0x0026
+#define MT6323_CHR_CON20 0x0028
+#define MT6323_CHR_CON21 0x002A
+#define MT6323_CHR_CON22 0x002C
+#define MT6323_CHR_CON23 0x002E
+#define MT6323_CHR_CON24 0x0030
+#define MT6323_CHR_CON25 0x0032
+#define MT6323_CHR_CON26 0x0034
+#define MT6323_CHR_CON27 0x0036
+#define MT6323_CHR_CON28 0x0038
+#define MT6323_CHR_CON29 0x003A
+#define MT6323_STRUP_CON0 0x003C
+#define MT6323_STRUP_CON2 0x003E
+#define MT6323_STRUP_CON3 0x0040
+#define MT6323_STRUP_CON4 0x0042
+#define MT6323_STRUP_CON5 0x0044
+#define MT6323_STRUP_CON6 0x0046
+#define MT6323_STRUP_CON7 0x0048
+#define MT6323_STRUP_CON8 0x004A
+#define MT6323_STRUP_CON9 0x004C
+#define MT6323_STRUP_CON10 0x004E
+#define MT6323_STRUP_CON11 0x0050
+#define MT6323_SPK_CON0 0x0052
+#define MT6323_SPK_CON1 0x0054
+#define MT6323_SPK_CON2 0x0056
+#define MT6323_SPK_CON6 0x005E
+#define MT6323_SPK_CON7 0x0060
+#define MT6323_SPK_CON8 0x0062
+#define MT6323_SPK_CON9 0x0064
+#define MT6323_SPK_CON10 0x0066
+#define MT6323_SPK_CON11 0x0068
+#define MT6323_SPK_CON12 0x006A
+#define MT6323_CID 0x0100
+#define MT6323_TOP_CKPDN0 0x0102
+#define MT6323_TOP_CKPDN0_SET 0x0104
+#define MT6323_TOP_CKPDN0_CLR 0x0106
+#define MT6323_TOP_CKPDN1 0x0108
+#define MT6323_TOP_CKPDN1_SET 0x010A
+#define MT6323_TOP_CKPDN1_CLR 0x010C
+#define MT6323_TOP_CKPDN2 0x010E
+#define MT6323_TOP_CKPDN2_SET 0x0110
+#define MT6323_TOP_CKPDN2_CLR 0x0112
+#define MT6323_TOP_RST_CON 0x0114
+#define MT6323_TOP_RST_CON_SET 0x0116
+#define MT6323_TOP_RST_CON_CLR 0x0118
+#define MT6323_TOP_RST_MISC 0x011A
+#define MT6323_TOP_RST_MISC_SET 0x011C
+#define MT6323_TOP_RST_MISC_CLR 0x011E
+#define MT6323_TOP_CKCON0 0x0120
+#define MT6323_TOP_CKCON0_SET 0x0122
+#define MT6323_TOP_CKCON0_CLR 0x0124
+#define MT6323_TOP_CKCON1 0x0126
+#define MT6323_TOP_CKCON1_SET 0x0128
+#define MT6323_TOP_CKCON1_CLR 0x012A
+#define MT6323_TOP_CKTST0 0x012C
+#define MT6323_TOP_CKTST1 0x012E
+#define MT6323_TOP_CKTST2 0x0130
+#define MT6323_TEST_OUT 0x0132
+#define MT6323_TEST_CON0 0x0134
+#define MT6323_TEST_CON1 0x0136
+#define MT6323_EN_STATUS0 0x0138
+#define MT6323_EN_STATUS1 0x013A
+#define MT6323_OCSTATUS0 0x013C
+#define MT6323_OCSTATUS1 0x013E
+#define MT6323_PGSTATUS 0x0140
+#define MT6323_CHRSTATUS 0x0142
+#define MT6323_TDSEL_CON 0x0144
+#define MT6323_RDSEL_CON 0x0146
+#define MT6323_SMT_CON0 0x0148
+#define MT6323_SMT_CON1 0x014A
+#define MT6323_SMT_CON2 0x014C
+#define MT6323_SMT_CON3 0x014E
+#define MT6323_SMT_CON4 0x0150
+#define MT6323_DRV_CON0 0x0152
+#define MT6323_DRV_CON1 0x0154
+#define MT6323_DRV_CON2 0x0156
+#define MT6323_DRV_CON3 0x0158
+#define MT6323_DRV_CON4 0x015A
+#define MT6323_SIMLS1_CON 0x015C
+#define MT6323_SIMLS2_CON 0x015E
+#define MT6323_INT_CON0 0x0160
+#define MT6323_INT_CON0_SET 0x0162
+#define MT6323_INT_CON0_CLR 0x0164
+#define MT6323_INT_CON1 0x0166
+#define MT6323_INT_CON1_SET 0x0168
+#define MT6323_INT_CON1_CLR 0x016A
+#define MT6323_INT_MISC_CON 0x016C
+#define MT6323_INT_MISC_CON_SET 0x016E
+#define MT6323_INT_MISC_CON_CLR 0x0170
+#define MT6323_INT_STATUS0 0x0172
+#define MT6323_INT_STATUS1 0x0174
+#define MT6323_OC_GEAR_0 0x0176
+#define MT6323_OC_GEAR_1 0x0178
+#define MT6323_OC_GEAR_2 0x017A
+#define MT6323_OC_CTL_VPROC 0x017C
+#define MT6323_OC_CTL_VSYS 0x017E
+#define MT6323_OC_CTL_VPA 0x0180
+#define MT6323_FQMTR_CON0 0x0182
+#define MT6323_FQMTR_CON1 0x0184
+#define MT6323_FQMTR_CON2 0x0186
+#define MT6323_RG_SPI_CON 0x0188
+#define MT6323_DEW_DIO_EN 0x018A
+#define MT6323_DEW_READ_TEST 0x018C
+#define MT6323_DEW_WRITE_TEST 0x018E
+#define MT6323_DEW_CRC_SWRST 0x0190
+#define MT6323_DEW_CRC_EN 0x0192
+#define MT6323_DEW_CRC_VAL 0x0194
+#define MT6323_DEW_DBG_MON_SEL 0x0196
+#define MT6323_DEW_CIPHER_KEY_SEL 0x0198
+#define MT6323_DEW_CIPHER_IV_SEL 0x019A
+#define MT6323_DEW_CIPHER_EN 0x019C
+#define MT6323_DEW_CIPHER_RDY 0x019E
+#define MT6323_DEW_CIPHER_MODE 0x01A0
+#define MT6323_DEW_CIPHER_SWRST 0x01A2
+#define MT6323_DEW_RDDMY_NO 0x01A4
+#define MT6323_DEW_RDATA_DLY_SEL 0x01A6
+#define MT6323_BUCK_CON0 0x0200
+#define MT6323_BUCK_CON1 0x0202
+#define MT6323_BUCK_CON2 0x0204
+#define MT6323_BUCK_CON3 0x0206
+#define MT6323_BUCK_CON4 0x0208
+#define MT6323_BUCK_CON5 0x020A
+#define MT6323_VPROC_CON0 0x020C
+#define MT6323_VPROC_CON1 0x020E
+#define MT6323_VPROC_CON2 0x0210
+#define MT6323_VPROC_CON3 0x0212
+#define MT6323_VPROC_CON4 0x0214
+#define MT6323_VPROC_CON5 0x0216
+#define MT6323_VPROC_CON7 0x021A
+#define MT6323_VPROC_CON8 0x021C
+#define MT6323_VPROC_CON9 0x021E
+#define MT6323_VPROC_CON10 0x0220
+#define MT6323_VPROC_CON11 0x0222
+#define MT6323_VPROC_CON12 0x0224
+#define MT6323_VPROC_CON13 0x0226
+#define MT6323_VPROC_CON14 0x0228
+#define MT6323_VPROC_CON15 0x022A
+#define MT6323_VPROC_CON18 0x0230
+#define MT6323_VSYS_CON0 0x0232
+#define MT6323_VSYS_CON1 0x0234
+#define MT6323_VSYS_CON2 0x0236
+#define MT6323_VSYS_CON3 0x0238
+#define MT6323_VSYS_CON4 0x023A
+#define MT6323_VSYS_CON5 0x023C
+#define MT6323_VSYS_CON7 0x0240
+#define MT6323_VSYS_CON8 0x0242
+#define MT6323_VSYS_CON9 0x0244
+#define MT6323_VSYS_CON10 0x0246
+#define MT6323_VSYS_CON11 0x0248
+#define MT6323_VSYS_CON12 0x024A
+#define MT6323_VSYS_CON13 0x024C
+#define MT6323_VSYS_CON14 0x024E
+#define MT6323_VSYS_CON15 0x0250
+#define MT6323_VSYS_CON18 0x0256
+#define MT6323_VPA_CON0 0x0300
+#define MT6323_VPA_CON1 0x0302
+#define MT6323_VPA_CON2 0x0304
+#define MT6323_VPA_CON3 0x0306
+#define MT6323_VPA_CON4 0x0308
+#define MT6323_VPA_CON5 0x030A
+#define MT6323_VPA_CON7 0x030E
+#define MT6323_VPA_CON8 0x0310
+#define MT6323_VPA_CON9 0x0312
+#define MT6323_VPA_CON10 0x0314
+#define MT6323_VPA_CON11 0x0316
+#define MT6323_VPA_CON12 0x0318
+#define MT6323_VPA_CON14 0x031C
+#define MT6323_VPA_CON16 0x0320
+#define MT6323_VPA_CON17 0x0322
+#define MT6323_VPA_CON18 0x0324
+#define MT6323_VPA_CON19 0x0326
+#define MT6323_VPA_CON20 0x0328
+#define MT6323_BUCK_K_CON0 0x032A
+#define MT6323_BUCK_K_CON1 0x032C
+#define MT6323_BUCK_K_CON2 0x032E
+#define MT6323_ISINK0_CON0 0x0330
+#define MT6323_ISINK0_CON1 0x0332
+#define MT6323_ISINK0_CON2 0x0334
+#define MT6323_ISINK0_CON3 0x0336
+#define MT6323_ISINK1_CON0 0x0338
+#define MT6323_ISINK1_CON1 0x033A
+#define MT6323_ISINK1_CON2 0x033C
+#define MT6323_ISINK1_CON3 0x033E
+#define MT6323_ISINK2_CON0 0x0340
+#define MT6323_ISINK2_CON1 0x0342
+#define MT6323_ISINK2_CON2 0x0344
+#define MT6323_ISINK2_CON3 0x0346
+#define MT6323_ISINK3_CON0 0x0348
+#define MT6323_ISINK3_CON1 0x034A
+#define MT6323_ISINK3_CON2 0x034C
+#define MT6323_ISINK3_CON3 0x034E
+#define MT6323_ISINK_ANA0 0x0350
+#define MT6323_ISINK_ANA1 0x0352
+#define MT6323_ISINK_PHASE_DLY 0x0354
+#define MT6323_ISINK_EN_CTRL 0x0356
+#define MT6323_ANALDO_CON0 0x0400
+#define MT6323_ANALDO_CON1 0x0402
+#define MT6323_ANALDO_CON2 0x0404
+#define MT6323_ANALDO_CON3 0x0406
+#define MT6323_ANALDO_CON4 0x0408
+#define MT6323_ANALDO_CON5 0x040A
+#define MT6323_ANALDO_CON6 0x040C
+#define MT6323_ANALDO_CON7 0x040E
+#define MT6323_ANALDO_CON8 0x0410
+#define MT6323_ANALDO_CON10 0x0412
+#define MT6323_ANALDO_CON15 0x0414
+#define MT6323_ANALDO_CON16 0x0416
+#define MT6323_ANALDO_CON17 0x0418
+#define MT6323_ANALDO_CON18 0x041A
+#define MT6323_ANALDO_CON19 0x041C
+#define MT6323_ANALDO_CON20 0x041E
+#define MT6323_ANALDO_CON21 0x0420
+#define MT6323_DIGLDO_CON0 0x0500
+#define MT6323_DIGLDO_CON2 0x0502
+#define MT6323_DIGLDO_CON3 0x0504
+#define MT6323_DIGLDO_CON5 0x0506
+#define MT6323_DIGLDO_CON6 0x0508
+#define MT6323_DIGLDO_CON7 0x050A
+#define MT6323_DIGLDO_CON8 0x050C
+#define MT6323_DIGLDO_CON9 0x050E
+#define MT6323_DIGLDO_CON10 0x0510
+#define MT6323_DIGLDO_CON11 0x0512
+#define MT6323_DIGLDO_CON12 0x0514
+#define MT6323_DIGLDO_CON13 0x0516
+#define MT6323_DIGLDO_CON14 0x0518
+#define MT6323_DIGLDO_CON15 0x051A
+#define MT6323_DIGLDO_CON16 0x051C
+#define MT6323_DIGLDO_CON17 0x051E
+#define MT6323_DIGLDO_CON18 0x0520
+#define MT6323_DIGLDO_CON19 0x0522
+#define MT6323_DIGLDO_CON20 0x0524
+#define MT6323_DIGLDO_CON21 0x0526
+#define MT6323_DIGLDO_CON23 0x0528
+#define MT6323_DIGLDO_CON24 0x052A
+#define MT6323_DIGLDO_CON26 0x052C
+#define MT6323_DIGLDO_CON27 0x052E
+#define MT6323_DIGLDO_CON28 0x0530
+#define MT6323_DIGLDO_CON29 0x0532
+#define MT6323_DIGLDO_CON30 0x0534
+#define MT6323_DIGLDO_CON31 0x0536
+#define MT6323_DIGLDO_CON32 0x0538
+#define MT6323_DIGLDO_CON33 0x053A
+#define MT6323_DIGLDO_CON34 0x053C
+#define MT6323_DIGLDO_CON35 0x053E
+#define MT6323_DIGLDO_CON36 0x0540
+#define MT6323_DIGLDO_CON39 0x0542
+#define MT6323_DIGLDO_CON40 0x0544
+#define MT6323_DIGLDO_CON41 0x0546
+#define MT6323_DIGLDO_CON42 0x0548
+#define MT6323_DIGLDO_CON43 0x054A
+#define MT6323_DIGLDO_CON44 0x054C
+#define MT6323_DIGLDO_CON45 0x054E
+#define MT6323_DIGLDO_CON46 0x0550
+#define MT6323_DIGLDO_CON47 0x0552
+#define MT6323_DIGLDO_CON48 0x0554
+#define MT6323_DIGLDO_CON49 0x0556
+#define MT6323_DIGLDO_CON50 0x0558
+#define MT6323_DIGLDO_CON51 0x055A
+#define MT6323_DIGLDO_CON52 0x055C
+#define MT6323_DIGLDO_CON53 0x055E
+#define MT6323_DIGLDO_CON54 0x0560
+#define MT6323_EFUSE_CON0 0x0600
+#define MT6323_EFUSE_CON1 0x0602
+#define MT6323_EFUSE_CON2 0x0604
+#define MT6323_EFUSE_CON3 0x0606
+#define MT6323_EFUSE_CON4 0x0608
+#define MT6323_EFUSE_CON5 0x060A
+#define MT6323_EFUSE_CON6 0x060C
+#define MT6323_EFUSE_VAL_0_15 0x060E
+#define MT6323_EFUSE_VAL_16_31 0x0610
+#define MT6323_EFUSE_VAL_32_47 0x0612
+#define MT6323_EFUSE_VAL_48_63 0x0614
+#define MT6323_EFUSE_VAL_64_79 0x0616
+#define MT6323_EFUSE_VAL_80_95 0x0618
+#define MT6323_EFUSE_VAL_96_111 0x061A
+#define MT6323_EFUSE_VAL_112_127 0x061C
+#define MT6323_EFUSE_VAL_128_143 0x061E
+#define MT6323_EFUSE_VAL_144_159 0x0620
+#define MT6323_EFUSE_VAL_160_175 0x0622
+#define MT6323_EFUSE_VAL_176_191 0x0624
+#define MT6323_EFUSE_DOUT_0_15 0x0626
+#define MT6323_EFUSE_DOUT_16_31 0x0628
+#define MT6323_EFUSE_DOUT_32_47 0x062A
+#define MT6323_EFUSE_DOUT_48_63 0x062C
+#define MT6323_EFUSE_DOUT_64_79 0x062E
+#define MT6323_EFUSE_DOUT_80_95 0x0630
+#define MT6323_EFUSE_DOUT_96_111 0x0632
+#define MT6323_EFUSE_DOUT_112_127 0x0634
+#define MT6323_EFUSE_DOUT_128_143 0x0636
+#define MT6323_EFUSE_DOUT_144_159 0x0638
+#define MT6323_EFUSE_DOUT_160_175 0x063A
+#define MT6323_EFUSE_DOUT_176_191 0x063C
+#define MT6323_EFUSE_CON7 0x063E
+#define MT6323_EFUSE_CON8 0x0640
+#define MT6323_EFUSE_CON9 0x0642
+#define MT6323_RTC_MIX_CON0 0x0644
+#define MT6323_RTC_MIX_CON1 0x0646
+#define MT6323_AUDTOP_CON0 0x0700
+#define MT6323_AUDTOP_CON1 0x0702
+#define MT6323_AUDTOP_CON2 0x0704
+#define MT6323_AUDTOP_CON3 0x0706
+#define MT6323_AUDTOP_CON4 0x0708
+#define MT6323_AUDTOP_CON5 0x070A
+#define MT6323_AUDTOP_CON6 0x070C
+#define MT6323_AUDTOP_CON7 0x070E
+#define MT6323_AUDTOP_CON8 0x0710
+#define MT6323_AUDTOP_CON9 0x0712
+#define MT6323_AUXADC_ADC0 0x0714
+#define MT6323_AUXADC_ADC1 0x0716
+#define MT6323_AUXADC_ADC2 0x0718
+#define MT6323_AUXADC_ADC3 0x071A
+#define MT6323_AUXADC_ADC4 0x071C
+#define MT6323_AUXADC_ADC5 0x071E
+#define MT6323_AUXADC_ADC6 0x0720
+#define MT6323_AUXADC_ADC7 0x0722
+#define MT6323_AUXADC_ADC8 0x0724
+#define MT6323_AUXADC_ADC9 0x0726
+#define MT6323_AUXADC_ADC10 0x0728
+#define MT6323_AUXADC_ADC11 0x072A
+#define MT6323_AUXADC_ADC12 0x072C
+#define MT6323_AUXADC_ADC13 0x072E
+#define MT6323_AUXADC_ADC14 0x0730
+#define MT6323_AUXADC_ADC15 0x0732
+#define MT6323_AUXADC_ADC16 0x0734
+#define MT6323_AUXADC_ADC17 0x0736
+#define MT6323_AUXADC_ADC18 0x0738
+#define MT6323_AUXADC_ADC19 0x073A
+#define MT6323_AUXADC_ADC20 0x073C
+#define MT6323_AUXADC_RSV1 0x073E
+#define MT6323_AUXADC_RSV2 0x0740
+#define MT6323_AUXADC_CON0 0x0742
+#define MT6323_AUXADC_CON1 0x0744
+#define MT6323_AUXADC_CON2 0x0746
+#define MT6323_AUXADC_CON3 0x0748
+#define MT6323_AUXADC_CON4 0x074A
+#define MT6323_AUXADC_CON5 0x074C
+#define MT6323_AUXADC_CON6 0x074E
+#define MT6323_AUXADC_CON7 0x0750
+#define MT6323_AUXADC_CON8 0x0752
+#define MT6323_AUXADC_CON9 0x0754
+#define MT6323_AUXADC_CON10 0x0756
+#define MT6323_AUXADC_CON11 0x0758
+#define MT6323_AUXADC_CON12 0x075A
+#define MT6323_AUXADC_CON13 0x075C
+#define MT6323_AUXADC_CON14 0x075E
+#define MT6323_AUXADC_CON15 0x0760
+#define MT6323_AUXADC_CON16 0x0762
+#define MT6323_AUXADC_CON17 0x0764
+#define MT6323_AUXADC_CON18 0x0766
+#define MT6323_AUXADC_CON19 0x0768
+#define MT6323_AUXADC_CON20 0x076A
+#define MT6323_AUXADC_CON21 0x076C
+#define MT6323_AUXADC_CON22 0x076E
+#define MT6323_AUXADC_CON23 0x0770
+#define MT6323_AUXADC_CON24 0x0772
+#define MT6323_AUXADC_CON25 0x0774
+#define MT6323_AUXADC_CON26 0x0776
+#define MT6323_AUXADC_CON27 0x0778
+#define MT6323_ACCDET_CON0 0x077A
+#define MT6323_ACCDET_CON1 0x077C
+#define MT6323_ACCDET_CON2 0x077E
+#define MT6323_ACCDET_CON3 0x0780
+#define MT6323_ACCDET_CON4 0x0782
+#define MT6323_ACCDET_CON5 0x0784
+#define MT6323_ACCDET_CON6 0x0786
+#define MT6323_ACCDET_CON7 0x0788
+#define MT6323_ACCDET_CON8 0x078A
+#define MT6323_ACCDET_CON9 0x078C
+#define MT6323_ACCDET_CON10 0x078E
+#define MT6323_ACCDET_CON11 0x0790
+#define MT6323_ACCDET_CON12 0x0792
+#define MT6323_ACCDET_CON13 0x0794
+#define MT6323_ACCDET_CON14 0x0796
+#define MT6323_ACCDET_CON15 0x0798
+#define MT6323_ACCDET_CON16 0x079A
+
+#endif /* __MFD_MT6323_REGISTERS_H__ */
--
1.7.10.4
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH V3 4/4] mfd: mt6397: add MT6323 support to MT6397 driver
2016-01-27 11:47 ` [PATCH V3 4/4] mfd: mt6397: add MT6323 support to MT6397 driver John Crispin
@ 2016-02-10 16:59 ` Lee Jones
0 siblings, 0 replies; 10+ messages in thread
From: Lee Jones @ 2016-02-10 16:59 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 27 Jan 2016, John Crispin wrote:
> Signed-off-by: John Crispin <blogic@openwrt.org>
> ---
> Changes in V3
> * fix copyright date/author
> * use short license text
> * reanme the conetxt variable inside the probe function
>
> drivers/mfd/mt6397-core.c | 20 ++
> include/linux/mfd/mt6323/core.h | 36 +++
> include/linux/mfd/mt6323/registers.h | 408 ++++++++++++++++++++++++++++++++++
> 3 files changed, 464 insertions(+)
> create mode 100644 include/linux/mfd/mt6323/core.h
> create mode 100644 include/linux/mfd/mt6323/registers.h
Applied, thanks.
> diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
> index aa91606..8234cd3 100644
> --- a/drivers/mfd/mt6397-core.c
> +++ b/drivers/mfd/mt6397-core.c
> @@ -19,11 +19,14 @@
> #include <linux/regmap.h>
> #include <linux/mfd/core.h>
> #include <linux/mfd/mt6397/core.h>
> +#include <linux/mfd/mt6323/core.h>
> #include <linux/mfd/mt6397/registers.h>
> +#include <linux/mfd/mt6323/registers.h>
>
> #define MT6397_RTC_BASE 0xe000
> #define MT6397_RTC_SIZE 0x3e
>
> +#define MT6323_CID_CODE 0x23
> #define MT6391_CID_CODE 0x91
> #define MT6397_CID_CODE 0x97
>
> @@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_resources[] = {
> },
> };
>
> +static const struct mfd_cell mt6323_devs[] = {
> + {
> + .name = "mt6323-regulator",
> + .of_compatible = "mediatek,mt6323-regulator"
> + },
> +};
> +
> static const struct mfd_cell mt6397_devs[] = {
> {
> .name = "mt6397-rtc",
> @@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_device *pdev)
> }
>
> switch (id & 0xff) {
> + case MT6323_CID_CODE:
> + pmic->int_con[0] = MT6323_INT_CON0;
> + pmic->int_con[1] = MT6323_INT_CON1;
> + pmic->int_status[0] = MT6323_INT_STATUS0;
> + pmic->int_status[1] = MT6323_INT_STATUS1;
> + ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
> + ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
> + break;
> +
> case MT6397_CID_CODE:
> case MT6391_CID_CODE:
> pmic->int_con[0] = MT6397_INT_CON0;
> @@ -302,6 +321,7 @@ static int mt6397_remove(struct platform_device *pdev)
>
> static const struct of_device_id mt6397_of_match[] = {
> { .compatible = "mediatek,mt6397" },
> + { .compatible = "mediatek,mt6323" },
> { }
> };
> MODULE_DEVICE_TABLE(of, mt6397_of_match);
> diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
> new file mode 100644
> index 0000000..06d0ec3
> --- /dev/null
> +++ b/include/linux/mfd/mt6323/core.h
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MFD_MT6323_CORE_H__
> +#define __MFD_MT6323_CORE_H__
> +
> +enum MT6323_IRQ_STATUS_numbers {
> + MT6323_IRQ_STATUS_SPKL_AB = 0,
> + MT6323_IRQ_STATUS_SPKL,
> + MT6323_IRQ_STATUS_BAT_L,
> + MT6323_IRQ_STATUS_BAT_H,
> + MT6323_IRQ_STATUS_WATCHDOG,
> + MT6323_IRQ_STATUS_PWRKEY,
> + MT6323_IRQ_STATUS_THR_L,
> + MT6323_IRQ_STATUS_THR_H,
> + MT6323_IRQ_STATUS_VBATON_UNDET,
> + MT6323_IRQ_STATUS_BVALID_DET,
> + MT6323_IRQ_STATUS_CHRDET,
> + MT6323_IRQ_STATUS_OV,
> + MT6323_IRQ_STATUS_LDO = 16,
> + MT6323_IRQ_STATUS_FCHRKEY,
> + MT6323_IRQ_STATUS_ACCDET,
> + MT6323_IRQ_STATUS_AUDIO,
> + MT6323_IRQ_STATUS_RTC,
> + MT6323_IRQ_STATUS_VPROC,
> + MT6323_IRQ_STATUS_VSYS,
> + MT6323_IRQ_STATUS_VPA,
> + MT6323_IRQ_STATUS_NR,
> +};
> +
> +#endif /* __MFD_MT6323_CORE_H__ */
> diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
> new file mode 100644
> index 0000000..160f3c0
> --- /dev/null
> +++ b/include/linux/mfd/mt6323/registers.h
> @@ -0,0 +1,408 @@
> +/*
> + * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MFD_MT6323_REGISTERS_H__
> +#define __MFD_MT6323_REGISTERS_H__
> +
> +/* PMIC Registers */
> +#define MT6323_CHR_CON0 0x0000
> +#define MT6323_CHR_CON1 0x0002
> +#define MT6323_CHR_CON2 0x0004
> +#define MT6323_CHR_CON3 0x0006
> +#define MT6323_CHR_CON4 0x0008
> +#define MT6323_CHR_CON5 0x000A
> +#define MT6323_CHR_CON6 0x000C
> +#define MT6323_CHR_CON7 0x000E
> +#define MT6323_CHR_CON8 0x0010
> +#define MT6323_CHR_CON9 0x0012
> +#define MT6323_CHR_CON10 0x0014
> +#define MT6323_CHR_CON11 0x0016
> +#define MT6323_CHR_CON12 0x0018
> +#define MT6323_CHR_CON13 0x001A
> +#define MT6323_CHR_CON14 0x001C
> +#define MT6323_CHR_CON15 0x001E
> +#define MT6323_CHR_CON16 0x0020
> +#define MT6323_CHR_CON17 0x0022
> +#define MT6323_CHR_CON18 0x0024
> +#define MT6323_CHR_CON19 0x0026
> +#define MT6323_CHR_CON20 0x0028
> +#define MT6323_CHR_CON21 0x002A
> +#define MT6323_CHR_CON22 0x002C
> +#define MT6323_CHR_CON23 0x002E
> +#define MT6323_CHR_CON24 0x0030
> +#define MT6323_CHR_CON25 0x0032
> +#define MT6323_CHR_CON26 0x0034
> +#define MT6323_CHR_CON27 0x0036
> +#define MT6323_CHR_CON28 0x0038
> +#define MT6323_CHR_CON29 0x003A
> +#define MT6323_STRUP_CON0 0x003C
> +#define MT6323_STRUP_CON2 0x003E
> +#define MT6323_STRUP_CON3 0x0040
> +#define MT6323_STRUP_CON4 0x0042
> +#define MT6323_STRUP_CON5 0x0044
> +#define MT6323_STRUP_CON6 0x0046
> +#define MT6323_STRUP_CON7 0x0048
> +#define MT6323_STRUP_CON8 0x004A
> +#define MT6323_STRUP_CON9 0x004C
> +#define MT6323_STRUP_CON10 0x004E
> +#define MT6323_STRUP_CON11 0x0050
> +#define MT6323_SPK_CON0 0x0052
> +#define MT6323_SPK_CON1 0x0054
> +#define MT6323_SPK_CON2 0x0056
> +#define MT6323_SPK_CON6 0x005E
> +#define MT6323_SPK_CON7 0x0060
> +#define MT6323_SPK_CON8 0x0062
> +#define MT6323_SPK_CON9 0x0064
> +#define MT6323_SPK_CON10 0x0066
> +#define MT6323_SPK_CON11 0x0068
> +#define MT6323_SPK_CON12 0x006A
> +#define MT6323_CID 0x0100
> +#define MT6323_TOP_CKPDN0 0x0102
> +#define MT6323_TOP_CKPDN0_SET 0x0104
> +#define MT6323_TOP_CKPDN0_CLR 0x0106
> +#define MT6323_TOP_CKPDN1 0x0108
> +#define MT6323_TOP_CKPDN1_SET 0x010A
> +#define MT6323_TOP_CKPDN1_CLR 0x010C
> +#define MT6323_TOP_CKPDN2 0x010E
> +#define MT6323_TOP_CKPDN2_SET 0x0110
> +#define MT6323_TOP_CKPDN2_CLR 0x0112
> +#define MT6323_TOP_RST_CON 0x0114
> +#define MT6323_TOP_RST_CON_SET 0x0116
> +#define MT6323_TOP_RST_CON_CLR 0x0118
> +#define MT6323_TOP_RST_MISC 0x011A
> +#define MT6323_TOP_RST_MISC_SET 0x011C
> +#define MT6323_TOP_RST_MISC_CLR 0x011E
> +#define MT6323_TOP_CKCON0 0x0120
> +#define MT6323_TOP_CKCON0_SET 0x0122
> +#define MT6323_TOP_CKCON0_CLR 0x0124
> +#define MT6323_TOP_CKCON1 0x0126
> +#define MT6323_TOP_CKCON1_SET 0x0128
> +#define MT6323_TOP_CKCON1_CLR 0x012A
> +#define MT6323_TOP_CKTST0 0x012C
> +#define MT6323_TOP_CKTST1 0x012E
> +#define MT6323_TOP_CKTST2 0x0130
> +#define MT6323_TEST_OUT 0x0132
> +#define MT6323_TEST_CON0 0x0134
> +#define MT6323_TEST_CON1 0x0136
> +#define MT6323_EN_STATUS0 0x0138
> +#define MT6323_EN_STATUS1 0x013A
> +#define MT6323_OCSTATUS0 0x013C
> +#define MT6323_OCSTATUS1 0x013E
> +#define MT6323_PGSTATUS 0x0140
> +#define MT6323_CHRSTATUS 0x0142
> +#define MT6323_TDSEL_CON 0x0144
> +#define MT6323_RDSEL_CON 0x0146
> +#define MT6323_SMT_CON0 0x0148
> +#define MT6323_SMT_CON1 0x014A
> +#define MT6323_SMT_CON2 0x014C
> +#define MT6323_SMT_CON3 0x014E
> +#define MT6323_SMT_CON4 0x0150
> +#define MT6323_DRV_CON0 0x0152
> +#define MT6323_DRV_CON1 0x0154
> +#define MT6323_DRV_CON2 0x0156
> +#define MT6323_DRV_CON3 0x0158
> +#define MT6323_DRV_CON4 0x015A
> +#define MT6323_SIMLS1_CON 0x015C
> +#define MT6323_SIMLS2_CON 0x015E
> +#define MT6323_INT_CON0 0x0160
> +#define MT6323_INT_CON0_SET 0x0162
> +#define MT6323_INT_CON0_CLR 0x0164
> +#define MT6323_INT_CON1 0x0166
> +#define MT6323_INT_CON1_SET 0x0168
> +#define MT6323_INT_CON1_CLR 0x016A
> +#define MT6323_INT_MISC_CON 0x016C
> +#define MT6323_INT_MISC_CON_SET 0x016E
> +#define MT6323_INT_MISC_CON_CLR 0x0170
> +#define MT6323_INT_STATUS0 0x0172
> +#define MT6323_INT_STATUS1 0x0174
> +#define MT6323_OC_GEAR_0 0x0176
> +#define MT6323_OC_GEAR_1 0x0178
> +#define MT6323_OC_GEAR_2 0x017A
> +#define MT6323_OC_CTL_VPROC 0x017C
> +#define MT6323_OC_CTL_VSYS 0x017E
> +#define MT6323_OC_CTL_VPA 0x0180
> +#define MT6323_FQMTR_CON0 0x0182
> +#define MT6323_FQMTR_CON1 0x0184
> +#define MT6323_FQMTR_CON2 0x0186
> +#define MT6323_RG_SPI_CON 0x0188
> +#define MT6323_DEW_DIO_EN 0x018A
> +#define MT6323_DEW_READ_TEST 0x018C
> +#define MT6323_DEW_WRITE_TEST 0x018E
> +#define MT6323_DEW_CRC_SWRST 0x0190
> +#define MT6323_DEW_CRC_EN 0x0192
> +#define MT6323_DEW_CRC_VAL 0x0194
> +#define MT6323_DEW_DBG_MON_SEL 0x0196
> +#define MT6323_DEW_CIPHER_KEY_SEL 0x0198
> +#define MT6323_DEW_CIPHER_IV_SEL 0x019A
> +#define MT6323_DEW_CIPHER_EN 0x019C
> +#define MT6323_DEW_CIPHER_RDY 0x019E
> +#define MT6323_DEW_CIPHER_MODE 0x01A0
> +#define MT6323_DEW_CIPHER_SWRST 0x01A2
> +#define MT6323_DEW_RDDMY_NO 0x01A4
> +#define MT6323_DEW_RDATA_DLY_SEL 0x01A6
> +#define MT6323_BUCK_CON0 0x0200
> +#define MT6323_BUCK_CON1 0x0202
> +#define MT6323_BUCK_CON2 0x0204
> +#define MT6323_BUCK_CON3 0x0206
> +#define MT6323_BUCK_CON4 0x0208
> +#define MT6323_BUCK_CON5 0x020A
> +#define MT6323_VPROC_CON0 0x020C
> +#define MT6323_VPROC_CON1 0x020E
> +#define MT6323_VPROC_CON2 0x0210
> +#define MT6323_VPROC_CON3 0x0212
> +#define MT6323_VPROC_CON4 0x0214
> +#define MT6323_VPROC_CON5 0x0216
> +#define MT6323_VPROC_CON7 0x021A
> +#define MT6323_VPROC_CON8 0x021C
> +#define MT6323_VPROC_CON9 0x021E
> +#define MT6323_VPROC_CON10 0x0220
> +#define MT6323_VPROC_CON11 0x0222
> +#define MT6323_VPROC_CON12 0x0224
> +#define MT6323_VPROC_CON13 0x0226
> +#define MT6323_VPROC_CON14 0x0228
> +#define MT6323_VPROC_CON15 0x022A
> +#define MT6323_VPROC_CON18 0x0230
> +#define MT6323_VSYS_CON0 0x0232
> +#define MT6323_VSYS_CON1 0x0234
> +#define MT6323_VSYS_CON2 0x0236
> +#define MT6323_VSYS_CON3 0x0238
> +#define MT6323_VSYS_CON4 0x023A
> +#define MT6323_VSYS_CON5 0x023C
> +#define MT6323_VSYS_CON7 0x0240
> +#define MT6323_VSYS_CON8 0x0242
> +#define MT6323_VSYS_CON9 0x0244
> +#define MT6323_VSYS_CON10 0x0246
> +#define MT6323_VSYS_CON11 0x0248
> +#define MT6323_VSYS_CON12 0x024A
> +#define MT6323_VSYS_CON13 0x024C
> +#define MT6323_VSYS_CON14 0x024E
> +#define MT6323_VSYS_CON15 0x0250
> +#define MT6323_VSYS_CON18 0x0256
> +#define MT6323_VPA_CON0 0x0300
> +#define MT6323_VPA_CON1 0x0302
> +#define MT6323_VPA_CON2 0x0304
> +#define MT6323_VPA_CON3 0x0306
> +#define MT6323_VPA_CON4 0x0308
> +#define MT6323_VPA_CON5 0x030A
> +#define MT6323_VPA_CON7 0x030E
> +#define MT6323_VPA_CON8 0x0310
> +#define MT6323_VPA_CON9 0x0312
> +#define MT6323_VPA_CON10 0x0314
> +#define MT6323_VPA_CON11 0x0316
> +#define MT6323_VPA_CON12 0x0318
> +#define MT6323_VPA_CON14 0x031C
> +#define MT6323_VPA_CON16 0x0320
> +#define MT6323_VPA_CON17 0x0322
> +#define MT6323_VPA_CON18 0x0324
> +#define MT6323_VPA_CON19 0x0326
> +#define MT6323_VPA_CON20 0x0328
> +#define MT6323_BUCK_K_CON0 0x032A
> +#define MT6323_BUCK_K_CON1 0x032C
> +#define MT6323_BUCK_K_CON2 0x032E
> +#define MT6323_ISINK0_CON0 0x0330
> +#define MT6323_ISINK0_CON1 0x0332
> +#define MT6323_ISINK0_CON2 0x0334
> +#define MT6323_ISINK0_CON3 0x0336
> +#define MT6323_ISINK1_CON0 0x0338
> +#define MT6323_ISINK1_CON1 0x033A
> +#define MT6323_ISINK1_CON2 0x033C
> +#define MT6323_ISINK1_CON3 0x033E
> +#define MT6323_ISINK2_CON0 0x0340
> +#define MT6323_ISINK2_CON1 0x0342
> +#define MT6323_ISINK2_CON2 0x0344
> +#define MT6323_ISINK2_CON3 0x0346
> +#define MT6323_ISINK3_CON0 0x0348
> +#define MT6323_ISINK3_CON1 0x034A
> +#define MT6323_ISINK3_CON2 0x034C
> +#define MT6323_ISINK3_CON3 0x034E
> +#define MT6323_ISINK_ANA0 0x0350
> +#define MT6323_ISINK_ANA1 0x0352
> +#define MT6323_ISINK_PHASE_DLY 0x0354
> +#define MT6323_ISINK_EN_CTRL 0x0356
> +#define MT6323_ANALDO_CON0 0x0400
> +#define MT6323_ANALDO_CON1 0x0402
> +#define MT6323_ANALDO_CON2 0x0404
> +#define MT6323_ANALDO_CON3 0x0406
> +#define MT6323_ANALDO_CON4 0x0408
> +#define MT6323_ANALDO_CON5 0x040A
> +#define MT6323_ANALDO_CON6 0x040C
> +#define MT6323_ANALDO_CON7 0x040E
> +#define MT6323_ANALDO_CON8 0x0410
> +#define MT6323_ANALDO_CON10 0x0412
> +#define MT6323_ANALDO_CON15 0x0414
> +#define MT6323_ANALDO_CON16 0x0416
> +#define MT6323_ANALDO_CON17 0x0418
> +#define MT6323_ANALDO_CON18 0x041A
> +#define MT6323_ANALDO_CON19 0x041C
> +#define MT6323_ANALDO_CON20 0x041E
> +#define MT6323_ANALDO_CON21 0x0420
> +#define MT6323_DIGLDO_CON0 0x0500
> +#define MT6323_DIGLDO_CON2 0x0502
> +#define MT6323_DIGLDO_CON3 0x0504
> +#define MT6323_DIGLDO_CON5 0x0506
> +#define MT6323_DIGLDO_CON6 0x0508
> +#define MT6323_DIGLDO_CON7 0x050A
> +#define MT6323_DIGLDO_CON8 0x050C
> +#define MT6323_DIGLDO_CON9 0x050E
> +#define MT6323_DIGLDO_CON10 0x0510
> +#define MT6323_DIGLDO_CON11 0x0512
> +#define MT6323_DIGLDO_CON12 0x0514
> +#define MT6323_DIGLDO_CON13 0x0516
> +#define MT6323_DIGLDO_CON14 0x0518
> +#define MT6323_DIGLDO_CON15 0x051A
> +#define MT6323_DIGLDO_CON16 0x051C
> +#define MT6323_DIGLDO_CON17 0x051E
> +#define MT6323_DIGLDO_CON18 0x0520
> +#define MT6323_DIGLDO_CON19 0x0522
> +#define MT6323_DIGLDO_CON20 0x0524
> +#define MT6323_DIGLDO_CON21 0x0526
> +#define MT6323_DIGLDO_CON23 0x0528
> +#define MT6323_DIGLDO_CON24 0x052A
> +#define MT6323_DIGLDO_CON26 0x052C
> +#define MT6323_DIGLDO_CON27 0x052E
> +#define MT6323_DIGLDO_CON28 0x0530
> +#define MT6323_DIGLDO_CON29 0x0532
> +#define MT6323_DIGLDO_CON30 0x0534
> +#define MT6323_DIGLDO_CON31 0x0536
> +#define MT6323_DIGLDO_CON32 0x0538
> +#define MT6323_DIGLDO_CON33 0x053A
> +#define MT6323_DIGLDO_CON34 0x053C
> +#define MT6323_DIGLDO_CON35 0x053E
> +#define MT6323_DIGLDO_CON36 0x0540
> +#define MT6323_DIGLDO_CON39 0x0542
> +#define MT6323_DIGLDO_CON40 0x0544
> +#define MT6323_DIGLDO_CON41 0x0546
> +#define MT6323_DIGLDO_CON42 0x0548
> +#define MT6323_DIGLDO_CON43 0x054A
> +#define MT6323_DIGLDO_CON44 0x054C
> +#define MT6323_DIGLDO_CON45 0x054E
> +#define MT6323_DIGLDO_CON46 0x0550
> +#define MT6323_DIGLDO_CON47 0x0552
> +#define MT6323_DIGLDO_CON48 0x0554
> +#define MT6323_DIGLDO_CON49 0x0556
> +#define MT6323_DIGLDO_CON50 0x0558
> +#define MT6323_DIGLDO_CON51 0x055A
> +#define MT6323_DIGLDO_CON52 0x055C
> +#define MT6323_DIGLDO_CON53 0x055E
> +#define MT6323_DIGLDO_CON54 0x0560
> +#define MT6323_EFUSE_CON0 0x0600
> +#define MT6323_EFUSE_CON1 0x0602
> +#define MT6323_EFUSE_CON2 0x0604
> +#define MT6323_EFUSE_CON3 0x0606
> +#define MT6323_EFUSE_CON4 0x0608
> +#define MT6323_EFUSE_CON5 0x060A
> +#define MT6323_EFUSE_CON6 0x060C
> +#define MT6323_EFUSE_VAL_0_15 0x060E
> +#define MT6323_EFUSE_VAL_16_31 0x0610
> +#define MT6323_EFUSE_VAL_32_47 0x0612
> +#define MT6323_EFUSE_VAL_48_63 0x0614
> +#define MT6323_EFUSE_VAL_64_79 0x0616
> +#define MT6323_EFUSE_VAL_80_95 0x0618
> +#define MT6323_EFUSE_VAL_96_111 0x061A
> +#define MT6323_EFUSE_VAL_112_127 0x061C
> +#define MT6323_EFUSE_VAL_128_143 0x061E
> +#define MT6323_EFUSE_VAL_144_159 0x0620
> +#define MT6323_EFUSE_VAL_160_175 0x0622
> +#define MT6323_EFUSE_VAL_176_191 0x0624
> +#define MT6323_EFUSE_DOUT_0_15 0x0626
> +#define MT6323_EFUSE_DOUT_16_31 0x0628
> +#define MT6323_EFUSE_DOUT_32_47 0x062A
> +#define MT6323_EFUSE_DOUT_48_63 0x062C
> +#define MT6323_EFUSE_DOUT_64_79 0x062E
> +#define MT6323_EFUSE_DOUT_80_95 0x0630
> +#define MT6323_EFUSE_DOUT_96_111 0x0632
> +#define MT6323_EFUSE_DOUT_112_127 0x0634
> +#define MT6323_EFUSE_DOUT_128_143 0x0636
> +#define MT6323_EFUSE_DOUT_144_159 0x0638
> +#define MT6323_EFUSE_DOUT_160_175 0x063A
> +#define MT6323_EFUSE_DOUT_176_191 0x063C
> +#define MT6323_EFUSE_CON7 0x063E
> +#define MT6323_EFUSE_CON8 0x0640
> +#define MT6323_EFUSE_CON9 0x0642
> +#define MT6323_RTC_MIX_CON0 0x0644
> +#define MT6323_RTC_MIX_CON1 0x0646
> +#define MT6323_AUDTOP_CON0 0x0700
> +#define MT6323_AUDTOP_CON1 0x0702
> +#define MT6323_AUDTOP_CON2 0x0704
> +#define MT6323_AUDTOP_CON3 0x0706
> +#define MT6323_AUDTOP_CON4 0x0708
> +#define MT6323_AUDTOP_CON5 0x070A
> +#define MT6323_AUDTOP_CON6 0x070C
> +#define MT6323_AUDTOP_CON7 0x070E
> +#define MT6323_AUDTOP_CON8 0x0710
> +#define MT6323_AUDTOP_CON9 0x0712
> +#define MT6323_AUXADC_ADC0 0x0714
> +#define MT6323_AUXADC_ADC1 0x0716
> +#define MT6323_AUXADC_ADC2 0x0718
> +#define MT6323_AUXADC_ADC3 0x071A
> +#define MT6323_AUXADC_ADC4 0x071C
> +#define MT6323_AUXADC_ADC5 0x071E
> +#define MT6323_AUXADC_ADC6 0x0720
> +#define MT6323_AUXADC_ADC7 0x0722
> +#define MT6323_AUXADC_ADC8 0x0724
> +#define MT6323_AUXADC_ADC9 0x0726
> +#define MT6323_AUXADC_ADC10 0x0728
> +#define MT6323_AUXADC_ADC11 0x072A
> +#define MT6323_AUXADC_ADC12 0x072C
> +#define MT6323_AUXADC_ADC13 0x072E
> +#define MT6323_AUXADC_ADC14 0x0730
> +#define MT6323_AUXADC_ADC15 0x0732
> +#define MT6323_AUXADC_ADC16 0x0734
> +#define MT6323_AUXADC_ADC17 0x0736
> +#define MT6323_AUXADC_ADC18 0x0738
> +#define MT6323_AUXADC_ADC19 0x073A
> +#define MT6323_AUXADC_ADC20 0x073C
> +#define MT6323_AUXADC_RSV1 0x073E
> +#define MT6323_AUXADC_RSV2 0x0740
> +#define MT6323_AUXADC_CON0 0x0742
> +#define MT6323_AUXADC_CON1 0x0744
> +#define MT6323_AUXADC_CON2 0x0746
> +#define MT6323_AUXADC_CON3 0x0748
> +#define MT6323_AUXADC_CON4 0x074A
> +#define MT6323_AUXADC_CON5 0x074C
> +#define MT6323_AUXADC_CON6 0x074E
> +#define MT6323_AUXADC_CON7 0x0750
> +#define MT6323_AUXADC_CON8 0x0752
> +#define MT6323_AUXADC_CON9 0x0754
> +#define MT6323_AUXADC_CON10 0x0756
> +#define MT6323_AUXADC_CON11 0x0758
> +#define MT6323_AUXADC_CON12 0x075A
> +#define MT6323_AUXADC_CON13 0x075C
> +#define MT6323_AUXADC_CON14 0x075E
> +#define MT6323_AUXADC_CON15 0x0760
> +#define MT6323_AUXADC_CON16 0x0762
> +#define MT6323_AUXADC_CON17 0x0764
> +#define MT6323_AUXADC_CON18 0x0766
> +#define MT6323_AUXADC_CON19 0x0768
> +#define MT6323_AUXADC_CON20 0x076A
> +#define MT6323_AUXADC_CON21 0x076C
> +#define MT6323_AUXADC_CON22 0x076E
> +#define MT6323_AUXADC_CON23 0x0770
> +#define MT6323_AUXADC_CON24 0x0772
> +#define MT6323_AUXADC_CON25 0x0774
> +#define MT6323_AUXADC_CON26 0x0776
> +#define MT6323_AUXADC_CON27 0x0778
> +#define MT6323_ACCDET_CON0 0x077A
> +#define MT6323_ACCDET_CON1 0x077C
> +#define MT6323_ACCDET_CON2 0x077E
> +#define MT6323_ACCDET_CON3 0x0780
> +#define MT6323_ACCDET_CON4 0x0782
> +#define MT6323_ACCDET_CON5 0x0784
> +#define MT6323_ACCDET_CON6 0x0786
> +#define MT6323_ACCDET_CON7 0x0788
> +#define MT6323_ACCDET_CON8 0x078A
> +#define MT6323_ACCDET_CON9 0x078C
> +#define MT6323_ACCDET_CON10 0x078E
> +#define MT6323_ACCDET_CON11 0x0790
> +#define MT6323_ACCDET_CON12 0x0792
> +#define MT6323_ACCDET_CON13 0x0794
> +#define MT6323_ACCDET_CON14 0x0796
> +#define MT6323_ACCDET_CON15 0x0798
> +#define MT6323_ACCDET_CON16 0x079A
> +
> +#endif /* __MFD_MT6323_REGISTERS_H__ */
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC
2016-01-27 11:47 [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC John Crispin
` (2 preceding siblings ...)
2016-01-27 11:47 ` [PATCH V3 4/4] mfd: mt6397: add MT6323 support to MT6397 driver John Crispin
@ 2016-02-01 15:41 ` Rob Herring
2016-02-10 16:58 ` Lee Jones
2016-02-10 17:01 ` Lee Jones
5 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2016-02-01 15:41 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 27, 2016 at 12:47:35PM +0100, John Crispin wrote:
> Signed-off-by: John Crispin <blogic@openwrt.org>
> Cc: devicetree at vger.kernel.org
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC
2016-01-27 11:47 [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC John Crispin
` (3 preceding siblings ...)
2016-02-01 15:41 ` [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC Rob Herring
@ 2016-02-10 16:58 ` Lee Jones
2016-02-10 17:01 ` Lee Jones
5 siblings, 0 replies; 10+ messages in thread
From: Lee Jones @ 2016-02-10 16:58 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 27 Jan 2016, John Crispin wrote:
> Signed-off-by: John Crispin <blogic@openwrt.org>
> Cc: devicetree at vger.kernel.org
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Applied, thanks.
> diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
> index 15043e6..949c85f 100644
> --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
> +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
> @@ -1,6 +1,6 @@
> -MediaTek MT6397 Multifunction Device Driver
> +MediaTek MT6397/MT6323 Multifunction Device Driver
>
> -MT6397 is a multifunction device with the following sub modules:
> +MT6397/MT6323 is a multifunction device with the following sub modules:
> - Regulator
> - RTC
> - Audio codec
> @@ -8,14 +8,14 @@ MT6397 is a multifunction device with the following sub modules:
> - Clock
>
> It is interfaced to host controller using SPI interface by a proprietary hardware
> -called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
> +called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
> See the following for pwarp node definitions:
> Documentation/devicetree/bindings/soc/pwrap.txt
>
> This document describes the binding for MFD device and its sub module.
>
> Required properties:
> -compatible: "mediatek,mt6397"
> +compatible: "mediatek,mt6397" or "mediatek,mt6323"
>
> Optional subnodes:
>
> @@ -26,6 +26,8 @@ Optional subnodes:
> Required properties:
> - compatible: "mediatek,mt6397-regulator"
> see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
> + - compatible: "mediatek,mt6323-regulator"
> + see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
> - codec
> Required properties:
> - compatible: "mediatek,mt6397-codec"
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC
2016-01-27 11:47 [PATCH V3 1/4] dt-bindings: mfd: Add bindings for the MediaTek MT6323 PMIC John Crispin
` (4 preceding siblings ...)
2016-02-10 16:58 ` Lee Jones
@ 2016-02-10 17:01 ` Lee Jones
5 siblings, 0 replies; 10+ messages in thread
From: Lee Jones @ 2016-02-10 17:01 UTC (permalink / raw)
To: linux-arm-kernel
If you're submitting a set of patches like this, you really ought to
be providing a cover-letter.
Also, when submitting patches, please do so in the style expected by
the subsystem. I will fix these once up for now, but please bear that
in mind in the future.
`git log --oneline -- <subsystem>` works well for this.
> Signed-off-by: John Crispin <blogic@openwrt.org>
> Cc: devicetree at vger.kernel.org
> ---
> Documentation/devicetree/bindings/mfd/mt6397.txt | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
> index 15043e6..949c85f 100644
> --- a/Documentation/devicetree/bindings/mfd/mt6397.txt
> +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
> @@ -1,6 +1,6 @@
> -MediaTek MT6397 Multifunction Device Driver
> +MediaTek MT6397/MT6323 Multifunction Device Driver
>
> -MT6397 is a multifunction device with the following sub modules:
> +MT6397/MT6323 is a multifunction device with the following sub modules:
> - Regulator
> - RTC
> - Audio codec
> @@ -8,14 +8,14 @@ MT6397 is a multifunction device with the following sub modules:
> - Clock
>
> It is interfaced to host controller using SPI interface by a proprietary hardware
> -called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
> +called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
> See the following for pwarp node definitions:
> Documentation/devicetree/bindings/soc/pwrap.txt
>
> This document describes the binding for MFD device and its sub module.
>
> Required properties:
> -compatible: "mediatek,mt6397"
> +compatible: "mediatek,mt6397" or "mediatek,mt6323"
>
> Optional subnodes:
>
> @@ -26,6 +26,8 @@ Optional subnodes:
> Required properties:
> - compatible: "mediatek,mt6397-regulator"
> see Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
> + - compatible: "mediatek,mt6323-regulator"
> + see Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
> - codec
> Required properties:
> - compatible: "mediatek,mt6397-codec"
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 10+ messages in thread