From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
Date: Fri, 12 Feb 2016 14:16:54 +0000 [thread overview]
Message-ID: <20160212141654.GA10826@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1455261093-11849-1-git-send-email-dirk.behme@de.bosch.com>
On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
> All the generic L2 cache handling code is encapsulated by a
> check if the L2 cache is enabled. If it's enabled already, the code
> is skipped.
>
> For the i.MX6 specific L2 cache handling we missed this check.
> Add it.
What's the reasoning behind this? The prefetch register is writable
while the L2 cache is enabled, unlike the auxiliary control register.
--
RMK's Patch system: http://www.arm.linux.org.uk/developer/patches/
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next prev parent reply other threads:[~2016-02-12 14:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-12 7:11 [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled Dirk Behme
2016-02-12 14:16 ` Russell King - ARM Linux [this message]
2016-02-12 15:51 ` Dirk Behme
2016-02-14 8:18 ` Shawn Guo
2016-02-14 8:30 ` Dirk Behme
2016-02-18 14:57 ` Shawn Guo
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