From: shawnguo@kernel.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled
Date: Sun, 14 Feb 2016 16:18:57 +0800 [thread overview]
Message-ID: <20160214081857.GQ6756@tiger> (raw)
In-Reply-To: <56BDFF64.9090701@gmail.com>
On Fri, Feb 12, 2016 at 04:51:00PM +0100, Dirk Behme wrote:
> On 12.02.2016 15:16, Russell King - ARM Linux wrote:
> >On Fri, Feb 12, 2016 at 08:11:33AM +0100, Dirk Behme wrote:
> >>All the generic L2 cache handling code is encapsulated by a
> >>check if the L2 cache is enabled. If it's enabled already, the code
> >>is skipped.
> >>
> >>For the i.MX6 specific L2 cache handling we missed this check.
> >>Add it.
> >
> >What's the reasoning behind this? The prefetch register is writable
> >while the L2 cache is enabled, unlike the auxiliary control register.
>
> From an internal log I have the following info:
>
> The write to the L2-Cache controller from non-secure world causes an
> imprecise
> external abort. If Linux runs from normal world the cache controller
> is already
> enabled and thus no configuration is needed by Linux.
Dirk,
Do you have a real use case of this, i.e. running Linux on i.MX6 in
non-secure world?
Shawn
next prev parent reply other threads:[~2016-02-14 8:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-12 7:11 [PATCH] ARM: imx: Do L2 errata only if the L2 cache isn't enabled Dirk Behme
2016-02-12 14:16 ` Russell King - ARM Linux
2016-02-12 15:51 ` Dirk Behme
2016-02-14 8:18 ` Shawn Guo [this message]
2016-02-14 8:30 ` Dirk Behme
2016-02-18 14:57 ` Shawn Guo
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