[PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates

[mturquette@baylibre.com (Michael Turquette)]

Quoting Eric Anholt (2016-02-15 19:03:57)
> Our dividers weren't being set successfully because CM_PASSWORD wasn't
> included in the register write.  It looks easier to just compute the
> divider to write ourselves than to update clk-divider for the ability
> to OR in some arbitrary bits on write.
> 
> Fixes about half of the video modes on my HDMI monitor (everything
> except 720x400).
> 
> Cc: stable at vger.kernel.org
> Signed-off-by: Eric Anholt <eric@anholt.net>

Applied to clk-next.

Regards,
Mike

> ---
>  drivers/clk/bcm/clk-bcm2835.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 015e687..9f4df8f 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1107,13 +1107,15 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
>         struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
>         struct bcm2835_cprman *cprman = divider->cprman;
>         const struct bcm2835_pll_divider_data *data = divider->data;
> -       u32 cm;
> -       int ret;
> +       u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
>  
> -       ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
> -       if (ret)
> -               return ret;
> +       div = DIV_ROUND_UP_ULL(parent_rate, rate);
> +
> +       div = min(div, max_div);
> +       if (div == max_div)
> +               div = 0;
>  
> +       cprman_write(cprman, data->a2w_reg, div);
>         cm = cprman_read(cprman, data->cm_reg);
>         cprman_write(cprman, data->cm_reg, cm | data->load_mask);
>         cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
> -- 
> 2.7.0
>