* [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates
@ 2016-02-16 3:03 Eric Anholt
2016-02-16 3:03 ` [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate() Eric Anholt
2016-02-16 21:44 ` [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Michael Turquette
0 siblings, 2 replies; 4+ messages in thread
From: Eric Anholt @ 2016-02-16 3:03 UTC (permalink / raw)
To: linux-arm-kernel
Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write. It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.
Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).
Cc: stable at vger.kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
---
drivers/clk/bcm/clk-bcm2835.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 015e687..9f4df8f 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1107,13 +1107,15 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
struct bcm2835_cprman *cprman = divider->cprman;
const struct bcm2835_pll_divider_data *data = divider->data;
- u32 cm;
- int ret;
+ u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
- ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
- if (ret)
- return ret;
+ div = DIV_ROUND_UP_ULL(parent_rate, rate);
+
+ div = min(div, max_div);
+ if (div == max_div)
+ div = 0;
+ cprman_write(cprman, data->a2w_reg, div);
cm = cprman_read(cprman, data->cm_reg);
cprman_write(cprman, data->cm_reg, cm | data->load_mask);
cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
--
2.7.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()
2016-02-16 3:03 [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Eric Anholt
@ 2016-02-16 3:03 ` Eric Anholt
2016-02-16 21:45 ` Michael Turquette
2016-02-16 21:44 ` [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Michael Turquette
1 sibling, 1 reply; 4+ messages in thread
From: Eric Anholt @ 2016-02-16 3:03 UTC (permalink / raw)
To: linux-arm-kernel
We were rolling this ourselves, but clk-divider can do it now.
Signed-off-by: Eric Anholt <eric@anholt.net>
---
drivers/clk/bcm/clk-bcm2835.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 9f4df8f..353e438 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1060,16 +1060,7 @@ static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
- struct bcm2835_cprman *cprman = divider->cprman;
- const struct bcm2835_pll_divider_data *data = divider->data;
- u32 div = cprman_read(cprman, data->a2w_reg);
-
- div &= (1 << A2W_PLL_DIV_BITS) - 1;
- if (div == 0)
- div = 256;
-
- return parent_rate / div;
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
}
static void bcm2835_pll_divider_off(struct clk_hw *hw)
@@ -1430,7 +1421,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
divider->div.reg = cprman->regs + data->a2w_reg;
divider->div.shift = A2W_PLL_DIV_SHIFT;
divider->div.width = A2W_PLL_DIV_BITS;
- divider->div.flags = 0;
+ divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
divider->div.lock = &cprman->regs_lock;
divider->div.hw.init = &init;
divider->div.table = NULL;
--
2.7.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()
2016-02-16 3:03 ` [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate() Eric Anholt
@ 2016-02-16 21:45 ` Michael Turquette
0 siblings, 0 replies; 4+ messages in thread
From: Michael Turquette @ 2016-02-16 21:45 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Eric Anholt (2016-02-15 19:03:58)
> We were rolling this ourselves, but clk-divider can do it now.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/bcm/clk-bcm2835.c | 13 ++-----------
> 1 file changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 9f4df8f..353e438 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1060,16 +1060,7 @@ static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
> static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> - struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
> - struct bcm2835_cprman *cprman = divider->cprman;
> - const struct bcm2835_pll_divider_data *data = divider->data;
> - u32 div = cprman_read(cprman, data->a2w_reg);
> -
> - div &= (1 << A2W_PLL_DIV_BITS) - 1;
> - if (div == 0)
> - div = 256;
> -
> - return parent_rate / div;
> + return clk_divider_ops.recalc_rate(hw, parent_rate);
> }
>
> static void bcm2835_pll_divider_off(struct clk_hw *hw)
> @@ -1430,7 +1421,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
> divider->div.reg = cprman->regs + data->a2w_reg;
> divider->div.shift = A2W_PLL_DIV_SHIFT;
> divider->div.width = A2W_PLL_DIV_BITS;
> - divider->div.flags = 0;
> + divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
> divider->div.lock = &cprman->regs_lock;
> divider->div.hw.init = &init;
> divider->div.table = NULL;
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates
2016-02-16 3:03 [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Eric Anholt
2016-02-16 3:03 ` [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate() Eric Anholt
@ 2016-02-16 21:44 ` Michael Turquette
1 sibling, 0 replies; 4+ messages in thread
From: Michael Turquette @ 2016-02-16 21:44 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Eric Anholt (2016-02-15 19:03:57)
> Our dividers weren't being set successfully because CM_PASSWORD wasn't
> included in the register write. It looks easier to just compute the
> divider to write ourselves than to update clk-divider for the ability
> to OR in some arbitrary bits on write.
>
> Fixes about half of the video modes on my HDMI monitor (everything
> except 720x400).
>
> Cc: stable at vger.kernel.org
> Signed-off-by: Eric Anholt <eric@anholt.net>
Applied to clk-next.
Regards,
Mike
> ---
> drivers/clk/bcm/clk-bcm2835.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 015e687..9f4df8f 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1107,13 +1107,15 @@ static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
> struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
> struct bcm2835_cprman *cprman = divider->cprman;
> const struct bcm2835_pll_divider_data *data = divider->data;
> - u32 cm;
> - int ret;
> + u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
>
> - ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
> - if (ret)
> - return ret;
> + div = DIV_ROUND_UP_ULL(parent_rate, rate);
> +
> + div = min(div, max_div);
> + if (div == max_div)
> + div = 0;
>
> + cprman_write(cprman, data->a2w_reg, div);
> cm = cprman_read(cprman, data->cm_reg);
> cprman_write(cprman, data->cm_reg, cm | data->load_mask);
> cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
> --
> 2.7.0
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2016-02-16 3:03 [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Eric Anholt
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2016-02-16 21:45 ` Michael Turquette
2016-02-16 21:44 ` [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Michael Turquette
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