* [PATCH v2 1/5] dt-binding: Change the mbigen binding file to support the mbigen-v1
2016-02-16 6:37 [PATCH v2 0/5] irqchip: Add support for Hisilicon mbigen v1 chip MaJun
@ 2016-02-16 6:37 ` MaJun
2016-02-16 6:37 ` [PATCH v2 2/5] dt-binding:Rename the mbigen binding file name MaJun
` (3 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: MaJun @ 2016-02-16 6:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ma Jun <majun258@huawei.com>
Add the "hisilicon,mbigen-v1" string in binding file.
Signed-off-by: Ma Jun <majun258@huawei.com>
---
.../interrupt-controller/hisilicon,mbigen-v2.txt | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
index 720f7c9..bdd1dea 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
@@ -16,7 +16,7 @@ The mbigen chip and devices connect to mbigen have the following properties:
Mbigen main node required properties:
-------------------------------------------
-- compatible: Should be "hisilicon,mbigen-v2"
+- compatible: Should be "hisilicon,mbigen-v2" or "hisilicon,mbigen-v1"
- reg: Specifies the base physical address and size of the Mbigen
registers.
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 2/5] dt-binding:Rename the mbigen binding file name
2016-02-16 6:37 [PATCH v2 0/5] irqchip: Add support for Hisilicon mbigen v1 chip MaJun
2016-02-16 6:37 ` [PATCH v2 1/5] dt-binding: Change the mbigen binding file to support the mbigen-v1 MaJun
@ 2016-02-16 6:37 ` MaJun
2016-02-16 6:37 ` [PATCH v2 3/5] irqchip: add platform device driver for mbigen device MaJun
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: MaJun @ 2016-02-16 6:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ma Jun <majun258@huawei.com>
Because added the mbigen-v1 compatible string, the origin name is
not suitable any more. So,I remove the version number from file name.
Signed-off-by: Ma Jun <majun258@huawei.com>
---
.../interrupt-controller/hisilicon,mbigen-v2.txt | 74 --------------------
.../interrupt-controller/hisilicon,mbigen.txt | 74 ++++++++++++++++++++
2 files changed, 74 insertions(+), 74 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
deleted file mode 100644
index bdd1dea..0000000
--- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Hisilicon mbigen device tree bindings.
-=======================================
-
-Mbigen means: message based interrupt generator.
-
-MBI is kind of msi interrupt only used on Non-PCI devices.
-
-To reduce the wired interrupt number connected to GIC,
-Hisilicon designed mbigen to collect and generate interrupt.
-
-
-Non-pci devices can connect to mbigen and generate the
-interrupt by writing ITS register.
-
-The mbigen chip and devices connect to mbigen have the following properties:
-
-Mbigen main node required properties:
--------------------------------------------
-- compatible: Should be "hisilicon,mbigen-v2" or "hisilicon,mbigen-v1"
-
-- reg: Specifies the base physical address and size of the Mbigen
- registers.
-
-- interrupt controller: Identifies the node as an interrupt controller
-
-- msi-parent: Specifies the MSI controller this mbigen use.
- For more detail information,please refer to the generic msi-parent binding in
- Documentation/devicetree/bindings/interrupt-controller/msi.txt.
-
-- num-pins: the total number of pins implemented in this Mbigen
- instance.
-
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value must be 2.
-
- The 1st cell is hardware pin number of the interrupt.This number is local to
- each mbigen chip and in the range from 0 to the maximum interrupts number
- of the mbigen.
-
- The 2nd cell is the interrupt trigger type.
- The value of this cell should be:
- 1: rising edge triggered
- or
- 4: high level triggered
-
-Examples:
-
- mbigen_device_gmac:intc {
- compatible = "hisilicon,mbigen-v2";
- reg = <0x0 0xc0080000 0x0 0x10000>;
- interrupt-controller;
- msi-parent = <&its_dsa 0x40b1c>;
- num-pins = <9>;
- #interrupt-cells = <2>;
- };
-
-Devices connect to mbigen required properties:
-----------------------------------------------------
--interrupt-parent: Specifies the mbigen device node which device connected.
-
--interrupts:Specifies the interrupt source.
- For the specific information of each cell in this property,please refer to
- the "interrupt-cells" description mentioned above.
-
-Examples:
- gmac0: ethernet at c2080000 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0 0xc2080000 0 0x20000>,
- <0 0xc0000000 0 0x1000>;
- interrupt-parent = <&mbigen_device_gmac>;
- interrupts = <656 1>,
- <657 1>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen.txt
new file mode 100644
index 0000000..bdd1dea
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen.txt
@@ -0,0 +1,74 @@
+Hisilicon mbigen device tree bindings.
+=======================================
+
+Mbigen means: message based interrupt generator.
+
+MBI is kind of msi interrupt only used on Non-PCI devices.
+
+To reduce the wired interrupt number connected to GIC,
+Hisilicon designed mbigen to collect and generate interrupt.
+
+
+Non-pci devices can connect to mbigen and generate the
+interrupt by writing ITS register.
+
+The mbigen chip and devices connect to mbigen have the following properties:
+
+Mbigen main node required properties:
+-------------------------------------------
+- compatible: Should be "hisilicon,mbigen-v2" or "hisilicon,mbigen-v1"
+
+- reg: Specifies the base physical address and size of the Mbigen
+ registers.
+
+- interrupt controller: Identifies the node as an interrupt controller
+
+- msi-parent: Specifies the MSI controller this mbigen use.
+ For more detail information,please refer to the generic msi-parent binding in
+ Documentation/devicetree/bindings/interrupt-controller/msi.txt.
+
+- num-pins: the total number of pins implemented in this Mbigen
+ instance.
+
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value must be 2.
+
+ The 1st cell is hardware pin number of the interrupt.This number is local to
+ each mbigen chip and in the range from 0 to the maximum interrupts number
+ of the mbigen.
+
+ The 2nd cell is the interrupt trigger type.
+ The value of this cell should be:
+ 1: rising edge triggered
+ or
+ 4: high level triggered
+
+Examples:
+
+ mbigen_device_gmac:intc {
+ compatible = "hisilicon,mbigen-v2";
+ reg = <0x0 0xc0080000 0x0 0x10000>;
+ interrupt-controller;
+ msi-parent = <&its_dsa 0x40b1c>;
+ num-pins = <9>;
+ #interrupt-cells = <2>;
+ };
+
+Devices connect to mbigen required properties:
+----------------------------------------------------
+-interrupt-parent: Specifies the mbigen device node which device connected.
+
+-interrupts:Specifies the interrupt source.
+ For the specific information of each cell in this property,please refer to
+ the "interrupt-cells" description mentioned above.
+
+Examples:
+ gmac0: ethernet at c2080000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0xc2080000 0 0x20000>,
+ <0 0xc0000000 0 0x1000>;
+ interrupt-parent = <&mbigen_device_gmac>;
+ interrupts = <656 1>,
+ <657 1>;
+ };
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 3/5] irqchip: add platform device driver for mbigen device
2016-02-16 6:37 [PATCH v2 0/5] irqchip: Add support for Hisilicon mbigen v1 chip MaJun
2016-02-16 6:37 ` [PATCH v2 1/5] dt-binding: Change the mbigen binding file to support the mbigen-v1 MaJun
2016-02-16 6:37 ` [PATCH v2 2/5] dt-binding:Rename the mbigen binding file name MaJun
@ 2016-02-16 6:37 ` MaJun
2016-02-16 6:37 ` [PATCH v2 4/5] irqchip:create irq domain for each " MaJun
2016-02-16 6:37 ` [PATCH v2 5/5] irqchip:implement the mbigen irq chip operation functions MaJun
4 siblings, 0 replies; 9+ messages in thread
From: MaJun @ 2016-02-16 6:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ma Jun <majun258@huawei.com>
Add the platform device driver for mbigen chip v1.
This patch just same as mbigen v2.
Signed-off-by: Ma Jun <majun258@huawei.com>
---
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/irq-mbigen-v1.c | 76 +++++++++++++++++++++++++++++++++++++++
2 files changed, 77 insertions(+), 1 deletions(-)
create mode 100644 drivers/irqchip/irq-mbigen-v1.c
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index d91d99d..d4b9c7f 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -25,7 +25,7 @@ obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o
obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
-obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o
+obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o irq-mbigen-v1.o
obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
obj-$(CONFIG_ARM_VIC) += irq-vic.o
obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
diff --git a/drivers/irqchip/irq-mbigen-v1.c b/drivers/irqchip/irq-mbigen-v1.c
new file mode 100644
index 0000000..9445658
--- /dev/null
+++ b/drivers/irqchip/irq-mbigen-v1.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
+ * Author: Jun Ma <majun258@huawei.com>
+ * Author: Yun Wu <wuyun.wu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/**
+ * struct mbigen_device - holds the information of mbigen device.
+ *
+ * @pdev: pointer to the platform device structure of mbigen chip.
+ * @base: mapped address of this mbigen chip.
+ */
+struct mbigen_device {
+ struct platform_device *pdev;
+ void __iomem *base;
+};
+
+static int mbigen_device_probe(struct platform_device *pdev)
+{
+ struct mbigen_device *mgn_chip;
+ struct resource *res;
+
+ mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
+ if (!mgn_chip)
+ return -ENOMEM;
+
+ mgn_chip->pdev = pdev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mgn_chip->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mgn_chip->base))
+ return PTR_ERR(mgn_chip->base);
+
+ platform_set_drvdata(pdev, mgn_chip);
+
+ return 0;
+}
+
+static const struct of_device_id mbigen_of_match[] = {
+ { .compatible = "hisilicon,mbigen-v1" },
+ { /* END */ }
+};
+MODULE_DEVICE_TABLE(of, mbigen_of_match);
+
+static struct platform_driver mbigen_platform_driver = {
+ .driver = {
+ .name = "Hisilicon MBIGEN-V1",
+ .owner = THIS_MODULE,
+ .of_match_table = mbigen_of_match,
+ },
+ .probe = mbigen_device_probe,
+};
+
+module_platform_driver(mbigen_platform_driver);
+
+MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
+MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/5] irqchip:create irq domain for each mbigen device
2016-02-16 6:37 [PATCH v2 0/5] irqchip: Add support for Hisilicon mbigen v1 chip MaJun
` (2 preceding siblings ...)
2016-02-16 6:37 ` [PATCH v2 3/5] irqchip: add platform device driver for mbigen device MaJun
@ 2016-02-16 6:37 ` MaJun
2016-02-16 8:50 ` Marc Zyngier
2016-02-16 6:37 ` [PATCH v2 5/5] irqchip:implement the mbigen irq chip operation functions MaJun
4 siblings, 1 reply; 9+ messages in thread
From: MaJun @ 2016-02-16 6:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ma Jun <majun258@huawei.com>
For peripheral devices which connect to mbigen,mbigen is a interrupt
controller. So, we create irq domain for each mbigen device and add
mbigen irq domain into irq hierarchy structure.
Signed-off-by: Ma Jun <majun258@huawei.com>
---
drivers/irqchip/irq-mbigen-v1.c | 136 +++++++++++++++++++++++++++++++++++++++
1 files changed, 136 insertions(+), 0 deletions(-)
diff --git a/drivers/irqchip/irq-mbigen-v1.c b/drivers/irqchip/irq-mbigen-v1.c
index 9445658..61e7ad0 100644
--- a/drivers/irqchip/irq-mbigen-v1.c
+++ b/drivers/irqchip/irq-mbigen-v1.c
@@ -16,11 +16,30 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+/* The maximum IRQ pin number of mbigen chip(start from 0) */
+#define MAXIMUM_IRQ_PIN_NUM 640
+
+/**
+ * In mbigen vector register
+ * bit[31:16]: device id
+ * bit[15:0]: event id value
+ */
+#define IRQ_EVENT_ID_MASK 0xffff
+
+/* offset of vector register in mbigen node */
+#define REG_MBIGEN_VEC_OFFSET 0x300
+#define REG_MBIGEN_EXT_VEC_OFFSET 0x320
+
/**
* struct mbigen_device - holds the information of mbigen device.
*
@@ -32,10 +51,112 @@ struct mbigen_device {
void __iomem *base;
};
+static int get_mbigen_nid(unsigned int offset)
+{
+ int nid = 0;
+
+ if (offset < 256)
+ nid = offset / 64;
+ else if (offset < 384)
+ nid = 4;
+ else if (offset < 640)
+ nid = 5;
+
+ return nid;
+}
+
+static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
+{
+ unsigned int nid;
+
+ nid = get_mbigen_nid(hwirq);
+
+ if (nid < 4)
+ return (nid * 4) + REG_MBIGEN_VEC_OFFSET;
+ else
+ return (nid - 4) * 4 + REG_MBIGEN_EXT_VEC_OFFSET;
+}
+
+static struct irq_chip mbigen_irq_chip = {
+ .name = "mbigen-v1",
+};
+
+static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+ /* The address of doorbell is encoded in mbigen register by default
+ * So,we don't need to program the doorbell address@here
+ * Besides, the event ID is decided by the hardware pin number,
+ * we can't change it in software.So, we don't need to encode the
+ * event ID in mbigen register.
+ */
+}
+
+static int mbigen_domain_translate(struct irq_domain *d,
+ struct irq_fwspec *fwspec,
+ unsigned long *hwirq,
+ unsigned int *type)
+{
+ if (is_of_node(fwspec->fwnode)) {
+ if (fwspec->param_count != 2)
+ return -EINVAL;
+
+ if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM)
+ return -EINVAL;
+
+ *hwirq = fwspec->param[0];
+
+ /* If there is no valid irq type, just use the default type */
+ if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
+ (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
+ *type = fwspec->param[1];
+ else
+ return -EINVAL;
+
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static int mbigen_irq_domain_alloc(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs,
+ void *args)
+{
+ struct irq_fwspec *fwspec = args;
+ irq_hw_number_t hwirq;
+ unsigned int type;
+ struct mbigen_device *mgn_chip;
+ int i, err;
+
+ err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
+ if (err)
+ return err;
+
+ err = platform_msi_domain_alloc(domain, virq, nr_irqs);
+ if (err)
+ return err;
+
+ mgn_chip = platform_msi_get_host_data(domain);
+
+ for (i = 0; i < nr_irqs; i++)
+ irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+ &mbigen_irq_chip, mgn_chip->base);
+
+ return 0;
+}
+
+static struct irq_domain_ops mbigen_domain_ops = {
+ .translate = mbigen_domain_translate,
+ .alloc = mbigen_irq_domain_alloc,
+ .free = irq_domain_free_irqs_common,
+};
+
static int mbigen_device_probe(struct platform_device *pdev)
{
struct mbigen_device *mgn_chip;
struct resource *res;
+ struct irq_domain *domain;
+ u32 num_pins;
mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
if (!mgn_chip)
@@ -48,8 +169,23 @@ static int mbigen_device_probe(struct platform_device *pdev)
if (IS_ERR(mgn_chip->base))
return PTR_ERR(mgn_chip->base);
+ if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) {
+ dev_err(&pdev->dev, "No num-pins property\n");
+ return -EINVAL;
+ }
+
+ domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
+ mbigen_write_msg,
+ &mbigen_domain_ops,
+ mgn_chip);
+
+ if (!domain)
+ return -ENOMEM;
+
platform_set_drvdata(pdev, mgn_chip);
+ dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins);
+
return 0;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v2 4/5] irqchip:create irq domain for each mbigen device
2016-02-16 6:37 ` [PATCH v2 4/5] irqchip:create irq domain for each " MaJun
@ 2016-02-16 8:50 ` Marc Zyngier
2016-02-17 4:18 ` majun (F)
0 siblings, 1 reply; 9+ messages in thread
From: Marc Zyngier @ 2016-02-16 8:50 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, 16 Feb 2016 14:37:27 +0800
MaJun <majun258@huawei.com> wrote:
> From: Ma Jun <majun258@huawei.com>
>
> For peripheral devices which connect to mbigen,mbigen is a interrupt
> controller. So, we create irq domain for each mbigen device and add
> mbigen irq domain into irq hierarchy structure.
>
> Signed-off-by: Ma Jun <majun258@huawei.com>
> ---
> drivers/irqchip/irq-mbigen-v1.c | 136 +++++++++++++++++++++++++++++++++++++++
> 1 files changed, 136 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mbigen-v1.c b/drivers/irqchip/irq-mbigen-v1.c
> index 9445658..61e7ad0 100644
> --- a/drivers/irqchip/irq-mbigen-v1.c
> +++ b/drivers/irqchip/irq-mbigen-v1.c
> @@ -16,11 +16,30 @@
> * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +#include <linux/interrupt.h>
> +#include <linux/irqchip.h>
> #include <linux/module.h>
> +#include <linux/msi.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/slab.h>
>
> +/* The maximum IRQ pin number of mbigen chip(start from 0) */
> +#define MAXIMUM_IRQ_PIN_NUM 640
> +
> +/**
> + * In mbigen vector register
> + * bit[31:16]: device id
> + * bit[15:0]: event id value
> + */
> +#define IRQ_EVENT_ID_MASK 0xffff
> +
> +/* offset of vector register in mbigen node */
> +#define REG_MBIGEN_VEC_OFFSET 0x300
> +#define REG_MBIGEN_EXT_VEC_OFFSET 0x320
> +
> /**
> * struct mbigen_device - holds the information of mbigen device.
> *
> @@ -32,10 +51,112 @@ struct mbigen_device {
> void __iomem *base;
> };
>
> +static int get_mbigen_nid(unsigned int offset)
> +{
> + int nid = 0;
> +
> + if (offset < 256)
> + nid = offset / 64;
> + else if (offset < 384)
> + nid = 4;
> + else if (offset < 640)
> + nid = 5;
> +
> + return nid;
> +}
> +
> +static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
> +{
> + unsigned int nid;
> +
> + nid = get_mbigen_nid(hwirq);
> +
> + if (nid < 4)
> + return (nid * 4) + REG_MBIGEN_VEC_OFFSET;
> + else
> + return (nid - 4) * 4 + REG_MBIGEN_EXT_VEC_OFFSET;
> +}
> +
> +static struct irq_chip mbigen_irq_chip = {
> + .name = "mbigen-v1",
> +};
> +
> +static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
> +{
> + /* The address of doorbell is encoded in mbigen register by default
> + * So,we don't need to program the doorbell address at here
> + * Besides, the event ID is decided by the hardware pin number,
> + * we can't change it in software.So, we don't need to encode the
> + * event ID in mbigen register.
> + */
Really? What if tomorrow I decide to change the EventID allocation
policy in the ITS driver? Have your HW engineers really baked the
behaviour of the Linux driver into the device?
I'm puzzled.
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 4/5] irqchip:create irq domain for each mbigen device
2016-02-16 8:50 ` Marc Zyngier
@ 2016-02-17 4:18 ` majun (F)
2016-02-17 7:47 ` Marc Zyngier
0 siblings, 1 reply; 9+ messages in thread
From: majun (F) @ 2016-02-17 4:18 UTC (permalink / raw)
To: linux-arm-kernel
? 2016/2/16 16:50, Marc Zyngier ??:
> On Tue, 16 Feb 2016 14:37:27 +0800
> MaJun <majun258@huawei.com> wrote:
>
>> From: Ma Jun <majun258@huawei.com>
[...]
>> + unsigned int nid;
>> +
>> + nid = get_mbigen_nid(hwirq);
>> +
>> + if (nid < 4)
>> + return (nid * 4) + REG_MBIGEN_VEC_OFFSET;
>> + else
>> + return (nid - 4) * 4 + REG_MBIGEN_EXT_VEC_OFFSET;
>> +}
>> +
>> +static struct irq_chip mbigen_irq_chip = {
>> + .name = "mbigen-v1",
>> +};
>> +
>> +static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
>> +{
>> + /* The address of doorbell is encoded in mbigen register by default
>> + * So,we don't need to program the doorbell address at here
>> + * Besides, the event ID is decided by the hardware pin number,
>> + * we can't change it in software.So, we don't need to encode the
>> + * event ID in mbigen register.
>> + */
>
> Really? What if tomorrow I decide to change the EventID allocation
> policy in the ITS driver? Have your HW engineers really baked the
> behaviour of the Linux driver into the device?
>
Yes.
If we really need to support this chip,is there
any possible solution for this problem?
Thanks!
MaJun
> I'm puzzled.
>
> M.
>
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH v2 4/5] irqchip:create irq domain for each mbigen device
2016-02-17 4:18 ` majun (F)
@ 2016-02-17 7:47 ` Marc Zyngier
0 siblings, 0 replies; 9+ messages in thread
From: Marc Zyngier @ 2016-02-17 7:47 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 17 Feb 2016 12:18:52 +0800
"majun (F)" <majun258@huawei.com> wrote:
>
>
> ? 2016/2/16 16:50, Marc Zyngier ??:
> > On Tue, 16 Feb 2016 14:37:27 +0800
> > MaJun <majun258@huawei.com> wrote:
> >
> >> From: Ma Jun <majun258@huawei.com>
> [...]
> >> + unsigned int nid;
> >> +
> >> + nid = get_mbigen_nid(hwirq);
> >> +
> >> + if (nid < 4)
> >> + return (nid * 4) + REG_MBIGEN_VEC_OFFSET;
> >> + else
> >> + return (nid - 4) * 4 + REG_MBIGEN_EXT_VEC_OFFSET;
> >> +}
> >> +
> >> +static struct irq_chip mbigen_irq_chip = {
> >> + .name = "mbigen-v1",
> >> +};
> >> +
> >> +static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
> >> +{
> >> + /* The address of doorbell is encoded in mbigen register by default
> >> + * So,we don't need to program the doorbell address at here
> >> + * Besides, the event ID is decided by the hardware pin number,
> >> + * we can't change it in software.So, we don't need to encode the
> >> + * event ID in mbigen register.
> >> + */
> >
> > Really? What if tomorrow I decide to change the EventID allocation
> > policy in the ITS driver? Have your HW engineers really baked the
> > behaviour of the Linux driver into the device?
> >
>
> Yes.
> If we really need to support this chip,is there
> any possible solution for this problem?
You would have to provide some sort of lookup table from the
device-tree, or find a way to pass this information down the ITS code.
The real question is: do we take this as it is and fix it once it
breaks? or do we mandate a proper solution before this has a remote
chance of getting in?
At the moment, I don't know, because the idea of hardcoded MSIs is so
wrong and so against the way the whole stack works that I just want to
say no to this and run away.
I need to think.
M.
--
Jazz is not dead. It just smells funny.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 5/5] irqchip:implement the mbigen irq chip operation functions
2016-02-16 6:37 [PATCH v2 0/5] irqchip: Add support for Hisilicon mbigen v1 chip MaJun
` (3 preceding siblings ...)
2016-02-16 6:37 ` [PATCH v2 4/5] irqchip:create irq domain for each " MaJun
@ 2016-02-16 6:37 ` MaJun
4 siblings, 0 replies; 9+ messages in thread
From: MaJun @ 2016-02-16 6:37 UTC (permalink / raw)
To: linux-arm-kernel
From: Ma Jun <majun258@huawei.com>
Add the interrupt controller chip operation functions of mbigen chip.
Signed-off-by: Ma Jun <majun258@huawei.com>
---
drivers/irqchip/irq-mbigen-v1.c | 75 +++++++++++++++++++++++++++++++++++++++
1 files changed, 75 insertions(+), 0 deletions(-)
diff --git a/drivers/irqchip/irq-mbigen-v1.c b/drivers/irqchip/irq-mbigen-v1.c
index 61e7ad0..0636165 100644
--- a/drivers/irqchip/irq-mbigen-v1.c
+++ b/drivers/irqchip/irq-mbigen-v1.c
@@ -41,6 +41,20 @@
#define REG_MBIGEN_EXT_VEC_OFFSET 0x320
/**
+ * offset of clear register in mbigen node
+ * This register is used to clear the status
+ * of interrupt
+ */
+#define REG_MBIGEN_CLEAR_OFFSET 0x100
+
+/**
+ * offset of interrupt type register
+ * This register is used to configure interrupt
+ * trigger type
+ */
+#define REG_MBIGEN_TYPE_OFFSET 0x0
+
+/**
* struct mbigen_device - holds the information of mbigen device.
*
* @pdev: pointer to the platform device structure of mbigen chip.
@@ -77,8 +91,69 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
return (nid - 4) * 4 + REG_MBIGEN_EXT_VEC_OFFSET;
}
+static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
+ u32 *mask, u32 *addr)
+{
+ int ofst;
+
+ ofst = hwirq / 32 * 4;
+ *mask = 1 << (hwirq % 32);
+
+ *addr = ofst + REG_MBIGEN_TYPE_OFFSET;
+}
+
+static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
+ u32 *mask, u32 *addr)
+{
+ unsigned int ofst;
+
+ ofst = hwirq / 32 * 4;
+
+ *mask = 1 << (hwirq % 32);
+ *addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
+}
+
+static void mbigen_eoi_irq(struct irq_data *data)
+{
+ void __iomem *base = data->chip_data;
+ u32 mask, addr;
+
+ get_mbigen_clear_reg(data->hwirq, &mask, &addr);
+
+ writel_relaxed(mask, base + addr);
+
+ irq_chip_eoi_parent(data);
+}
+
+static int mbigen_set_type(struct irq_data *data, unsigned int type)
+{
+ void __iomem *base = data->chip_data;
+ u32 mask, addr, val;
+
+ if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+ return -EINVAL;
+
+ get_mbigen_type_reg(data->hwirq, &mask, &addr);
+
+ val = readl_relaxed(base + addr);
+
+ if (type == IRQ_TYPE_LEVEL_HIGH)
+ val |= mask;
+ else
+ val &= ~mask;
+
+ writel_relaxed(val, base + addr);
+
+ return 0;
+}
+
static struct irq_chip mbigen_irq_chip = {
.name = "mbigen-v1",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = mbigen_eoi_irq,
+ .irq_set_type = mbigen_set_type,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
};
static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread