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* [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files
@ 2016-02-26 11:44 Lothar Waßmann
  2016-02-26 14:52 ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Lothar Waßmann
  2016-02-26 17:31 ` [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files Zhi Li
  0 siblings, 2 replies; 5+ messages in thread
From: Lothar Waßmann @ 2016-02-26 11:44 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

after finding a bug in the imx6ul-pinconf.h file (missing input_sel
config for MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO), I decided
to write a perl script (see attachment) to check the file for
consistency and found 44 more errors in the same file.

Running the script over the remaining imx pinconf files revealed the
following errors:
arch/arm/boot/dts/imx35-pinfunc.h:
----------------------------------
ERROR: Missing INPUT_SEL address for FUNCTION 'KPP_ROW_3' on PAD 'MX35_PAD_CSI_D15',
        other pads for this function are:
        MX35_PAD_FST             0x097c 0x1
        MX35_PAD_ATA_BUFF_EN     0x097c 0x2
ERROR: Missing INPUT_SEL address for FUNCTION 'AUDMUX_AUD6_RXC' on PAD 'MX35_PAD_FEC_RDATA1',
        other pads for this function are:
        MX35_PAD_ATA_DATA10      0x07b8 0x0
ERROR: Missing INPUT_SEL address for FUNCTION 'AUDMUX_AUD5_RXC' on PAD 'MX35_PAD_RTS2',
        other pads for this function are:
        MX35_PAD_HCKT            0x07a8 0x0
arch/arm/boot/dts/imx35-pinfunc.h: 952 pads checked: 3 errors found

arch/arm/boot/dts/imx50-pinfunc.h:
----------------------------------
ERROR: Missing INPUT_SEL address for FUNCTION 'UART3_CTS' on PAD 'MX50_PAD_ECSPI1_MOSI',
        other pads for this function are:
        MX50_PAD_UART4_TXD       0x07d0 0x0
ERROR: Duplicate MUX reg addr 0x01f8 for pad 'MX50_PAD_EPDC_GDRL' and 'MX50_PAD_EPDC_GDOE'
ERROR: Duplicate INPUT_SEL value 0x0 for FUNC 'ELCDIF_DAT_4' on pad 'MX50_PAD_EPDC_SDCE1'
        pads for this function are:
        MX50_PAD_DISP_D4         0x070c 0x0
        MX50_PAD_EPDC_SDCE1      0x070c 0x0
arch/arm/boot/dts/imx50-pinfunc.h: 905 pads checked: 3 errors found

arch/arm/boot/dts/imx51-pinfunc.h:
----------------------------------
ERROR: Missing INPUT_SEL address for FUNCTION 'DISP1_EXT_CLK' on PAD 'MX51_PAD_DISPB2_SER_RS',
        other pads for this function are:
        MX51_PAD_EIM_CS5         0x0904 0x0
ERROR: Duplicate MUX value 0x2 for FUNC 'DISP1_EXT_CLK' and 'DISP1_PIN16' on PAD 'MX51_PAD_DISPB2_SER_RS'
arch/arm/boot/dts/imx51-pinfunc.h: 755 pads checked: 1 errors found

arch/arm/boot/dts/imx7d-pinfunc.h:
----------------------------------
ERROR: Missing INPUT_SEL address for FUNCTION 'KPP_COL1' on PAD 'MX7D_PAD_ENET1_RGMII_RXC',
        other pads for this function are:
        MX7D_PAD_EPDC_DATA05     0x05f8 0x0
ERROR: Missing INPUT_SEL address for FUNCTION 'SAI1_RX_BCLK' on PAD 'MX7D_PAD_ENET1_RGMII_TXC',
        other pads for this function are:
        MX7D_PAD_SAI1_RX_BCLK    0x069c 0x0
ERROR: Missing INPUT_SEL address for FUNCTION 'SAI1_RX_SYNC' on PAD 'MX7D_PAD_ENET1_RGMII_TX_CTL',
        other pads for this function are:
        MX7D_PAD_SAI1_RX_SYNC    0x06a4 0x0
ERROR: Duplicate MUX reg addr 0x0014 for pad 'MX7D_PAD_GPIO1_IO08' and 'MX7D_PAD_GPIO1_IO05'
ERROR: Duplicate MUX reg addr 0x0018 for pad 'MX7D_PAD_GPIO1_IO09' and 'MX7D_PAD_GPIO1_IO06'
ERROR: Duplicate MUX reg addr 0x001c for pad 'MX7D_PAD_GPIO1_IO10' and 'MX7D_PAD_GPIO1_IO07'
ERROR: Missing INPUT_SEL address for FUNCTION 'CCM_PMIC_READY' on PAD 'MX7D_PAD_UART1_RX_DATA',
        other pads for this function are:
        MX7D_PAD_GPIO1_IO09      0x04f4 0x0
        MX7D_PAD_GPIO1_IO13      0x04f4 0x1
        MX7D_PAD_SAI1_MCLK       0x04f4 0x3
ERROR: Missing INPUT_SEL address for FUNCTION 'ENET1_MDIO' on PAD 'MX7D_PAD_UART1_RX_DATA',
        other pads for this function are:
        MX7D_PAD_GPIO1_IO10      0x0568 0x0
        MX7D_PAD_SD2_CD_B        0x0568 0x2
ERROR: Missing INPUT_SEL address for FUNCTION 'SAI3_RX_BCLK' on PAD 'MX7D_PAD_UART2_RX_DATA',
        other pads for this function are:
        MX7D_PAD_SD1_CMD         0x06c4 0x1
        MX7D_PAD_SD3_CMD         0x06c4 0x2
ERROR: Missing INPUT_SEL address for FUNCTION 'ENET2_MDIO' on PAD 'MX7D_PAD_UART2_RX_DATA',
        other pads for this function are:
        MX7D_PAD_GPIO1_IO14      0x0574 0x0
        MX7D_PAD_SD2_CD_B        0x0574 0x2
ERROR: Missing INPUT_SEL address for FUNCTION 'UART2_DTE_RX' on PAD 'MX7D_PAD_UART2_TX_DATA',
        other pads for this function are:
        MX7D_PAD_LCD_ENABLE      0x06fc 0x1
ERROR: Missing INPUT_SEL address for FUNCTION 'ECSPI1_SCLK' on PAD 'MX7D_PAD_UART3_RTS_B',
        other pads for this function are:
        MX7D_PAD_ECSPI1_SCLK     0x0524 0x1
arch/arm/boot/dts/imx7d-pinfunc.h: 1135 pads checked: 12 errors found


I will send a patch for imx6ul and imx51 shortly.
But I have no resources to correct the bugs in the imx35, imx50 and
imx7d files.
The "Duplicate MUX reg addr" message for imx7d are false positives due
to the deviant nature of the imx7d pinctrl design, but the other
messages should be relevant.



Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
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www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
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^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h
  2016-02-26 11:44 [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files Lothar Waßmann
@ 2016-02-26 14:52 ` Lothar Waßmann
  2016-02-26 14:52   ` [PATCH 2/2] ARM: dts: imx6ul: add missing input_sel config for various pins Lothar Waßmann
  2016-02-28  3:08   ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Shawn Guo
  2016-02-26 17:31 ` [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files Zhi Li
  1 sibling, 2 replies; 5+ messages in thread
From: Lothar Waßmann @ 2016-02-26 14:52 UTC (permalink / raw)
  To: linux-arm-kernel

This patchset adds missing input_sel settings to imx6ul-pinfunc.h.
The first patch is a cleanup patch with no functional changes
intended.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/2] ARM: dts: imx6ul: add missing input_sel config for various pins
  2016-02-26 14:52 ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Lothar Waßmann
@ 2016-02-26 14:52   ` Lothar Waßmann
  2016-02-28  3:08   ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Shawn Guo
  1 sibling, 0 replies; 5+ messages in thread
From: Lothar Waßmann @ 2016-02-26 14:52 UTC (permalink / raw)
  To: linux-arm-kernel

Various pads are missing the input_sel offset and value. Fix this.

Signed-off-by: Lothar Wa?mann <LW@KARO-electronics.de>
---
 arch/arm/boot/dts/imx6ul-pinfunc.h | 90 +++++++++++++++++++-------------------
 1 file changed, 45 insertions(+), 45 deletions(-)

diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h
index c00d230..0034eeb 100644
--- a/arch/arm/boot/dts/imx6ul-pinfunc.h
+++ b/arch/arm/boot/dts/imx6ul-pinfunc.h
@@ -60,7 +60,7 @@
 #define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL		0x0050 0x02dc 0x0000 8 0
 #define MX6UL_PAD_JTAG_TCK__SJC_TCK			0x0054 0x02e0 0x0000 0 0
 #define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2		0x0054 0x02e0 0x0000 1 0
-#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA		0x0054 0x02e0 0x0000 2 0
+#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA		0x0054 0x02e0 0x05f4 2 0
 #define MX6UL_PAD_JTAG_TCK__PWM7_OUT			0x0054 0x02e0 0x0000 4 0
 #define MX6UL_PAD_JTAG_TCK__GPIO1_IO14			0x0054 0x02e0 0x0000 5 0
 #define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL		0x0054 0x02e0 0x0000 8 0
@@ -165,7 +165,7 @@
 #define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX		0x0084 0x0310 0x0624 0 2
 #define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02		0x0084 0x0310 0x0000 1 0
 #define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL		0x0084 0x0310 0x05b4 2 0
-#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02		0x0084 0x0310 0x0000 3 0
+#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02		0x0084 0x0310 0x04c4 3 1
 #define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1		0x0084 0x0310 0x0000 4 0
 #define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16		0x0084 0x0310 0x0000 5 0
 #define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT		0x0084 0x0310 0x0000 8 0
@@ -173,31 +173,31 @@
 #define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX		0x0088 0x0314 0x0000 0 0
 #define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03		0x0088 0x0314 0x0000 1 0
 #define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA		0x0088 0x0314 0x05b8 2 0
-#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03		0x0088 0x0314 0x0000 3 0
+#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03		0x0088 0x0314 0x04c8 3 1
 #define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK		0x0088 0x0314 0x0594 4 0
 #define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17		0x0088 0x0314 0x0000 5 0
-#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN		0x0088 0x0314 0x0000 8 0
+#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN		0x0088 0x0314 0x0618 8 1
 #define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS		0x008c 0x0318 0x0000 0 0
 #define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS		0x008c 0x0318 0x0620 0 2
 #define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK		0x008c 0x0318 0x0000 1 0
 #define MX6UL_PAD_UART1_CTS_B__USDHC1_WP		0x008c 0x0318 0x066c 2 1
-#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04		0x008c 0x0318 0x0000 3 0
+#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04		0x008c 0x0318 0x04d8 3 0
 #define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN	0x008c 0x0318 0x0000 4 0
 #define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18		0x008c 0x0318 0x0000 5 0
-#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP		0x008c 0x0318 0x0000 8 0
+#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP		0x008c 0x0318 0x069c 8 1
 #define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS		0x0090 0x031c 0x0620 0 3
 #define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS		0x0090 0x031c 0x0000 0 0
 #define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER		0x0090 0x031c 0x0000 1 0
 #define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B		0x0090 0x031c 0x0668 2 1
-#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05		0x0090 0x031c 0x0000 3 0
+#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05		0x0090 0x031c 0x04cc 3 1
 #define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT	0x0090 0x031c 0x0000 4 0
 #define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19		0x0090 0x031c 0x0000 5 0
-#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B		0x0090 0x031c 0x0000 8 0
+#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B		0x0090 0x031c 0x0674 8 2
 #define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX		0x0094 0x0320 0x0000 0 0
 #define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX		0x0094 0x0320 0x062c 0 0
 #define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02		0x0094 0x0320 0x0000 1 0
 #define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL		0x0094 0x0320 0x05bc 2 0
-#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06		0x0094 0x0320 0x0000 3 0
+#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06		0x0094 0x0320 0x04dc 3 0
 #define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1		0x0094 0x0320 0x058c 4 1
 #define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20		0x0094 0x0320 0x0000 5 0
 #define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0		0x0094 0x0320 0x0000 8 0
@@ -205,29 +205,29 @@
 #define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX		0x0098 0x0324 0x0000 0 0
 #define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03		0x0098 0x0324 0x0000 1 0
 #define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA		0x0098 0x0324 0x05c0 2 0
-#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07		0x0098 0x0324 0x0000 3 0
+#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07		0x0098 0x0324 0x04e0 3 0
 #define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2		0x0098 0x0324 0x0590 4 0
 #define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21		0x0098 0x0324 0x0000 5 0
 #define MX6UL_PAD_UART2_RX_DATA__SJC_DONE		0x0098 0x0324 0x0000 7 0
-#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK		0x0098 0x0324 0x0000 8 0
+#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK		0x0098 0x0324 0x0554 8 0
 #define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS		0x009c 0x0328 0x0000 0 0
 #define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS		0x009c 0x0328 0x0628 0 0
 #define MX6UL_PAD_UART2_CTS_B__ENET1_CRS		0x009c 0x0328 0x0000 1 0
 #define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX		0x009c 0x0328 0x0000 2 0
-#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08		0x009c 0x0328 0x0000 3 0
+#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08		0x009c 0x0328 0x04e4 3 0
 #define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2		0x009c 0x0328 0x0000 4 0
 #define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22		0x009c 0x0328 0x0000 5 0
 #define MX6UL_PAD_UART2_CTS_B__SJC_DE_B			0x009c 0x0328 0x0000 7 0
-#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI		0x009c 0x0328 0x0000 8 0
+#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI		0x009c 0x0328 0x055c 8 0
 #define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS		0x00a0 0x032c 0x0628 0 1
 #define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS		0x00a0 0x032c 0x0000 0 0
 #define MX6UL_PAD_UART2_RTS_B__ENET1_COL		0x00a0 0x032c 0x0000 1 0
 #define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX		0x00a0 0x032c 0x0588 2 0
-#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09		0x00a0 0x032c 0x0000 3 0
+#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09		0x00a0 0x032c 0x04e8 3 0
 #define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3		0x00a0 0x032c 0x0000 4 0
 #define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23		0x00a0 0x032c 0x0000 5 0
 #define MX6UL_PAD_UART2_RTS_B__SJC_FAIL			0x00a0 0x032c 0x0000 7 0
-#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO		0x00a0 0x032c 0x0000 8 0
+#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO		0x00a0 0x032c 0x0558 8 0
 #define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX		0x00a4 0x0330 0x0000 0 0
 #define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX		0x00a4 0x0330 0x0634 0 0
 #define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02		0x00a4 0x0330 0x0000 1 0
@@ -237,7 +237,7 @@
 #define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS		0x00a4 0x0330 0x0628 4 2
 #define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24		0x00a4 0x0330 0x0000 5 0
 #define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT		0x00a4 0x0330 0x0000 7 0
-#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID		0x00a4 0x0330 0x0000 8 0
+#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID		0x00a4 0x0330 0x04b8 8 1
 #define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX		0x00a8 0x0334 0x0634 0 1
 #define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX		0x00a8 0x0334 0x0000 0 0
 #define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03		0x00a8 0x0334 0x0000 1 0
@@ -270,7 +270,7 @@
 #define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12		0x00b4 0x0340 0x0000 3 0
 #define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02	0x00b4 0x0340 0x0000 4 0
 #define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28		0x00b4 0x0340 0x0000 5 0
-#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK		0x00b4 0x0340 0x0000 8 0
+#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK		0x00b4 0x0340 0x0544 8 1
 #define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX		0x00b8 0x0344 0x063c 0 1
 #define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX		0x00b8 0x0344 0x0000 0 0
 #define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03		0x00b8 0x0344 0x0000 1 0
@@ -280,7 +280,7 @@
 #define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29		0x00b8 0x0344 0x0000 5 0
 #define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0		0x00b8 0x0344 0x0000 8 0
 #define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30		0x00bc 0x0348 0x0000 5 0
-#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI		0x00bc 0x0348 0x0000 8 0
+#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI		0x00bc 0x0348 0x054c 8 0
 #define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX		0x00bc 0x0348 0x0000 0 0
 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX		0x00bc 0x0348 0x0644 0 4
 #define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS		0x00bc 0x0348 0x0000 1 0
@@ -294,7 +294,7 @@
 #define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15		0x00c0 0x034c 0x0000 3 0
 #define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB	0x00c0 0x034c 0x0000 4 0
 #define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31		0x00c0 0x034c 0x0000 5 0
-#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO		0x00c0 0x034c 0x0000 8 0
+#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO		0x00c0 0x034c 0x0548 8 1
 #define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00		0x00c4 0x0350 0x0000 0 0
 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS		0x00c4 0x0350 0x0638 1 0
 #define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS		0x00c4 0x0350 0x0000 1 0
@@ -355,7 +355,7 @@
 #define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1		0x00dc 0x0368 0x0574 4 2
 #define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06		0x00dc 0x0368 0x0000 5 0
 #define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03		0x00dc 0x0368 0x0000 6 0
-#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK		0x00dc 0x0368 0x0000 8 0
+#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK		0x00dc 0x0368 0x0594 8 1
 #define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER		0x00e0 0x036c 0x0000 0 0
 #define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS		0x00e0 0x036c 0x0650 1 1
 #define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS		0x00e0 0x036c 0x0000 1 0
@@ -364,7 +364,7 @@
 #define MX6UL_PAD_ENET1_RX_ER__EIM_CRE			0x00e0 0x036c 0x0000 4 0
 #define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07		0x00e0 0x036c 0x0000 5 0
 #define MX6UL_PAD_ENET1_RX_ER__KPP_COL03		0x00e0 0x036c 0x0000 6 0
-#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2		0x00e0 0x036c 0x0000 8 0
+#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2		0x00e0 0x036c 0x0590 8 1
 #define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00		0x00e4 0x0370 0x0000 0 0
 #define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX		0x00e4 0x0370 0x0000 1 0
 #define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX		0x00e4 0x0370 0x064c 1 1
@@ -382,7 +382,7 @@
 #define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC		0x00e8 0x0374 0x0000 4 0
 #define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09		0x00e8 0x0374 0x0000 5 0
 #define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04		0x00e8 0x0374 0x0000 6 0
-#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC		0x00e8 0x0374 0x0000 8 0
+#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC		0x00e8 0x0374 0x0664 8 1
 #define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN		0x00ec 0x0378 0x0000 0 0
 #define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX		0x00ec 0x0378 0x0000 1 0
 #define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX		0x00ec 0x0378 0x0654 1 0
@@ -417,7 +417,7 @@
 #define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN		0x00f8 0x0384 0x0000 4 0
 #define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13		0x00f8 0x0384 0x0000 5 0
 #define MX6UL_PAD_ENET2_TX_EN__KPP_COL06		0x00f8 0x0384 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC		0x00f8 0x0384 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC		0x00f8 0x0384 0x0660 8 1
 #define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK		0x00fc 0x0388 0x0000 0 0
 #define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS		0x00fc 0x0388 0x0000 1 0
 #define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS		0x00fc 0x0388 0x0658 1 0
@@ -426,7 +426,7 @@
 #define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2		0x00fc 0x0388 0x057c 4 2
 #define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14		0x00fc 0x0388 0x0000 5 0
 #define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07		0x00fc 0x0388 0x0000 6 0
-#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID		0x00fc 0x0388 0x0000 8 0
+#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID		0x00fc 0x0388 0x04bc 8 1
 #define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER		0x0100 0x038c 0x0000 0 0
 #define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS		0x0100 0x038c 0x0658 1 1
 #define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS		0x0100 0x038c 0x0000 1 0
@@ -488,14 +488,14 @@
 #define MX6UL_PAD_LCD_DATA01__I2C3_SCL			0x011c 0x03a8 0x05b4 4 2
 #define MX6UL_PAD_LCD_DATA01__GPIO3_IO06		0x011c 0x03a8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01		0x011c 0x03a8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC		0x011c 0x03a8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC		0x011c 0x03a8 0x05ec 8 0
 #define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02		0x0120 0x03ac 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA02__PWM3_OUT			0x0120 0x03ac 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN	0x0120 0x03ac 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA02__I2C4_SDA			0x0120 0x03ac 0x05c0 4 2
 #define MX6UL_PAD_LCD_DATA02__GPIO3_IO07		0x0120 0x03ac 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02		0x0120 0x03ac 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK		0x0120 0x03ac 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK		0x0120 0x03ac 0x05e8 8 0
 #define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03		0x0124 0x03b0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA03__PWM4_OUT			0x0124 0x03b0 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT	0x0124 0x03b0 0x0000 3 0
@@ -548,7 +548,7 @@
 #define MX6UL_PAD_LCD_DATA09__EIM_DATA01		0x013c 0x03c8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA09__GPIO3_IO14		0x013c 0x03c8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09		0x013c 0x03c8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX		0x013c 0x03c8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX		0x013c 0x03c8 0x0584 8 2
 #define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10		0x0140 0x03cc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC		0x0140 0x03cc 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA10__CSI_DATA18		0x0140 0x03cc 0x0000 3 0
@@ -562,7 +562,7 @@
 #define MX6UL_PAD_LCD_DATA11__EIM_DATA03		0x0144 0x03d0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA11__GPIO3_IO16		0x0144 0x03d0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11		0x0144 0x03d0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX		0x0144 0x03d0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX		0x0144 0x03d0 0x0588 8 2
 #define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12		0x0148 0x03d4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC		0x0148 0x03d4 0x060c 1 1
 #define MX6UL_PAD_LCD_DATA12__CSI_DATA20		0x0148 0x03d4 0x0000 3 0
@@ -583,14 +583,14 @@
 #define MX6UL_PAD_LCD_DATA14__EIM_DATA06		0x0150 0x03dc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA14__GPIO3_IO19		0x0150 0x03dc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14		0x0150 0x03dc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4		0x0150 0x03dc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4		0x0150 0x03dc 0x068c 8 0
 #define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15		0x0154 0x03e0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA		0x0154 0x03e0 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA15__CSI_DATA23		0x0154 0x03e0 0x0000 3 0
 #define MX6UL_PAD_LCD_DATA15__EIM_DATA07		0x0154 0x03e0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA15__GPIO3_IO20		0x0154 0x03e0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15		0x0154 0x03e0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5		0x0154 0x03e0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5		0x0154 0x03e0 0x0690 8 0
 #define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16		0x0158 0x03e4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX		0x0158 0x03e4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX		0x0158 0x03e4 0x0654 1 2
@@ -598,7 +598,7 @@
 #define MX6UL_PAD_LCD_DATA16__EIM_DATA08		0x0158 0x03e4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA16__GPIO3_IO21		0x0158 0x03e4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24		0x0158 0x03e4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6		0x0158 0x03e4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6		0x0158 0x03e4 0x0694 8 0
 #define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17		0x015c 0x03e8 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX		0x015c 0x03e8 0x0654 1 3
 #define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX		0x015c 0x03e8 0x0000 1 0
@@ -606,7 +606,7 @@
 #define MX6UL_PAD_LCD_DATA17__EIM_DATA09		0x015c 0x03e8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA17__GPIO3_IO22		0x015c 0x03e8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25		0x015c 0x03e8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7		0x015c 0x03e8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7		0x015c 0x03e8 0x0698 8 0
 #define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18		0x0160 0x03ec 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA18__PWM5_OUT			0x0160 0x03ec 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO		0x0160 0x03ec 0x0000 2 0
@@ -614,11 +614,11 @@
 #define MX6UL_PAD_LCD_DATA18__EIM_DATA10		0x0160 0x03ec 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA18__GPIO3_IO23		0x0160 0x03ec 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26		0x0160 0x03ec 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD		0x0160 0x03ec 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD		0x0160 0x03ec 0x0678 8 1
 #define MX6UL_PAD_LCD_DATA19__EIM_DATA11		0x0164 0x03f0 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA19__GPIO3_IO24		0x0164 0x03f0 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27		0x0164 0x03f0 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK		0x0164 0x03f0 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK		0x0164 0x03f0 0x0670 8 1
 #define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19		0x0164 0x03f0 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA19__PWM6_OUT			0x0164 0x03f0 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY		0x0164 0x03f0 0x0000 2 0
@@ -626,7 +626,7 @@
 #define MX6UL_PAD_LCD_DATA20__EIM_DATA12		0x0168 0x03f4 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA20__GPIO3_IO25		0x0168 0x03f4 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28		0x0168 0x03f4 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0		0x0168 0x03f4 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0		0x0168 0x03f4 0x067c 8 1
 #define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20		0x0168 0x03f4 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX		0x0168 0x03f4 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX		0x0168 0x03f4 0x065c 1 2
@@ -640,7 +640,7 @@
 #define MX6UL_PAD_LCD_DATA21__EIM_DATA13		0x016c 0x03f8 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA21__GPIO3_IO26		0x016c 0x03f8 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29		0x016c 0x03f8 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1		0x016c 0x03f8 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1		0x016c 0x03f8 0x0680 8 1
 #define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22		0x0170 0x03fc 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA22__MQS_RIGHT			0x0170 0x03fc 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI		0x0170 0x03fc 0x053c 2 0
@@ -648,7 +648,7 @@
 #define MX6UL_PAD_LCD_DATA22__EIM_DATA14		0x0170 0x03fc 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA22__GPIO3_IO27		0x0170 0x03fc 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30		0x0170 0x03fc 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2		0x0170 0x03fc 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2		0x0170 0x03fc 0x0684 8 0
 #define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23		0x0174 0x0400 0x0000 0 0
 #define MX6UL_PAD_LCD_DATA23__MQS_LEFT			0x0174 0x0400 0x0000 1 0
 #define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO		0x0174 0x0400 0x0538 2 0
@@ -656,7 +656,7 @@
 #define MX6UL_PAD_LCD_DATA23__EIM_DATA15		0x0174 0x0400 0x0000 4 0
 #define MX6UL_PAD_LCD_DATA23__GPIO3_IO28		0x0174 0x0400 0x0000 5 0
 #define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31		0x0174 0x0400 0x0000 6 0
-#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3		0x0174 0x0400 0x0000 8 0
+#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3		0x0174 0x0400 0x0688 8 1
 #define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B		0x0178 0x0404 0x0000 0 0
 #define MX6UL_PAD_NAND_RE_B__USDHC2_CLK			0x0178 0x0404 0x0670 1 2
 #define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK		0x0178 0x0404 0x0000 2 0
@@ -784,7 +784,7 @@
 #define MX6UL_PAD_NAND_DQS__EIM_WAIT			0x01b8 0x0444 0x0000 4 0
 #define MX6UL_PAD_NAND_DQS__GPIO4_IO16			0x01b8 0x0444 0x0000 5 0
 #define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01		0x01b8 0x0444 0x0000 6 0
-#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK		0x01b8 0x0444 0x0000 8 0
+#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK		0x01b8 0x0444 0x061c 8 1
 #define MX6UL_PAD_SD1_CMD__USDHC1_CMD			0x01bc 0x0448 0x0000 0 0
 #define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1		0x01bc 0x0448 0x0000 1 0
 #define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC			0x01bc 0x0448 0x0000 2 0
@@ -799,14 +799,14 @@
 #define MX6UL_PAD_SD1_CLK__SPDIF_IN			0x01c0 0x044c 0x0618 3 3
 #define MX6UL_PAD_SD1_CLK__EIM_ADDR20			0x01c0 0x044c 0x0000 4 0
 #define MX6UL_PAD_SD1_CLK__GPIO2_IO17			0x01c0 0x044c 0x0000 5 0
-#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC			0x01c0 0x044c 0x0000 8 0
+#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC			0x01c0 0x044c 0x0664 8 2
 #define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0		0x01c4 0x0450 0x0000 0 0
 #define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3		0x01c4 0x0450 0x0000 1 0
 #define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC		0x01c4 0x0450 0x05fc 2 1
 #define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX		0x01c4 0x0450 0x0000 3 0
 #define MX6UL_PAD_SD1_DATA0__EIM_ADDR21			0x01c4 0x0450 0x0000 4 0
 #define MX6UL_PAD_SD1_DATA0__GPIO2_IO18			0x01c4 0x0450 0x0000 5 0
-#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID		0x01c4 0x0450 0x0000 8 0
+#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID		0x01c4 0x0450 0x04b8 8 2
 #define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1		0x01c8 0x0454 0x0000 0 0
 #define MX6UL_PAD_SD1_DATA1__GPT2_CLK			0x01c8 0x0454 0x05a0 1 1
 #define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK		0x01c8 0x0454 0x05f8 2 1
@@ -821,7 +821,7 @@
 #define MX6UL_PAD_SD1_DATA2__EIM_ADDR23			0x01cc 0x0458 0x0000 4 0
 #define MX6UL_PAD_SD1_DATA2__GPIO2_IO20			0x01cc 0x0458 0x0000 5 0
 #define MX6UL_PAD_SD1_DATA2__CCM_CLKO1			0x01cc 0x0458 0x0000 6 0
-#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC		0x01cc 0x0458 0x0000 8 0
+#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC		0x01cc 0x0458 0x0660 8 2
 #define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3		0x01d0 0x045c 0x0000 0 0
 #define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2		0x01d0 0x045c 0x059c 1 1
 #define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA		0x01d0 0x045c 0x0000 2 0
@@ -829,7 +829,7 @@
 #define MX6UL_PAD_SD1_DATA3__EIM_ADDR24			0x01d0 0x045c 0x0000 4 0
 #define MX6UL_PAD_SD1_DATA3__GPIO2_IO21			0x01d0 0x045c 0x0000 5 0
 #define MX6UL_PAD_SD1_DATA3__CCM_CLKO2			0x01d0 0x045c 0x0000 6 0
-#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID		0x01d0 0x045c 0x0000 8 0
+#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID		0x01d0 0x045c 0x04bc 8 2
 #define MX6UL_PAD_CSI_MCLK__CSI_MCLK			0x01d4 0x0460 0x0000 0 0
 #define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B			0x01d4 0x0460 0x0674 1 0
 #define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B		0x01d4 0x0460 0x0000 2 0
@@ -909,7 +909,7 @@
 #define MX6UL_PAD_CSI_DATA04__EIM_AD04			0x01f4 0x0480 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA04__GPIO4_IO25		0x01f4 0x0480 0x0000 5 0
 #define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC		0x01f4 0x0480 0x05ec 6 1
-#define MX6UL_PAD_CSI_DATA04__USDHC1_WP			0x01f4 0x0480 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA04__USDHC1_WP			0x01f4 0x0480 0x066c 8 2
 #define MX6UL_PAD_CSI_DATA05__CSI_DATA07		0x01f8 0x0484 0x04e0 0 1
 #define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5		0x01f8 0x0484 0x0690 1 2
 #define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B		0x01f8 0x0484 0x0000 2 0
@@ -917,7 +917,7 @@
 #define MX6UL_PAD_CSI_DATA05__EIM_AD05			0x01f8 0x0484 0x0000 4 0
 #define MX6UL_PAD_CSI_DATA05__GPIO4_IO26		0x01f8 0x0484 0x0000 5 0
 #define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK		0x01f8 0x0484 0x05e8 6 1
-#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B		0x01f8 0x0484 0x0000 8 0
+#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B		0x01f8 0x0484 0x0668 8 2
 #define MX6UL_PAD_CSI_DATA06__CSI_DATA08		0x01fc 0x0488 0x04e4 0 1
 #define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6		0x01fc 0x0488 0x0694 1 2
 #define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN		0x01fc 0x0488 0x0000 2 0
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files
  2016-02-26 11:44 [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files Lothar Waßmann
  2016-02-26 14:52 ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Lothar Waßmann
@ 2016-02-26 17:31 ` Zhi Li
  1 sibling, 0 replies; 5+ messages in thread
From: Zhi Li @ 2016-02-26 17:31 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Feb 26, 2016 at 5:44 AM, Lothar Wa?mann <LW@karo-electronics.de> wrote:
> Hi,
>
> after finding a bug in the imx6ul-pinconf.h file (missing input_sel
> config for MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO), I decided
> to write a perl script (see attachment) to check the file for
> consistency and found 44 more errors in the same file.
>
> Running the script over the remaining imx pinconf files revealed the
> following errors:
> arch/arm/boot/dts/imx35-pinfunc.h:
> ----------------------------------
> ERROR: Missing INPUT_SEL address for FUNCTION 'KPP_ROW_3' on PAD 'MX35_PAD_CSI_D15',
>         other pads for this function are:
>         MX35_PAD_FST             0x097c 0x1
>         MX35_PAD_ATA_BUFF_EN     0x097c 0x2
> ERROR: Missing INPUT_SEL address for FUNCTION 'AUDMUX_AUD6_RXC' on PAD 'MX35_PAD_FEC_RDATA1',
>         other pads for this function are:
>         MX35_PAD_ATA_DATA10      0x07b8 0x0
> ERROR: Missing INPUT_SEL address for FUNCTION 'AUDMUX_AUD5_RXC' on PAD 'MX35_PAD_RTS2',
>         other pads for this function are:
>         MX35_PAD_HCKT            0x07a8 0x0
> arch/arm/boot/dts/imx35-pinfunc.h: 952 pads checked: 3 errors found
>
> arch/arm/boot/dts/imx50-pinfunc.h:
> ----------------------------------
> ERROR: Missing INPUT_SEL address for FUNCTION 'UART3_CTS' on PAD 'MX50_PAD_ECSPI1_MOSI',
>         other pads for this function are:
>         MX50_PAD_UART4_TXD       0x07d0 0x0
> ERROR: Duplicate MUX reg addr 0x01f8 for pad 'MX50_PAD_EPDC_GDRL' and 'MX50_PAD_EPDC_GDOE'
> ERROR: Duplicate INPUT_SEL value 0x0 for FUNC 'ELCDIF_DAT_4' on pad 'MX50_PAD_EPDC_SDCE1'
>         pads for this function are:
>         MX50_PAD_DISP_D4         0x070c 0x0
>         MX50_PAD_EPDC_SDCE1      0x070c 0x0
> arch/arm/boot/dts/imx50-pinfunc.h: 905 pads checked: 3 errors found
>
> arch/arm/boot/dts/imx51-pinfunc.h:
> ----------------------------------
> ERROR: Missing INPUT_SEL address for FUNCTION 'DISP1_EXT_CLK' on PAD 'MX51_PAD_DISPB2_SER_RS',
>         other pads for this function are:
>         MX51_PAD_EIM_CS5         0x0904 0x0
> ERROR: Duplicate MUX value 0x2 for FUNC 'DISP1_EXT_CLK' and 'DISP1_PIN16' on PAD 'MX51_PAD_DISPB2_SER_RS'
> arch/arm/boot/dts/imx51-pinfunc.h: 755 pads checked: 1 errors found
>
> arch/arm/boot/dts/imx7d-pinfunc.h:
> ----------------------------------
> ERROR: Missing INPUT_SEL address for FUNCTION 'KPP_COL1' on PAD 'MX7D_PAD_ENET1_RGMII_RXC',
>         other pads for this function are:
>         MX7D_PAD_EPDC_DATA05     0x05f8 0x0
> ERROR: Missing INPUT_SEL address for FUNCTION 'SAI1_RX_BCLK' on PAD 'MX7D_PAD_ENET1_RGMII_TXC',
>         other pads for this function are:
>         MX7D_PAD_SAI1_RX_BCLK    0x069c 0x0
> ERROR: Missing INPUT_SEL address for FUNCTION 'SAI1_RX_SYNC' on PAD 'MX7D_PAD_ENET1_RGMII_TX_CTL',
>         other pads for this function are:
>         MX7D_PAD_SAI1_RX_SYNC    0x06a4 0x0
> ERROR: Duplicate MUX reg addr 0x0014 for pad 'MX7D_PAD_GPIO1_IO08' and 'MX7D_PAD_GPIO1_IO05'
> ERROR: Duplicate MUX reg addr 0x0018 for pad 'MX7D_PAD_GPIO1_IO09' and 'MX7D_PAD_GPIO1_IO06'
> ERROR: Duplicate MUX reg addr 0x001c for pad 'MX7D_PAD_GPIO1_IO10' and 'MX7D_PAD_GPIO1_IO07'
> ERROR: Missing INPUT_SEL address for FUNCTION 'CCM_PMIC_READY' on PAD 'MX7D_PAD_UART1_RX_DATA',
>         other pads for this function are:
>         MX7D_PAD_GPIO1_IO09      0x04f4 0x0
>         MX7D_PAD_GPIO1_IO13      0x04f4 0x1
>         MX7D_PAD_SAI1_MCLK       0x04f4 0x3
> ERROR: Missing INPUT_SEL address for FUNCTION 'ENET1_MDIO' on PAD 'MX7D_PAD_UART1_RX_DATA',
>         other pads for this function are:
>         MX7D_PAD_GPIO1_IO10      0x0568 0x0
>         MX7D_PAD_SD2_CD_B        0x0568 0x2
> ERROR: Missing INPUT_SEL address for FUNCTION 'SAI3_RX_BCLK' on PAD 'MX7D_PAD_UART2_RX_DATA',
>         other pads for this function are:
>         MX7D_PAD_SD1_CMD         0x06c4 0x1
>         MX7D_PAD_SD3_CMD         0x06c4 0x2
> ERROR: Missing INPUT_SEL address for FUNCTION 'ENET2_MDIO' on PAD 'MX7D_PAD_UART2_RX_DATA',
>         other pads for this function are:
>         MX7D_PAD_GPIO1_IO14      0x0574 0x0
>         MX7D_PAD_SD2_CD_B        0x0574 0x2
> ERROR: Missing INPUT_SEL address for FUNCTION 'UART2_DTE_RX' on PAD 'MX7D_PAD_UART2_TX_DATA',
>         other pads for this function are:
>         MX7D_PAD_LCD_ENABLE      0x06fc 0x1
> ERROR: Missing INPUT_SEL address for FUNCTION 'ECSPI1_SCLK' on PAD 'MX7D_PAD_UART3_RTS_B',
>         other pads for this function are:
>         MX7D_PAD_ECSPI1_SCLK     0x0524 0x1
> arch/arm/boot/dts/imx7d-pinfunc.h: 1135 pads checked: 12 errors found
>
>
> I will send a patch for imx6ul and imx51 shortly.
> But I have no resources to correct the bugs in the imx35, imx50 and
> imx7d files.
> The "Duplicate MUX reg addr" message for imx7d are false positives due
> to the deviant nature of the imx7d pinctrl design, but the other
> messages should be relevant.

Thanks. We will check auto generate script and found why this happen.

best regards
Frank Li

>
>
>
> Lothar Wa?mann
> --
> ___________________________________________________________
>
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>
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>
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>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h
  2016-02-26 14:52 ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Lothar Waßmann
  2016-02-26 14:52   ` [PATCH 2/2] ARM: dts: imx6ul: add missing input_sel config for various pins Lothar Waßmann
@ 2016-02-28  3:08   ` Shawn Guo
  1 sibling, 0 replies; 5+ messages in thread
From: Shawn Guo @ 2016-02-28  3:08 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Feb 26, 2016 at 03:52:57PM +0100, Lothar Wa?mann wrote:
> This patchset adds missing input_sel settings to imx6ul-pinfunc.h.
> The first patch is a cleanup patch with no functional changes
> intended.

Applied both, thanks.

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2016-02-28  3:08 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-02-26 11:44 [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files Lothar Waßmann
2016-02-26 14:52 ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Lothar Waßmann
2016-02-26 14:52   ` [PATCH 2/2] ARM: dts: imx6ul: add missing input_sel config for various pins Lothar Waßmann
2016-02-28  3:08   ` [PATCH 0/2] cleanup and add missing input_sel settings to imx6ul-pinfunc.h Shawn Guo
2016-02-26 17:31 ` [i.MX] various errors in arch/arm/boot/dts/imx*-pinfunc.h files Zhi Li

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