From: davem@davemloft.net (David Miller)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES
Date: Thu, 31 Mar 2016 16:47:10 -0400 (EDT) [thread overview]
Message-ID: <20160331.164710.1998871529914699937.davem@davemloft.net> (raw)
In-Reply-To: <20160331223735.32904e42@free-electrons.com>
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Date: Thu, 31 Mar 2016 22:37:35 +0200
> Hello,
>
> On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote:
>> From: Jisheng Zhang <jszhang@marvell.com>
>> Date: Wed, 30 Mar 2016 19:55:21 +0800
>>
>> > The mvneta is also used in some Marvell berlin family SoCs which may
>> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
>> > usage with L1_CACHE_BYTES.
>> >
>> > And since dma_alloc_coherent() is always cacheline size aligned, so
>> > remove the align checks.
>> >
>> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
>>
>> Applied.
>
> A new version of the patch was sent, which more rightfully uses
> cache_line_size(), see:
>
> "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size"
Sorry about that.
Send me a realtive fixup patch if you like.
Thanks.
next prev parent reply other threads:[~2016-03-31 20:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 11:55 [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES Jisheng Zhang
2016-03-31 19:15 ` David Miller
2016-03-31 20:37 ` Thomas Petazzoni
2016-03-31 20:47 ` David Miller [this message]
2016-04-01 7:15 ` Jisheng Zhang
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