[PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data

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* [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data
@ 2016-03-31 21:58 Nishanth Menon
  2016-03-31 21:58 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA Nishanth Menon
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Nishanth Menon @ 2016-03-31 21:58 UTC (permalink / raw)
  To: linux-arm-kernel

First level updates for power domain data, in line with the latest
AM57xx and DRA7 TRMs.

NOTE: follow on patches are pending for the following:

a) wakeupgen is somehow messedup again and mpu pd no
longer goes to low power mode. I am looking into that.
http://pastebin.ubuntu.com/15571519/ gets past that story - but I see
mpu_pwrdm stuck in ON though..

b) beagleboard-X15 does require the following patch
https://patchwork.kernel.org/patch/8718431/

c) We do have yet another major TRM update to only allow ON and OFF
for all power domains other than core and MPU (MPU still will support
CSWR) - I am still waiting for TRM update to take place before we can
actually post upstream.

BeagleBoard-X15 test log: http://pastebin.ubuntu.com/15571570/

series based on: v4.6-rc1

Nishanth Menon (3):
  ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable
    core INA
  ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories
  ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability

 arch/arm/mach-omap2/powerdomains7xx_data.c | 82 +++++++++++++++---------------
 1 file changed, 41 insertions(+), 41 deletions(-)

-- 
2.8.0

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA
  2016-03-31 21:58 [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Nishanth Menon
@ 2016-03-31 21:58 ` Nishanth Menon
  2016-03-31 21:58 ` [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories Nishanth Menon
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2016-03-31 21:58 UTC (permalink / raw)
  To: linux-arm-kernel

Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.

By allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues and device failure as a result.

Ref: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/powerdomains7xx_data.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 287a2037aa16..f2b4557124f3 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -160,7 +160,7 @@ static struct powerdomain core_7xx_pwrdm = {
 	.name		  = "core_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_CORE_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_INA_ON,
+	.pwrsts		  = PWRSTS_ON,
 	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 5,
 	.pwrsts_mem_ret	= {
-- 
2.8.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories
  2016-03-31 21:58 [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Nishanth Menon
  2016-03-31 21:58 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA Nishanth Menon
@ 2016-03-31 21:58 ` Nishanth Menon
  2016-03-31 21:58 ` [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability Nishanth Menon
  2016-04-13 21:30 ` [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Tony Lindgren
  3 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2016-03-31 21:58 UTC (permalink / raw)
  To: linux-arm-kernel

When the power domain is in "ON" state, the memories should be always
in "ON", even though the hardware register allows other states to be
written, wrong states may confuse certain hardware blocks.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/powerdomains7xx_data.c | 66 +++++++++++++++---------------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index f2b4557124f3..81e883d972b9 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -45,10 +45,10 @@ static struct powerdomain iva_7xx_pwrdm = {
 		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
-		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
-		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
-		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
+		[0] = PWRSTS_ON,	/* hwa_mem */
+		[1] = PWRSTS_ON,	/* sl2_mem */
+		[2] = PWRSTS_ON,	/* tcm1_mem */
+		[3] = PWRSTS_ON,	/* tcm2_mem */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -83,8 +83,8 @@ static struct powerdomain ipu_7xx_pwrdm = {
 		[1] = PWRSTS_OFF_RET,	/* periphmem */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* aessmem */
-		[1] = PWRSTS_OFF_RET,	/* periphmem */
+		[0] = PWRSTS_ON,	/* aessmem */
+		[1] = PWRSTS_ON,	/* periphmem */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -101,7 +101,7 @@ static struct powerdomain dss_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* dss_mem */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* dss_mem */
+		[0] = PWRSTS_ON,	/* dss_mem */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -119,8 +119,8 @@ static struct powerdomain l4per_7xx_pwrdm = {
 		[1] = PWRSTS_OFF_RET,	/* retained_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* nonretained_bank */
-		[1] = PWRSTS_OFF_RET,	/* retained_bank */
+		[0] = PWRSTS_ON,	/* nonretained_bank */
+		[1] = PWRSTS_ON,	/* retained_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -136,7 +136,7 @@ static struct powerdomain gpu_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
+		[0] = PWRSTS_ON,	/* gpu_mem */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -171,11 +171,11 @@ static struct powerdomain core_7xx_pwrdm = {
 		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
-		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
-		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
-		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
-		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
+		[0] = PWRSTS_ON,	/* core_nret_bank */
+		[1] = PWRSTS_ON,	/* core_ocmram */
+		[2] = PWRSTS_ON,	/* core_other_bank */
+		[3] = PWRSTS_ON,	/* ipu_l2ram */
+		[4] = PWRSTS_ON,	/* ipu_unicache */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -232,7 +232,7 @@ static struct powerdomain vpe_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
+		[0] = PWRSTS_ON,	/* vpe_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -250,8 +250,8 @@ static struct powerdomain mpu_7xx_pwrdm = {
 		[1] = PWRSTS_RET,	/* mpu_ram */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
-		[1] = PWRSTS_OFF_RET,	/* mpu_ram */
+		[0] = PWRSTS_ON,	/* mpu_l2 */
+		[1] = PWRSTS_ON,	/* mpu_ram */
 	},
 };
 
@@ -269,9 +269,9 @@ static struct powerdomain l3init_7xx_pwrdm = {
 		[2] = PWRSTS_OFF_RET,	/* l3init_bank2 */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* gmac_bank */
-		[1] = PWRSTS_OFF_RET,	/* l3init_bank1 */
-		[2] = PWRSTS_OFF_RET,	/* l3init_bank2 */
+		[0] = PWRSTS_ON,	/* gmac_bank */
+		[1] = PWRSTS_ON,	/* l3init_bank1 */
+		[2] = PWRSTS_ON,	/* l3init_bank2 */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -287,7 +287,7 @@ static struct powerdomain eve3_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* eve3_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* eve3_bank */
+		[0] = PWRSTS_ON,	/* eve3_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -303,7 +303,7 @@ static struct powerdomain emu_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* emu_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* emu_bank */
+		[0] = PWRSTS_ON,	/* emu_bank */
 	},
 };
 
@@ -320,9 +320,9 @@ static struct powerdomain dsp2_7xx_pwrdm = {
 		[2] = PWRSTS_OFF_RET,	/* dsp2_l2 */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* dsp2_edma */
-		[1] = PWRSTS_OFF_RET,	/* dsp2_l1 */
-		[2] = PWRSTS_OFF_RET,	/* dsp2_l2 */
+		[0] = PWRSTS_ON,	/* dsp2_edma */
+		[1] = PWRSTS_ON,	/* dsp2_l1 */
+		[2] = PWRSTS_ON,	/* dsp2_l2 */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -340,9 +340,9 @@ static struct powerdomain dsp1_7xx_pwrdm = {
 		[2] = PWRSTS_OFF_RET,	/* dsp1_l2 */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* dsp1_edma */
-		[1] = PWRSTS_OFF_RET,	/* dsp1_l1 */
-		[2] = PWRSTS_OFF_RET,	/* dsp1_l2 */
+		[0] = PWRSTS_ON,	/* dsp1_edma */
+		[1] = PWRSTS_ON,	/* dsp1_l1 */
+		[2] = PWRSTS_ON,	/* dsp1_l2 */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -358,7 +358,7 @@ static struct powerdomain cam_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* vip_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* vip_bank */
+		[0] = PWRSTS_ON,	/* vip_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -374,7 +374,7 @@ static struct powerdomain eve4_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* eve4_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* eve4_bank */
+		[0] = PWRSTS_ON,	/* eve4_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -390,7 +390,7 @@ static struct powerdomain eve2_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* eve2_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* eve2_bank */
+		[0] = PWRSTS_ON,	/* eve2_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -406,7 +406,7 @@ static struct powerdomain eve1_7xx_pwrdm = {
 		[0] = PWRSTS_OFF_RET,	/* eve1_bank */
 	},
 	.pwrsts_mem_on	= {
-		[0] = PWRSTS_OFF_RET,	/* eve1_bank */
+		[0] = PWRSTS_ON,	/* eve1_bank */
 	},
 	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
-- 
2.8.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability
  2016-03-31 21:58 [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Nishanth Menon
  2016-03-31 21:58 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA Nishanth Menon
  2016-03-31 21:58 ` [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories Nishanth Menon
@ 2016-03-31 21:58 ` Nishanth Menon
  2016-04-13 21:30 ` [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Tony Lindgren
  3 siblings, 0 replies; 5+ messages in thread
From: Nishanth Menon @ 2016-03-31 21:58 UTC (permalink / raw)
  To: linux-arm-kernel

Open Switch Retention(OSWR) is a retention state which is unsupported
in DRA7 SoC. This state is achieved when power state is set to
retention and logic power state is set to OFF.

Even though DRA7 architecture is a OMAP derivative, none of the
powerdomains are actually implemented to achieve OSWR in the SoC.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/powerdomains7xx_data.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 81e883d972b9..0ec2d00f4237 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -35,7 +35,7 @@ static struct powerdomain iva_7xx_pwrdm = {
 	.name		  = "iva_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_IVA_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts		  = PWRSTS_OFF_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 4,
 	.pwrsts_mem_ret	= {
@@ -75,7 +75,7 @@ static struct powerdomain ipu_7xx_pwrdm = {
 	.name		  = "ipu_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_IPU_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts		  = PWRSTS_OFF_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 2,
 	.pwrsts_mem_ret	= {
@@ -94,7 +94,7 @@ static struct powerdomain dss_7xx_pwrdm = {
 	.name		  = "dss_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_DSS_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_OFF_RET_ON,
+	.pwrsts		  = PWRSTS_OFF_ON,
 	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
@@ -112,7 +112,7 @@ static struct powerdomain l4per_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_RET_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 2,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* nonretained_bank */
@@ -225,8 +225,8 @@ static struct powerdomain vpe_7xx_pwrdm = {
 	.name		  = "vpe_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_VPE_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_OFF_RET_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.pwrsts		  = PWRSTS_OFF_ON,
+	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
@@ -261,7 +261,7 @@ static struct powerdomain l3init_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_RET_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF_RET,
+	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 3,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* gmac_bank */
-- 
2.8.0

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data
  2016-03-31 21:58 [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Nishanth Menon
                   ` (2 preceding siblings ...)
  2016-03-31 21:58 ` [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability Nishanth Menon
@ 2016-04-13 21:30 ` Tony Lindgren
  3 siblings, 0 replies; 5+ messages in thread
From: Tony Lindgren @ 2016-04-13 21:30 UTC (permalink / raw)
  To: linux-arm-kernel

* Nishanth Menon <nm@ti.com> [160331 15:01]:
> First level updates for power domain data, in line with the latest
> AM57xx and DRA7 TRMs.
> 
> NOTE: follow on patches are pending for the following:
> 
> a) wakeupgen is somehow messedup again and mpu pd no
> longer goes to low power mode. I am looking into that.
> http://pastebin.ubuntu.com/15571519/ gets past that story - but I see
> mpu_pwrdm stuck in ON though..
> 
> b) beagleboard-X15 does require the following patch
> https://patchwork.kernel.org/patch/8718431/
> 
> c) We do have yet another major TRM update to only allow ON and OFF
> for all power domains other than core and MPU (MPU still will support
> CSWR) - I am still waiting for TRM update to take place before we can
> actually post upstream.
> 
> BeagleBoard-X15 test log: http://pastebin.ubuntu.com/15571570/

Applying into omap-for-v4.7/soc thanks.

Tony

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2016-04-13 21:30 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2016-03-31 21:58 [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Nishanth Menon
2016-03-31 21:58 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA Nishanth Menon
2016-03-31 21:58 ` [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories Nishanth Menon
2016-03-31 21:58 ` [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability Nishanth Menon
2016-04-13 21:30 ` [PATCH 0/3] ARM: OMAP: DRA7: Updates for power domain data Tony Lindgren

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