From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec
Date: Fri, 15 Apr 2016 17:27:03 -0700 [thread overview]
Message-ID: <20160416002703.GH26353@codeaurora.org> (raw)
In-Reply-To: <1458158097-21137-3-git-send-email-t-kristo@ti.com>
On 03/16, Tero Kristo wrote:
> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
> max-rate parameter based on the DPLL types.
>
> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
> Cc: Lokesh Vutla <lokeshvutla@ti.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-04-16 0:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-16 19:54 [PATCH 0/3] ARM: AMx3xx: misc clock fixes Tero Kristo
2016-03-16 19:54 ` [PATCH 1/3] clk: ti: dpll: add support for specifying max rate for DPLLs Tero Kristo
2016-04-01 19:27 ` Stephen Boyd
2016-04-16 0:26 ` Stephen Boyd
2016-03-16 19:54 ` [PATCH 2/3] clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec Tero Kristo
2016-04-01 19:28 ` Stephen Boyd
2016-04-13 12:51 ` Tero Kristo
2016-04-16 0:23 ` Stephen Boyd
2016-04-16 0:27 ` Stephen Boyd [this message]
2016-03-16 19:54 ` [PATCH 3/3] ARM: dts: am43xx: add support for clkout1 clock Tero Kristo
2016-04-12 21:05 ` Tony Lindgren
2016-04-13 12:52 ` Tero Kristo
2016-04-13 19:07 ` Tony Lindgren
2016-03-16 22:33 ` [PATCH 0/3] ARM: AMx3xx: misc clock fixes Nishanth Menon
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