From: thierry.reding@gmail.com (Thierry Reding)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC v2 1/5] drm/mediatek: rename macros, add chip suffix
Date: Mon, 30 May 2016 12:41:29 +0200 [thread overview]
Message-ID: <20160530104129.GA8388@ulmo.ba.sec> (raw)
In-Reply-To: <1463756736-46573-2-git-send-email-yt.shen@mediatek.com>
On Fri, May 20, 2016 at 11:05:32PM +0800, yt.shen at mediatek.com wrote:
> From: YT Shen <yt.shen@mediatek.com>
>
> Add MT8173 suffix for hardware related macros.
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 62 ++++++++++++++++----------------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 17ba935..d6aafd4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -36,21 +36,21 @@
> #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
>
> -#define MUTEX_MOD_DISP_OVL0 BIT(11)
> -#define MUTEX_MOD_DISP_OVL1 BIT(12)
> -#define MUTEX_MOD_DISP_RDMA0 BIT(13)
> -#define MUTEX_MOD_DISP_RDMA1 BIT(14)
> -#define MUTEX_MOD_DISP_RDMA2 BIT(15)
> -#define MUTEX_MOD_DISP_WDMA0 BIT(16)
> -#define MUTEX_MOD_DISP_WDMA1 BIT(17)
> -#define MUTEX_MOD_DISP_COLOR0 BIT(18)
> -#define MUTEX_MOD_DISP_COLOR1 BIT(19)
> -#define MUTEX_MOD_DISP_AAL BIT(20)
> -#define MUTEX_MOD_DISP_GAMMA BIT(21)
> -#define MUTEX_MOD_DISP_UFOE BIT(22)
> -#define MUTEX_MOD_DISP_PWM0 BIT(23)
> -#define MUTEX_MOD_DISP_PWM1 BIT(24)
> -#define MUTEX_MOD_DISP_OD BIT(25)
> +#define MUTEX_MOD_DISP_OVL0_MT8173 BIT(11)
> +#define MUTEX_MOD_DISP_OVL1_MT8173 BIT(12)
> +#define MUTEX_MOD_DISP_RDMA0_MT8173 BIT(13)
> +#define MUTEX_MOD_DISP_RDMA1_MT8173 BIT(14)
> +#define MUTEX_MOD_DISP_RDMA2_MT8173 BIT(15)
> +#define MUTEX_MOD_DISP_WDMA0_MT8173 BIT(16)
> +#define MUTEX_MOD_DISP_WDMA1_MT8173 BIT(17)
> +#define MUTEX_MOD_DISP_COLOR0_MT8173 BIT(18)
> +#define MUTEX_MOD_DISP_COLOR1_MT8173 BIT(19)
> +#define MUTEX_MOD_DISP_AAL_MT8173 BIT(20)
> +#define MUTEX_MOD_DISP_GAMMA_MT8173 BIT(21)
> +#define MUTEX_MOD_DISP_UFOE_MT8173 BIT(22)
> +#define MUTEX_MOD_DISP_PWM0_MT8173 BIT(23)
> +#define MUTEX_MOD_DISP_PWM1_MT8173 BIT(24)
> +#define MUTEX_MOD_DISP_OD_MT8173 BIT(25)
Just a random fly-by comment: this looks like a hardware spinlock, have
you ever considered implementing this as a hwspinlock driver? See the
drivers/hwspinlock subdirectory for existing examples.
Thierry
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next prev parent reply other threads:[~2016-05-30 10:41 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-20 15:05 [RFC v2 0/5] MT2701 DRM support yt.shen at mediatek.com
2016-05-20 15:05 ` [RFC v2 1/5] drm/mediatek: rename macros, add chip suffix yt.shen at mediatek.com
2016-05-27 9:30 ` Emil Velikov
2016-05-30 10:23 ` YT Shen
2016-05-30 10:41 ` Thierry Reding [this message]
2016-06-01 9:09 ` YT Shen
2016-05-20 15:05 ` [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701 yt.shen at mediatek.com
2016-05-23 9:09 ` CK Hu
2016-05-27 7:29 ` YT Shen
2016-05-27 9:35 ` Emil Velikov
2016-05-30 10:24 ` YT Shen
2016-05-20 15:05 ` [RFC v2 3/5] drm/mediatek: add *driver_data for different hardware settings yt.shen at mediatek.com
2016-05-23 9:43 ` CK Hu
2016-05-27 7:31 ` YT Shen
2016-05-27 9:24 ` Emil Velikov
2016-05-30 10:26 ` YT Shen
2016-05-30 10:45 ` Thierry Reding
2016-06-01 9:10 ` YT Shen
2016-05-20 15:05 ` [RFC v2 4/5] drm/mediatek: add shadow register support yt.shen at mediatek.com
2016-05-20 15:05 ` [RFC v2 5/5] arm: dts: mt2701: Add display subsystem related nodes for MT2701 yt.shen at mediatek.com
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