From: linux@armlinux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec
Date: Tue, 28 Jun 2016 10:49:14 +0100 [thread overview]
Message-ID: <20160628094914.GI1041@n2100.armlinux.org.uk> (raw)
In-Reply-To: <1467106837-20996-1-git-send-email-patrice.chotard@st.com>
On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard at st.com wrote:
> From: Patrice Chotard <patrice.chotard@st.com>
>
> This patch implements the write_sec callback that handle PL310
> secure registers writes.
> This callback is just a stub for now, to avoid system crash.
> Later, it could handle SMC calls so that TZ handles the needed writes.
Is there much point having the L2 cache DT node enabled if you have
no support for the writes, which are required for the hardware to be
enabled?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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next prev parent reply other threads:[~2016-06-28 9:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-28 9:40 [PATCH] ARM: sti: Implement dummy L2 cache's write_sec patrice.chotard at st.com
2016-06-28 9:49 ` Russell King - ARM Linux [this message]
2016-06-28 11:55 ` Patrice Chotard
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