From: briannorris@chromium.org (Brian Norris)
To: linux-arm-kernel@lists.infradead.org
Subject: [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src
Date: Mon, 1 Aug 2016 13:13:50 -0700 [thread overview]
Message-ID: <20160801201349.GA129313@google.com> (raw)
In-Reply-To: <1470045224-31854-4-git-send-email-zhengxing@rock-chips.com>
On Mon, Aug 01, 2016 at 05:53:38PM +0800, Xing Zheng wrote:
> There was a typo, swapping 'c' <--> 'g'.
> (This patch is updated and am from https://patchwork.kernel.org/patch/9254067/)
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> ---
>
> Changes in v2: None
I believe this patch was already applied upstream; otherwise, it
wouldn't make sense to have both this patch and patch 4 -- we would
probably squash them together.
Brian
> drivers/clk/rockchip/clk-rk3399.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index f55f967f..2182391 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
> RK3399_CLKGATE_CON(13), 1, GFLAGS),
>
> /* perihp */
> - GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> + GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(5), 0, GFLAGS),
> - GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
> + GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
> RK3399_CLKGATE_CON(5), 1, GFLAGS),
> COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
> RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
> --
> 1.7.9.5
>
>
next prev parent reply other threads:[~2016-08-01 20:13 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-01 9:53 [RESEND PATCH v2 0/8] fix and optimize some clock configuration for the RK3399 platfom Xing Zheng
2016-08-01 9:53 ` [RESEND PATCH v2 2/8] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1 Xing Zheng
2016-08-01 9:53 ` [RESEND PATCH v2 3/8] clk: rockchip: rk3399: fix incorrect parent for rk3399's {c, g}pll_aclk_perihp_src Xing Zheng
2016-08-01 20:13 ` Brian Norris [this message]
2016-08-02 1:50 ` Xing Zheng
2016-08-01 9:53 ` [RESEND PATCH v2 4/8] clk: rockchip: rk3399: fix incorrect GATE bits for " Xing Zheng
2016-08-01 20:20 ` Brian Norris
2016-08-01 9:56 ` [RESEND PATCH v2 5/8] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits Xing Zheng
2016-08-01 9:58 ` [RESEND PATCH v2 6/8] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI Xing Zheng
2016-08-01 9:58 ` [RESEND PATCH v2 7/8] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie Xing Zheng
2016-08-01 9:58 ` [RESEND PATCH v2 8/8] clk: rockchip: rk3399: Add support frac mode frequencies Xing Zheng
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