From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [kernel-hardening] [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
Date: Mon, 15 Aug 2016 11:10:09 +0100 [thread overview]
Message-ID: <20160815101009.GC13262@arm.com> (raw)
In-Reply-To: <20160815100649.GB1996@svinekod>
On Mon, Aug 15, 2016 at 11:06:49AM +0100, Mark Rutland wrote:
> On Mon, Aug 15, 2016 at 12:02:33PM +0200, Ard Biesheuvel wrote:
> > On 15 August 2016 at 11:58, Mark Rutland <mark.rutland@arm.com> wrote:
> > > On Mon, Aug 15, 2016 at 10:48:42AM +0100, Catalin Marinas wrote:
> > >> On Sat, Aug 13, 2016 at 11:13:58AM +0200, Ard Biesheuvel wrote:
> > >> > On 12 August 2016 at 17:27, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > >> > > This is the first (public) attempt at emulating PAN by disabling
> > >> > > TTBR0_EL1 accesses on arm64.
> > >> >
> > >> > I take it using TCR_EL1.EPD0 is too expensive?
> > >>
> > >> It would require full TLB invalidation on entering/exiting the kernel
> > >> and again for any user access. That's because the architecture allows
> > >> this bit to be cached in the TLB so without TLBI we wouldn't have any
> > >> guarantee that the actual PAN was toggled. I'm not sure it's even clear
> > >> whether a TLBI by ASID or a local one would suffice (likely OK for the
> > >> latter).
> > >
> > > It's worth noting that even ignoring the TLB-caching of TCR_EL1.EPD0, the
> > > control only affects the behaviour on a TLB miss. Thus to use EPD0 we'd at
> > > least need TLB invalidation by ASID to remove previously-allocated entries from
> > > TLBs.
> >
> > ... or update the ASID to the reserved ASID in TTBR0_EL1, but leave
> > the actual TTBR address alone.
> >
> > This would remove the need for a zero page, and for recording the
> > original TTBR address in a per-cpu variable.
>
> That's a good point, and a better approach.
>
> Unfortunately, we're still left with the issue that TCR_EL1.* can be cached in
> a TLB, as Catalin pointed out. Which at minimum would require a TLBI ASIDE1,
> and may require something stronger, given the precise rules for TLB-cached
> fields isn't clear.
I suggest we get this clarified before merging the patch, as even the
author admits that it's ugly ;)
Will
next prev parent reply other threads:[~2016-08-15 10:10 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-12 15:27 [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-08-12 15:27 ` [PATCH 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-08-12 15:27 ` [PATCH 2/7] arm64: Factor out TTBR0_EL1 setting into a specific asm macro Catalin Marinas
2016-08-12 15:27 ` [PATCH 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-08-12 15:27 ` [PATCH 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-08-15 11:18 ` Mark Rutland
2016-08-15 16:39 ` Catalin Marinas
2016-08-12 15:27 ` [PATCH 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-08-12 15:27 ` [PATCH 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-08-15 9:58 ` Julien Grall
2016-08-15 18:00 ` Stefano Stabellini
2016-08-12 15:27 ` [PATCH 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas
2016-08-12 18:04 ` [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook
2016-08-12 18:22 ` Catalin Marinas
2016-08-13 9:13 ` [kernel-hardening] " Ard Biesheuvel
2016-08-15 9:48 ` Catalin Marinas
2016-08-15 9:58 ` Mark Rutland
2016-08-15 10:02 ` Ard Biesheuvel
2016-08-15 10:06 ` Mark Rutland
2016-08-15 10:10 ` Will Deacon [this message]
2016-08-15 10:15 ` Mark Rutland
2016-08-15 10:21 ` Will Deacon
2016-08-15 10:21 ` Ard Biesheuvel
2016-08-15 10:30 ` Will Deacon
2016-08-15 10:31 ` Ard Biesheuvel
2016-08-15 10:37 ` Will Deacon
2016-08-15 10:43 ` Ard Biesheuvel
2016-08-15 10:52 ` Catalin Marinas
2016-08-15 10:56 ` Ard Biesheuvel
2016-08-15 11:02 ` Will Deacon
2016-08-15 16:13 ` Catalin Marinas
2016-08-15 19:04 ` Ard Biesheuvel
2016-08-15 11:00 ` Will Deacon
2016-08-15 10:30 ` Mark Rutland
2016-08-15 10:08 ` Will Deacon
2016-08-26 15:39 ` David Brown
2016-08-26 17:24 ` Catalin Marinas
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