* [PATCH v2 0/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
@ 2016-08-25 6:57 Chanwoo Choi
2016-08-25 6:57 ` [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Chanwoo Choi
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Chanwoo Choi @ 2016-08-25 6:57 UTC (permalink / raw)
To: linux-arm-kernel
This patches add the clocks for CMU_CDREX (DRAM Express Controller)
that generates the clocks for DRAM and NoC (Network on Chip) bus clock.
[clk_summary on exynos5422-odroidxu3 board]
fout_bpll 0 0 800000000 0 0
mout_bpll 0 0 800000000 0 0
mout_mclk_cdrex 0 0 800000000 0 0
dout_pclk_core_mem 0 0 200000000 0 0
dout_sclk_cdrex 0 0 800000000 0 0
Changes from v1:
- Use the BPLL for DRAM clock to generate the 800MHz
- Add patch3 to assign the clock rate for DRAM clock
Chanwoo Choi (3):
dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller)
clk: samsung: exynos5420: Add clocks for CMU_CDREX domain
ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 +++
drivers/clk/samsung/clk-exynos5420.c | 37 ++++++++++++++++++++++
include/dt-bindings/clock/exynos5420.h | 11 ++++++-
3 files changed, 52 insertions(+), 1 deletion(-)
--
1.9.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) 2016-08-25 6:57 [PATCH v2 0/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi @ 2016-08-25 6:57 ` Chanwoo Choi 2016-09-01 17:28 ` Sylwester Nawrocki 2016-08-25 6:57 ` [PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi 2016-08-25 6:57 ` [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 Chanwoo Choi 2 siblings, 1 reply; 8+ messages in thread From: Chanwoo Choi @ 2016-08-25 6:57 UTC (permalink / raw) To: linux-arm-kernel This patch adds the new clock id for CMU_CDRES (DRAM Express Controller) geneates the clocks for DRAM and NoC (Network on Chip) bus clock. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- include/dt-bindings/clock/exynos5420.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 17ab8394bec7..6fd21c291416 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -214,6 +214,9 @@ #define CLK_MOUT_SW_ACLK400 651 #define CLK_MOUT_USER_ACLK300_GSCL 652 #define CLK_MOUT_SW_ACLK300_GSCL 653 +#define CLK_MOUT_MCLK_CDREX 654 +#define CLK_MOUT_BPLL 655 +#define CLK_MOUT_MX_MSPLL_CCORE 656 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -239,8 +242,14 @@ #define CLK_DOUT_ACLK300_DISP1 788 #define CLK_DOUT_ACLK300_GSCL 789 #define CLK_DOUT_ACLK400_DISP1 790 +#define CLK_DOUT_PCLK_CDREX 791 +#define CLK_DOUT_SCLK_CDREX 792 +#define CLK_DOUT_ACLK_CDREX1 793 +#define CLK_DOUT_CCLK_DREX0 794 +#define CLK_DOUT_CLK2X_PHY0 795 +#define CLK_DOUT_PCLK_CORE_MEM 796 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 791 +#define CLK_NR_CLKS 797 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) 2016-08-25 6:57 ` [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Chanwoo Choi @ 2016-09-01 17:28 ` Sylwester Nawrocki 0 siblings, 0 replies; 8+ messages in thread From: Sylwester Nawrocki @ 2016-09-01 17:28 UTC (permalink / raw) To: linux-arm-kernel On 08/25/2016 08:57 AM, Chanwoo Choi wrote: > This patch adds the new clock id for CMU_CDRES (DRAM Express Controller) > geneates the clocks for DRAM and NoC (Network on Chip) bus clock. > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Applied with the commit message changed as below, thanks. commit 9c605fbc299d31b482aefae547d126062c7a8792 Author: Chanwoo Choi <cw00.choi@samsung.com> Date: Thu Aug 25 15:57:16 2016 +0900 dt-bindings: Add clock IDs for the CMU_CDREX (DRAM Express Controller) This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller) which generates clocks for DRAM and NoC (Network on Chip) busses. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain 2016-08-25 6:57 [PATCH v2 0/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi 2016-08-25 6:57 ` [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Chanwoo Choi @ 2016-08-25 6:57 ` Chanwoo Choi 2016-09-01 17:32 ` Sylwester Nawrocki 2016-08-25 6:57 ` [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 Chanwoo Choi 2 siblings, 1 reply; 8+ messages in thread From: Chanwoo Choi @ 2016-08-25 6:57 UTC (permalink / raw) To: linux-arm-kernel This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express Controller) which generates the clocks for DRAM and NoC (Network on Chip) bus clock. But, there is differnet source of MUX_MX_MSPLL_CCORE between exynos5420 and exynos5422. So, each MUX_MX_MSPLL_CCORE uses the different parent source group. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index bb196ca21a77..8c8b495cbf0d 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -131,6 +131,9 @@ #define TOP_SPARE2 0x10b08 #define BPLL_LOCK 0x20010 #define BPLL_CON0 0x20110 +#define SRC_CDREX 0x20200 +#define DIV_CDREX0 0x20500 +#define DIV_CDREX1 0x20504 #define KPLL_LOCK 0x28000 #define KPLL_CON0 0x28100 #define SRC_KFC 0x28200 @@ -244,6 +247,9 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { GATE_TOP_SCLK_FSYS, GATE_TOP_SCLK_PERIC, TOP_SPARE2, + SRC_CDREX, + DIV_CDREX0, + DIV_CDREX1, SRC_KFC, DIV_KFC0, }; @@ -448,6 +454,8 @@ PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", "mout_sclk_epll", "mout_sclk_rpll"}; PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll"}; +PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; + /* List of parents specific to exynos5800 */ PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", @@ -465,6 +473,9 @@ PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", "mout_epll2", "mout_sclk_ipll" }; +PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", + "mout_sclk_mpll", "ff_dout_spll2", + "mout_sclk_spll", "mout_sclk_epll"}; PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", "mout_sclk_mpll", "ff_dout_spll2" }; @@ -523,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 20, 2), MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), @@ -601,6 +614,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", + mout_group5_5800_p, SRC_TOP7, 16, 2), MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2), MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), @@ -744,6 +759,12 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), + /* CDREX block */ + MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, + SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), + MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, + CLK_SET_RATE_PARENT, 0), + /* MAU Block */ MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), @@ -836,6 +857,21 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3), + /* CDREX Block */ + DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", + DIV_CDREX0, 28, 3), + DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", + DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), + DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", + DIV_CDREX0, 16, 3), + DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", + DIV_CDREX0, 8, 3), + DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", + DIV_CDREX0, 3, 5), + + DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", + DIV_CDREX1, 8, 3), + /* Audio Block */ DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), @@ -1364,6 +1400,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain 2016-08-25 6:57 ` [PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi @ 2016-09-01 17:32 ` Sylwester Nawrocki 0 siblings, 0 replies; 8+ messages in thread From: Sylwester Nawrocki @ 2016-09-01 17:32 UTC (permalink / raw) To: linux-arm-kernel On 08/25/2016 08:57 AM, Chanwoo Choi wrote: > This patch adds the mux/divider clocks for CMU_CDREX (DRAM Express > Controller) which generates the clocks for DRAM and NoC (Network on Chip) bus > clock. But, there is differnet source of MUX_MX_MSPLL_CCORE between exynos5420 > and exynos5422. So, each MUX_MX_MSPLL_CCORE uses the different parent source > group. > > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Applied, thanks, ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 2016-08-25 6:57 [PATCH v2 0/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi 2016-08-25 6:57 ` [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Chanwoo Choi 2016-08-25 6:57 ` [PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi @ 2016-08-25 6:57 ` Chanwoo Choi 2016-08-27 16:33 ` Krzysztof Kozlowski 2 siblings, 1 reply; 8+ messages in thread From: Chanwoo Choi @ 2016-08-25 6:57 UTC (permalink / raw) To: linux-arm-kernel This patch sets the clock rate for DREX (DRAM Express) block on exynos5422-odroidxu3 board. In the exynos5422 TRM, DRAM clocks use BPLL clock and CMU_CDREX generates the 800MHz DRAM clock. [clk_summary on exynos5422-odroidxu3 board] fout_bpll 0 0 800000000 0 0 mout_bpll 0 0 800000000 0 0 mout_mclk_cdrex 0 0 800000000 0 0 dout_pclk_core_mem 0 0 200000000 0 0 dout_sclk_cdrex 0 0 800000000 0 0 Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d56253049ccb..fd3f67c72039 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -229,6 +229,11 @@ status = "okay"; }; +&clock { + assigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>; + assigned-clock-rates = <800000000>; +}; + &clock_audss { assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_I2S>, -- 1.9.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 2016-08-25 6:57 ` [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 Chanwoo Choi @ 2016-08-27 16:33 ` Krzysztof Kozlowski 2016-09-02 8:58 ` Chanwoo Choi 0 siblings, 1 reply; 8+ messages in thread From: Krzysztof Kozlowski @ 2016-08-27 16:33 UTC (permalink / raw) To: linux-arm-kernel On Thu, Aug 25, 2016 at 03:57:18PM +0900, Chanwoo Choi wrote: > This patch sets the clock rate for DREX (DRAM Express) block > on exynos5422-odroidxu3 board. In the exynos5422 TRM, > DRAM clocks use BPLL clock and CMU_CDREX generates > the 800MHz DRAM clock. > >From the commit message I don't get two things: 1. Why setting this on XU3-family of boards, not all 542x/5800? 2. Why this is needed? The commit msg lacks the answer to the "why". > [clk_summary on exynos5422-odroidxu3 board] > fout_bpll 0 0 800000000 0 0 > mout_bpll 0 0 800000000 0 0 > mout_mclk_cdrex 0 0 800000000 0 0 > dout_pclk_core_mem 0 0 200000000 0 0 > dout_sclk_cdrex 0 0 800000000 0 0 > What is the purpose of this dump of clk_summary? Is it a state before or after the change? After it is quite obvious that it should have 800MHz... Best regards, Krzysztof > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > --- > arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > index d56253049ccb..fd3f67c72039 100644 > --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi > @@ -229,6 +229,11 @@ > status = "okay"; > }; > > +&clock { > + assigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>; > + assigned-clock-rates = <800000000>; > +}; > + > &clock_audss { > assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, > <&clock_audss EXYNOS_MOUT_I2S>, > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 2016-08-27 16:33 ` Krzysztof Kozlowski @ 2016-09-02 8:58 ` Chanwoo Choi 0 siblings, 0 replies; 8+ messages in thread From: Chanwoo Choi @ 2016-09-02 8:58 UTC (permalink / raw) To: linux-arm-kernel On 2016? 08? 28? 01:33, Krzysztof Kozlowski wrote: > On Thu, Aug 25, 2016 at 03:57:18PM +0900, Chanwoo Choi wrote: >> This patch sets the clock rate for DREX (DRAM Express) block >> on exynos5422-odroidxu3 board. In the exynos5422 TRM, >> DRAM clocks use BPLL clock and CMU_CDREX generates >> the 800MHz DRAM clock. >> > >>From the commit message I don't get two things: > 1. Why setting this on XU3-family of boards, not all 542x/5800? I have the only xu3 board. I cannot test it on other boards. > 2. Why this is needed? The commit msg lacks the answer to the "why". In the exynos5422's TRM, CMU_CDREX generates the 800MHz DRAM clock as above commit message. But, I'm missing what there is different before applying this patch. I add comment why we should set the clock rate for DRAM on below. > >> [clk_summary on exynos5422-odroidxu3 board] >> fout_bpll 0 0 800000000 0 0 >> mout_bpll 0 0 800000000 0 0 >> mout_mclk_cdrex 0 0 800000000 0 0 >> dout_pclk_core_mem 0 0 200000000 0 0 >> dout_sclk_cdrex 0 0 800000000 0 0 >> > > What is the purpose of this dump of clk_summary? Is it a state before or > after the change? After it is quite obvious that it should have > 800MHz... I'm missing the difference before applying this patch. As I mentioned on v1[1] patch, if I don't set the clock rate for CDREX, the default clock is 825MHz instead of 800MHz. So, I set the clock rate on this patch. [1] https://lkml.org/lkml/2016/8/22/255 If I don't apply this patch, the DREX clock is 825MHz. fout_bpll 0 0 825000000 0 0 mout_bpll 0 0 825000000 0 0 mout_mclk_cdrex 0 0 825000000 0 0 dout_pclk_core_mem 0 0 206250000 0 0 dout_sclk_cdrex 0 0 825000000 0 0 dout_clk2x_phy0 0 0 825000000 0 0 dout_aclk_cdrex1 0 0 412500000 0 0 dout_pclk_cdrex 0 0 103125000 0 0 dout_cclk_drex0 0 0 412500000 0 0 If you want to edit the commit message, I'll resend the v3 patch. Best Regards, Chanwoo Choi > > Best regards, > Krzysztof > >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> --- >> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> index d56253049ccb..fd3f67c72039 100644 >> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi >> @@ -229,6 +229,11 @@ >> status = "okay"; >> }; >> >> +&clock { >> + assigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>; >> + assigned-clock-rates = <800000000>; >> +}; >> + >> &clock_audss { >> assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, >> <&clock_audss EXYNOS_MOUT_I2S>, >> -- >> 1.9.1 >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel at lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > > > ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-09-02 8:58 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-08-25 6:57 [PATCH v2 0/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi 2016-08-25 6:57 ` [PATCH v2 1/3] dt-bindings: Add the clock id for CMU_CDREX (DRAM Express Controller) Chanwoo Choi 2016-09-01 17:28 ` Sylwester Nawrocki 2016-08-25 6:57 ` [PATCH v2 2/3] clk: samsung: exynos5420: Add clocks for CMU_CDREX domain Chanwoo Choi 2016-09-01 17:32 ` Sylwester Nawrocki 2016-08-25 6:57 ` [PATCH v2 3/3] ARM: dts: Set the clock rate for DREX block 800Mhz on exynos5422-odroidxu3 Chanwoo Choi 2016-08-27 16:33 ` Krzysztof Kozlowski 2016-09-02 8:58 ` Chanwoo Choi
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