From: boris.brezillon@free-electrons.com (Boris Brezillon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/7] mtd: nand: convert ONFI mode into data interface
Date: Tue, 6 Sep 2016 13:27:08 +0200 [thread overview]
Message-ID: <20160906132708.172a6475@bbrezillon> (raw)
In-Reply-To: <1473158355-22451-4-git-send-email-s.hauer@pengutronix.de>
On Tue, 6 Sep 2016 12:39:11 +0200
Sascha Hauer <s.hauer@pengutronix.de> wrote:
> struct nand_data_interface is the designated type to pass to
> the NAND drivers to configure the timing. To simplify this introduce
> onfi_async_timing_mode_to_data_interface() to convert a ONFI
> mode into a nand_data_interface.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/mtd/nand/nand_timings.c | 444 +++++++++++++++++++++-------------------
> include/linux/mtd/nand.h | 2 +
> 2 files changed, 240 insertions(+), 206 deletions(-)
>
> diff --git a/drivers/mtd/nand/nand_timings.c b/drivers/mtd/nand/nand_timings.c
> index e81470a..260b074 100644
> --- a/drivers/mtd/nand/nand_timings.c
> +++ b/drivers/mtd/nand/nand_timings.c
> @@ -13,228 +13,246 @@
> #include <linux/export.h>
> #include <linux/mtd/nand.h>
>
> -static const struct nand_sdr_timings onfi_sdr_timings[] = {
> +static const struct nand_data_interface onfi_sdr_timings[] = {
Do you have a good reason to turn onfi_sdr_timings into an array of
struct nand_data_interface?
> /* Mode 0 */
> {
> - .tADL_min = 200000,
> - .tALH_min = 20000,
> - .tALS_min = 50000,
> - .tAR_min = 25000,
> - .tCEA_max = 100000,
> - .tCEH_min = 20000,
> - .tCH_min = 20000,
> - .tCHZ_max = 100000,
> - .tCLH_min = 20000,
> - .tCLR_min = 20000,
> - .tCLS_min = 50000,
> - .tCOH_min = 0,
> - .tCS_min = 70000,
> - .tDH_min = 20000,
> - .tDS_min = 40000,
> - .tFEAT_max = 1000000,
> - .tIR_min = 10000,
> - .tITC_max = 1000000,
> - .tRC_min = 100000,
> - .tREA_max = 40000,
> - .tREH_min = 30000,
> - .tRHOH_min = 0,
> - .tRHW_min = 200000,
> - .tRHZ_max = 200000,
> - .tRLOH_min = 0,
> - .tRP_min = 50000,
> - .tRST_max = 250000000000ULL,
> - .tWB_max = 200000,
> - .tRR_min = 40000,
> - .tWC_min = 100000,
> - .tWH_min = 30000,
> - .tWHR_min = 120000,
> - .tWP_min = 50000,
> - .tWW_min = 100000,
> + .type = NAND_SDR_IFACE,
> + .timings.sdr = {
> + .tADL_min = 200000,
> + .tALH_min = 20000,
> + .tALS_min = 50000,
> + .tAR_min = 25000,
> + .tCEA_max = 100000,
> + .tCEH_min = 20000,
> + .tCH_min = 20000,
> + .tCHZ_max = 100000,
> + .tCLH_min = 20000,
> + .tCLR_min = 20000,
> + .tCLS_min = 50000,
> + .tCOH_min = 0,
> + .tCS_min = 70000,
> + .tDH_min = 20000,
> + .tDS_min = 40000,
> + .tFEAT_max = 1000000,
> + .tIR_min = 10000,
> + .tITC_max = 1000000,
> + .tRC_min = 100000,
> + .tREA_max = 40000,
> + .tREH_min = 30000,
> + .tRHOH_min = 0,
> + .tRHW_min = 200000,
> + .tRHZ_max = 200000,
> + .tRLOH_min = 0,
> + .tRP_min = 50000,
> + .tRST_max = 250000000000ULL,
> + .tWB_max = 200000,
> + .tRR_min = 40000,
> + .tWC_min = 100000,
> + .tWH_min = 30000,
> + .tWHR_min = 120000,
> + .tWP_min = 50000,
> + .tWW_min = 100000,
> + },
> },
> /* Mode 1 */
> {
> - .tADL_min = 100000,
> - .tALH_min = 10000,
> - .tALS_min = 25000,
> - .tAR_min = 10000,
> - .tCEA_max = 45000,
> - .tCEH_min = 20000,
> - .tCH_min = 10000,
> - .tCHZ_max = 50000,
> - .tCLH_min = 10000,
> - .tCLR_min = 10000,
> - .tCLS_min = 25000,
> - .tCOH_min = 15000,
> - .tCS_min = 35000,
> - .tDH_min = 10000,
> - .tDS_min = 20000,
> - .tFEAT_max = 1000000,
> - .tIR_min = 0,
> - .tITC_max = 1000000,
> - .tRC_min = 50000,
> - .tREA_max = 30000,
> - .tREH_min = 15000,
> - .tRHOH_min = 15000,
> - .tRHW_min = 100000,
> - .tRHZ_max = 100000,
> - .tRLOH_min = 0,
> - .tRP_min = 25000,
> - .tRR_min = 20000,
> - .tRST_max = 500000000,
> - .tWB_max = 100000,
> - .tWC_min = 45000,
> - .tWH_min = 15000,
> - .tWHR_min = 80000,
> - .tWP_min = 25000,
> - .tWW_min = 100000,
> + .type = NAND_SDR_IFACE,
> + .timings.sdr = {
> + .tADL_min = 100000,
> + .tALH_min = 10000,
> + .tALS_min = 25000,
> + .tAR_min = 10000,
> + .tCEA_max = 45000,
> + .tCEH_min = 20000,
> + .tCH_min = 10000,
> + .tCHZ_max = 50000,
> + .tCLH_min = 10000,
> + .tCLR_min = 10000,
> + .tCLS_min = 25000,
> + .tCOH_min = 15000,
> + .tCS_min = 35000,
> + .tDH_min = 10000,
> + .tDS_min = 20000,
> + .tFEAT_max = 1000000,
> + .tIR_min = 0,
> + .tITC_max = 1000000,
> + .tRC_min = 50000,
> + .tREA_max = 30000,
> + .tREH_min = 15000,
> + .tRHOH_min = 15000,
> + .tRHW_min = 100000,
> + .tRHZ_max = 100000,
> + .tRLOH_min = 0,
> + .tRP_min = 25000,
> + .tRR_min = 20000,
> + .tRST_max = 500000000,
> + .tWB_max = 100000,
> + .tWC_min = 45000,
> + .tWH_min = 15000,
> + .tWHR_min = 80000,
> + .tWP_min = 25000,
> + .tWW_min = 100000,
> + },
> },
> /* Mode 2 */
> {
> - .tADL_min = 100000,
> - .tALH_min = 10000,
> - .tALS_min = 15000,
> - .tAR_min = 10000,
> - .tCEA_max = 30000,
> - .tCEH_min = 20000,
> - .tCH_min = 10000,
> - .tCHZ_max = 50000,
> - .tCLH_min = 10000,
> - .tCLR_min = 10000,
> - .tCLS_min = 15000,
> - .tCOH_min = 15000,
> - .tCS_min = 25000,
> - .tDH_min = 5000,
> - .tDS_min = 15000,
> - .tFEAT_max = 1000000,
> - .tIR_min = 0,
> - .tITC_max = 1000000,
> - .tRC_min = 35000,
> - .tREA_max = 25000,
> - .tREH_min = 15000,
> - .tRHOH_min = 15000,
> - .tRHW_min = 100000,
> - .tRHZ_max = 100000,
> - .tRLOH_min = 0,
> - .tRR_min = 20000,
> - .tRST_max = 500000000,
> - .tWB_max = 100000,
> - .tRP_min = 17000,
> - .tWC_min = 35000,
> - .tWH_min = 15000,
> - .tWHR_min = 80000,
> - .tWP_min = 17000,
> - .tWW_min = 100000,
> + .type = NAND_SDR_IFACE,
> + .timings.sdr = {
> + .tADL_min = 100000,
> + .tALH_min = 10000,
> + .tALS_min = 15000,
> + .tAR_min = 10000,
> + .tCEA_max = 30000,
> + .tCEH_min = 20000,
> + .tCH_min = 10000,
> + .tCHZ_max = 50000,
> + .tCLH_min = 10000,
> + .tCLR_min = 10000,
> + .tCLS_min = 15000,
> + .tCOH_min = 15000,
> + .tCS_min = 25000,
> + .tDH_min = 5000,
> + .tDS_min = 15000,
> + .tFEAT_max = 1000000,
> + .tIR_min = 0,
> + .tITC_max = 1000000,
> + .tRC_min = 35000,
> + .tREA_max = 25000,
> + .tREH_min = 15000,
> + .tRHOH_min = 15000,
> + .tRHW_min = 100000,
> + .tRHZ_max = 100000,
> + .tRLOH_min = 0,
> + .tRR_min = 20000,
> + .tRST_max = 500000000,
> + .tWB_max = 100000,
> + .tRP_min = 17000,
> + .tWC_min = 35000,
> + .tWH_min = 15000,
> + .tWHR_min = 80000,
> + .tWP_min = 17000,
> + .tWW_min = 100000,
> + },
> },
> /* Mode 3 */
> {
> - .tADL_min = 100000,
> - .tALH_min = 5000,
> - .tALS_min = 10000,
> - .tAR_min = 10000,
> - .tCEA_max = 25000,
> - .tCEH_min = 20000,
> - .tCH_min = 5000,
> - .tCHZ_max = 50000,
> - .tCLH_min = 5000,
> - .tCLR_min = 10000,
> - .tCLS_min = 10000,
> - .tCOH_min = 15000,
> - .tCS_min = 25000,
> - .tDH_min = 5000,
> - .tDS_min = 10000,
> - .tFEAT_max = 1000000,
> - .tIR_min = 0,
> - .tITC_max = 1000000,
> - .tRC_min = 30000,
> - .tREA_max = 20000,
> - .tREH_min = 10000,
> - .tRHOH_min = 15000,
> - .tRHW_min = 100000,
> - .tRHZ_max = 100000,
> - .tRLOH_min = 0,
> - .tRP_min = 15000,
> - .tRR_min = 20000,
> - .tRST_max = 500000000,
> - .tWB_max = 100000,
> - .tWC_min = 30000,
> - .tWH_min = 10000,
> - .tWHR_min = 80000,
> - .tWP_min = 15000,
> - .tWW_min = 100000,
> + .type = NAND_SDR_IFACE,
> + .timings.sdr = {
> + .tADL_min = 100000,
> + .tALH_min = 5000,
> + .tALS_min = 10000,
> + .tAR_min = 10000,
> + .tCEA_max = 25000,
> + .tCEH_min = 20000,
> + .tCH_min = 5000,
> + .tCHZ_max = 50000,
> + .tCLH_min = 5000,
> + .tCLR_min = 10000,
> + .tCLS_min = 10000,
> + .tCOH_min = 15000,
> + .tCS_min = 25000,
> + .tDH_min = 5000,
> + .tDS_min = 10000,
> + .tFEAT_max = 1000000,
> + .tIR_min = 0,
> + .tITC_max = 1000000,
> + .tRC_min = 30000,
> + .tREA_max = 20000,
> + .tREH_min = 10000,
> + .tRHOH_min = 15000,
> + .tRHW_min = 100000,
> + .tRHZ_max = 100000,
> + .tRLOH_min = 0,
> + .tRP_min = 15000,
> + .tRR_min = 20000,
> + .tRST_max = 500000000,
> + .tWB_max = 100000,
> + .tWC_min = 30000,
> + .tWH_min = 10000,
> + .tWHR_min = 80000,
> + .tWP_min = 15000,
> + .tWW_min = 100000,
> + },
> },
> /* Mode 4 */
> {
> - .tADL_min = 70000,
> - .tALH_min = 5000,
> - .tALS_min = 10000,
> - .tAR_min = 10000,
> - .tCEA_max = 25000,
> - .tCEH_min = 20000,
> - .tCH_min = 5000,
> - .tCHZ_max = 30000,
> - .tCLH_min = 5000,
> - .tCLR_min = 10000,
> - .tCLS_min = 10000,
> - .tCOH_min = 15000,
> - .tCS_min = 20000,
> - .tDH_min = 5000,
> - .tDS_min = 10000,
> - .tFEAT_max = 1000000,
> - .tIR_min = 0,
> - .tITC_max = 1000000,
> - .tRC_min = 25000,
> - .tREA_max = 20000,
> - .tREH_min = 10000,
> - .tRHOH_min = 15000,
> - .tRHW_min = 100000,
> - .tRHZ_max = 100000,
> - .tRLOH_min = 5000,
> - .tRP_min = 12000,
> - .tRR_min = 20000,
> - .tRST_max = 500000000,
> - .tWB_max = 100000,
> - .tWC_min = 25000,
> - .tWH_min = 10000,
> - .tWHR_min = 80000,
> - .tWP_min = 12000,
> - .tWW_min = 100000,
> + .type = NAND_SDR_IFACE,
> + .timings.sdr = {
> + .tADL_min = 70000,
> + .tALH_min = 5000,
> + .tALS_min = 10000,
> + .tAR_min = 10000,
> + .tCEA_max = 25000,
> + .tCEH_min = 20000,
> + .tCH_min = 5000,
> + .tCHZ_max = 30000,
> + .tCLH_min = 5000,
> + .tCLR_min = 10000,
> + .tCLS_min = 10000,
> + .tCOH_min = 15000,
> + .tCS_min = 20000,
> + .tDH_min = 5000,
> + .tDS_min = 10000,
> + .tFEAT_max = 1000000,
> + .tIR_min = 0,
> + .tITC_max = 1000000,
> + .tRC_min = 25000,
> + .tREA_max = 20000,
> + .tREH_min = 10000,
> + .tRHOH_min = 15000,
> + .tRHW_min = 100000,
> + .tRHZ_max = 100000,
> + .tRLOH_min = 5000,
> + .tRP_min = 12000,
> + .tRR_min = 20000,
> + .tRST_max = 500000000,
> + .tWB_max = 100000,
> + .tWC_min = 25000,
> + .tWH_min = 10000,
> + .tWHR_min = 80000,
> + .tWP_min = 12000,
> + .tWW_min = 100000,
> + },
> },
> /* Mode 5 */
> {
> - .tADL_min = 70000,
> - .tALH_min = 5000,
> - .tALS_min = 10000,
> - .tAR_min = 10000,
> - .tCEA_max = 25000,
> - .tCEH_min = 20000,
> - .tCH_min = 5000,
> - .tCHZ_max = 30000,
> - .tCLH_min = 5000,
> - .tCLR_min = 10000,
> - .tCLS_min = 10000,
> - .tCOH_min = 15000,
> - .tCS_min = 15000,
> - .tDH_min = 5000,
> - .tDS_min = 7000,
> - .tFEAT_max = 1000000,
> - .tIR_min = 0,
> - .tITC_max = 1000000,
> - .tRC_min = 20000,
> - .tREA_max = 16000,
> - .tREH_min = 7000,
> - .tRHOH_min = 15000,
> - .tRHW_min = 100000,
> - .tRHZ_max = 100000,
> - .tRLOH_min = 5000,
> - .tRP_min = 10000,
> - .tRR_min = 20000,
> - .tRST_max = 500000000,
> - .tWB_max = 100000,
> - .tWC_min = 20000,
> - .tWH_min = 7000,
> - .tWHR_min = 80000,
> - .tWP_min = 10000,
> - .tWW_min = 100000,
> + .type = NAND_SDR_IFACE,
> + .timings.sdr = {
> + .tADL_min = 70000,
> + .tALH_min = 5000,
> + .tALS_min = 10000,
> + .tAR_min = 10000,
> + .tCEA_max = 25000,
> + .tCEH_min = 20000,
> + .tCH_min = 5000,
> + .tCHZ_max = 30000,
> + .tCLH_min = 5000,
> + .tCLR_min = 10000,
> + .tCLS_min = 10000,
> + .tCOH_min = 15000,
> + .tCS_min = 15000,
> + .tDH_min = 5000,
> + .tDS_min = 7000,
> + .tFEAT_max = 1000000,
> + .tIR_min = 0,
> + .tITC_max = 1000000,
> + .tRC_min = 20000,
> + .tREA_max = 16000,
> + .tREH_min = 7000,
> + .tRHOH_min = 15000,
> + .tRHW_min = 100000,
> + .tRHZ_max = 100000,
> + .tRLOH_min = 5000,
> + .tRP_min = 10000,
> + .tRR_min = 20000,
> + .tRST_max = 500000000,
> + .tWB_max = 100000,
> + .tWC_min = 20000,
> + .tWH_min = 7000,
> + .tWHR_min = 80000,
> + .tWP_min = 10000,
> + .tWW_min = 100000,
> + },
> },
> };
>
> @@ -248,6 +266,20 @@ const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
> if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
> return ERR_PTR(-EINVAL);
>
> - return &onfi_sdr_timings[mode];
> + return &onfi_sdr_timings[mode].timings.sdr;
> }
> EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
> +
> +/**
> + * onfi_async_timing_mode_to_data_interface - [NAND Interface] Retrieve NAND
> + * data interface according to the given ONFI timing mode
> + * @mode: ONFI timing mode
> + */
> +const struct nand_data_interface *onfi_async_timing_mode_to_data_interface(int mode)
> +{
> + if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
> + return ERR_PTR(-EINVAL);
> +
> + return &onfi_sdr_timings[mode];
> +}
> +EXPORT_SYMBOL(onfi_async_timing_mode_to_data_interface);
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 19c73ef..a8bdf6c 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -1088,6 +1088,8 @@ static inline int jedec_feature(struct nand_chip *chip)
>
> /* get timing characteristics from ONFI timing mode. */
> const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
> +/* get data interface from ONFI timing mode. */
> +const struct nand_data_interface *onfi_async_timing_mode_to_data_interface(int mode);
>
> int nand_check_erased_ecc_chunk(void *data, int datalen,
> void *ecc, int ecclen,
next prev parent reply other threads:[~2016-09-06 11:27 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-06 10:39 [PATCH v2] mtd: nand: automate NAND timings selection Sascha Hauer
2016-09-06 10:39 ` [PATCH 1/7] mtd: nand: Create a NAND reset function Sascha Hauer
2016-09-06 11:18 ` Boris Brezillon
2016-09-06 13:02 ` Sascha Hauer
2016-09-06 13:06 ` Boris Brezillon
2016-09-06 10:39 ` [PATCH 2/7] mtd: nand: Introduce nand_data_interface Sascha Hauer
2016-09-06 11:21 ` Boris Brezillon
2016-09-06 13:34 ` Sascha Hauer
2016-09-06 13:46 ` Boris Brezillon
2016-09-06 14:09 ` Sascha Hauer
2016-09-06 10:39 ` [PATCH 3/7] mtd: nand: convert ONFI mode into data interface Sascha Hauer
2016-09-06 11:27 ` Boris Brezillon [this message]
2016-09-06 12:15 ` Boris Brezillon
2016-09-06 10:39 ` [PATCH 4/7] mtd: nand: automate NAND timings selection Sascha Hauer
2016-09-06 11:58 ` Boris Brezillon
2016-09-06 14:08 ` Sascha Hauer
2016-09-06 14:50 ` Boris Brezillon
2016-09-06 15:04 ` Sascha Hauer
2016-09-06 15:15 ` Boris Brezillon
2016-09-06 10:39 ` [PATCH 5/7] mtd: nand: sunxi: switch from manual to automated timing config Sascha Hauer
2016-09-06 12:01 ` Boris Brezillon
2016-09-06 10:39 ` [PATCH 6/7] mtd: nand: mxc: implement onfi get/set features Sascha Hauer
2016-09-06 12:05 ` Boris Brezillon
2016-09-06 12:47 ` Sascha Hauer
2016-09-06 12:52 ` Boris Brezillon
2016-09-06 10:39 ` [PATCH 7/7] mtd: nand: mxc: Add timing setup for v2 controllers Sascha Hauer
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