linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/6] arm64: sysreg: replace open-coded mrs_s/msr_s with {read,write}_sysreg_s
Date: Fri, 9 Sep 2016 13:40:07 +0100	[thread overview]
Message-ID: <20160909124007.GD10562@leverpostej> (raw)
In-Reply-To: <1473419765-3437-2-git-send-email-will.deacon@arm.com>

On Fri, Sep 09, 2016 at 12:16:00PM +0100, Will Deacon wrote:
> Similar to our {read,write}_sysreg accessors for architected, named
> system registers, this patch introduces {read,write}_sysreg_s variants
> that can take arbitrary sys_reg output and therefore access IMPDEF
> registers or registers that unsupported by binutils.
> 
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
>  arch/arm64/include/asm/cputype.h |  6 +-----
>  arch/arm64/include/asm/sysreg.h  | 16 ++++++++++++++++
>  2 files changed, 17 insertions(+), 5 deletions(-)

> +#define write_sysreg_s(v, r) do {					\
> +	u64 __val = (u64)v;					\
> +	asm volatile("msr_s " __stringify(r) ", %0"		\
> +		     : : "r" (__val));				\
> +} while (0)

As with my patches, can we please make write_sysreg_s allow the zero
register? i.e. use the "%x0" tempate and "rZ" constraint. The mrs_s asm
template should handle that correctly.

With that:

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Thanks,
Mark.

  reply	other threads:[~2016-09-09 12:40 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-09 11:15 [PATCH 0/6] Further NOP/sysreg cleanups Will Deacon
2016-09-09 11:16 ` [PATCH 1/6] arm64: sysreg: replace open-coded mrs_s/msr_s with {read, write}_sysreg_s Will Deacon
2016-09-09 12:40   ` Mark Rutland [this message]
2016-09-09 11:16 ` [PATCH 2/6] arm64: barriers: introduce nops and __nops macros for NOP sequences Will Deacon
2016-09-09 11:16 ` [PATCH 3/6] arm64: lse: convert lse alternatives NOP padding to use __nops Will Deacon
2016-09-09 11:16 ` [PATCH 4/6] arm64: KVM: Move GIC accessors to arch_gicv3.h Will Deacon
2016-09-09 11:16 ` [PATCH 5/6] irqchip/gic-v3: Convert arm64 GIC accessors to {read, write}_sysreg_s Will Deacon
2016-09-09 11:16 ` [PATCH 6/6] irqchip/gic-v3: Use nops macro for Cavium ThunderX erratum 23154 Will Deacon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160909124007.GD10562@leverpostej \
    --to=mark.rutland@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).