* [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes
@ 2016-09-15 6:57 Chen-Yu Tsai
2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Chen-Yu Tsai @ 2016-09-15 6:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently
introduced for 4.9. The issues were noticed while working on the display
pipeline for the A31/A31s. The second patch follows what Maxime has done
for the A33 CCU driver. The third issue was noticed while doing the first
patch.
I hope we can get this into 4.9 as well, either right in -rc1, or in a
later -rc.
Thanks!
Regards
ChenYu
Chen-Yu Tsai (3):
clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output
clocks
clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs
clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk
drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 44 ++++++++++++++++++++----------------
1 file changed, 24 insertions(+), 20 deletions(-)
--
2.9.3
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks 2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai @ 2016-09-15 6:57 ` Chen-Yu Tsai 2016-09-16 23:04 ` Stephen Boyd 2016-09-15 6:57 ` [PATCH 2/3] clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs Chen-Yu Tsai ` (2 subsequent siblings) 3 siblings, 1 reply; 9+ messages in thread From: Chen-Yu Tsai @ 2016-09-15 6:57 UTC (permalink / raw) To: linux-arm-kernel The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks to generate their dot clocks. To be able to generate a full range of possible clock rates, the parent PLL clock rates should also be changed. Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index f1d61faa5bd9..bb488e8baea8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -543,17 +543,19 @@ static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1", "pll-video0-2x", "pll-video1-2x", "pll-mipi" }; static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents, - 0x118, 24, 2, BIT(31), 0); + 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents, - 0x11c, 24, 2, BIT(31), 0); + 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT); static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1", "pll-video0-2x", "pll-video1-2x" }; static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, - 0x12c, 0, 4, 24, 3, BIT(31), 0); + 0x12c, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents, - 0x12c, 0, 4, 24, 3, BIT(31), 0); + 0x12c, 0, 4, 24, 3, BIT(31), + CLK_SET_RATE_PARENT); static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1", "pll9", "pll10", "pll-mipi", @@ -601,7 +603,8 @@ static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio", 0x148, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, - 0x150, 0, 4, 24, 2, BIT(31), 0); + 0x150, 0, 4, 24, 2, BIT(31), + CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0); @@ -624,10 +627,11 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160, CLK_IS_CRITICAL); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents, - 0x168, 16, 3, 24, 2, BIT(31), 0); + 0x168, 16, 3, 24, 2, BIT(31), + CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy", lcd_ch1_parents, 0x168, 0, 3, 8, 2, - BIT(15), 0); + BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy", lcd_ch1_parents, 0x168, 0, 3, 8, 2, BIT(15), 0); @@ -956,9 +960,9 @@ static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", "pll-periph", 1, 2, 0); static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", - "pll-video0", 1, 2, 0); + "pll-video0", 1, 2, CLK_SET_RATE_PARENT); static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x", - "pll-video1", 1, 2, 0); + "pll-video1", 1, 2, CLK_SET_RATE_PARENT); static struct clk_hw_onecell_data sun6i_a31_hw_clks = { .hws = { -- 2.9.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks 2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai @ 2016-09-16 23:04 ` Stephen Boyd 0 siblings, 0 replies; 9+ messages in thread From: Stephen Boyd @ 2016-09-16 23:04 UTC (permalink / raw) To: linux-arm-kernel On 09/15, Chen-Yu Tsai wrote: > The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks > to generate their dot clocks. To be able to generate a full range of > possible clock rates, the parent PLL clock rates should also be changed. > > Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs 2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai 2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai @ 2016-09-15 6:57 ` Chen-Yu Tsai 2016-09-15 6:57 ` [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk Chen-Yu Tsai 2016-09-15 8:34 ` [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Maxime Ripard 3 siblings, 0 replies; 9+ messages in thread From: Chen-Yu Tsai @ 2016-09-15 6:57 UTC (permalink / raw) To: linux-arm-kernel The PLLs have a "lock" bit in their configuration registers which indicate if the PLL has locked on to the requested clock rate. We check this bit in the .set_rate op. The PLL cannot lock on if it's not running, which might be a false positive (warning). Set the CLK_SET_RATE_UNGATE flag for all PLLs so whenever clk_set_rate is called on them, they get enabled and the "lock" check is really checking the PLL. Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index bb488e8baea8..ff0d621495fd 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -59,7 +59,7 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 0, 5, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", "osc24M", 0x010, @@ -71,7 +71,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x018, @@ -83,7 +83,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", "osc24M", 0x020, @@ -92,7 +92,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 0, 2, /* M */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", "osc24M", 0x028, @@ -101,7 +101,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", BIT(31), /* gate */ BIT(28), /* lock */ 2, /* post-div */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", "osc24M", 0x030, @@ -113,7 +113,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", "osc24M", 0x038, @@ -125,7 +125,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); /* * The MIPI PLL has 2 modes: "MIPI" and "HDMI". @@ -145,7 +145,7 @@ static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi", 21, 0, /* mux */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9", "osc24M", 0x044, @@ -157,7 +157,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9", 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10", "osc24M", 0x048, @@ -169,7 +169,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10", 297000000, /* frac rate 1 */ BIT(31), /* gate */ BIT(28), /* lock */ - 0); + CLK_SET_RATE_UNGATE); static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpu", "pll-cpu" }; -- 2.9.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk 2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai 2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai 2016-09-15 6:57 ` [PATCH 2/3] clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs Chen-Yu Tsai @ 2016-09-15 6:57 ` Chen-Yu Tsai 2016-09-16 23:04 ` Stephen Boyd 2016-09-15 8:34 ` [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Maxime Ripard 3 siblings, 1 reply; 9+ messages in thread From: Chen-Yu Tsai @ 2016-09-15 6:57 UTC (permalink / raw) To: linux-arm-kernel The register offset for the mipi-csi clk is off by 4, a copy paste error from the mipi-dsi clk. Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index ff0d621495fd..79596463e0d9 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -633,7 +633,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy", lcd_ch1_parents, 0x168, 0, 3, 8, 2, BIT(15), CLK_SET_RATE_PARENT); static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy", - lcd_ch1_parents, 0x168, 0, 3, 8, 2, + lcd_ch1_parents, 0x16c, 0, 3, 8, 2, BIT(15), 0); static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents, -- 2.9.3 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk 2016-09-15 6:57 ` [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk Chen-Yu Tsai @ 2016-09-16 23:04 ` Stephen Boyd 0 siblings, 0 replies; 9+ messages in thread From: Stephen Boyd @ 2016-09-16 23:04 UTC (permalink / raw) To: linux-arm-kernel On 09/15, Chen-Yu Tsai wrote: > The register offset for the mipi-csi clk is off by 4, a copy paste > error from the mipi-dsi clk. > > Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes 2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai ` (2 preceding siblings ...) 2016-09-15 6:57 ` [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk Chen-Yu Tsai @ 2016-09-15 8:34 ` Maxime Ripard 2016-09-15 23:11 ` Stephen Boyd 3 siblings, 1 reply; 9+ messages in thread From: Maxime Ripard @ 2016-09-15 8:34 UTC (permalink / raw) To: linux-arm-kernel Hi, On Thu, Sep 15, 2016 at 02:57:37PM +0800, Chen-Yu Tsai wrote: > Hi, > > Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently > introduced for 4.9. The issues were noticed while working on the display > pipeline for the A31/A31s. The second patch follows what Maxime has done > for the A33 CCU driver. The third issue was noticed while doing the first > patch. > > I hope we can get this into 4.9 as well, either right in -rc1, or in a > later -rc. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Stephen, could you apply those patches directly on top of my previous PR, or do you want me to send another one? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160915/9197698c/attachment.sig> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes 2016-09-15 8:34 ` [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Maxime Ripard @ 2016-09-15 23:11 ` Stephen Boyd 2016-09-18 20:30 ` Maxime Ripard 0 siblings, 1 reply; 9+ messages in thread From: Stephen Boyd @ 2016-09-15 23:11 UTC (permalink / raw) To: linux-arm-kernel On 09/15/2016 01:34 AM, Maxime Ripard wrote: > Hi, > > On Thu, Sep 15, 2016 at 02:57:37PM +0800, Chen-Yu Tsai wrote: >> Hi, >> >> Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently >> introduced for 4.9. The issues were noticed while working on the display >> pipeline for the A31/A31s. The second patch follows what Maxime has done >> for the A33 CCU driver. The third issue was noticed while doing the first >> patch. >> >> I hope we can get this into 4.9 as well, either right in -rc1, or in a >> later -rc. > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Stephen, could you apply those patches directly on top of my previous > PR, or do you want me to send another one? > I can apply directly to clk-next. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes 2016-09-15 23:11 ` Stephen Boyd @ 2016-09-18 20:30 ` Maxime Ripard 0 siblings, 0 replies; 9+ messages in thread From: Maxime Ripard @ 2016-09-18 20:30 UTC (permalink / raw) To: linux-arm-kernel On Thu, Sep 15, 2016 at 04:11:32PM -0700, Stephen Boyd wrote: > On 09/15/2016 01:34 AM, Maxime Ripard wrote: > > Hi, > > > > On Thu, Sep 15, 2016 at 02:57:37PM +0800, Chen-Yu Tsai wrote: > >> Hi, > >> > >> Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently > >> introduced for 4.9. The issues were noticed while working on the display > >> pipeline for the A31/A31s. The second patch follows what Maxime has done > >> for the A33 CCU driver. The third issue was noticed while doing the first > >> patch. > >> > >> I hope we can get this into 4.9 as well, either right in -rc1, or in a > >> later -rc. > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > > > Stephen, could you apply those patches directly on top of my previous > > PR, or do you want me to send another one? > > > > I can apply directly to clk-next. Awesome, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160918/1e59ebf6/attachment-0001.sig> ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-09-18 20:30 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-09-15 6:57 [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Chen-Yu Tsai 2016-09-15 6:57 ` [PATCH 1/3] clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks Chen-Yu Tsai 2016-09-16 23:04 ` Stephen Boyd 2016-09-15 6:57 ` [PATCH 2/3] clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs Chen-Yu Tsai 2016-09-15 6:57 ` [PATCH 3/3] clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk Chen-Yu Tsai 2016-09-16 23:04 ` Stephen Boyd 2016-09-15 8:34 ` [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes Maxime Ripard 2016-09-15 23:11 ` Stephen Boyd 2016-09-18 20:30 ` Maxime Ripard
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