From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
Date: Thu, 15 Sep 2016 17:20:45 +0100 [thread overview]
Message-ID: <20160915162044.GB19214@leverpostej> (raw)
In-Reply-To: <1473788797-10879-1-git-send-email-catalin.marinas@arm.com>
Hi Catalin,
On Tue, Sep 13, 2016 at 06:46:30PM +0100, Catalin Marinas wrote:
> This is the third version of the arm64 PAN emulation using TTBR0_EL1
> switching. The series has not yet included the alternative nop patches
> from Mark Rutland, nor the empty_zero_page from Ard B. This will be done
> in a subsequent version once 4.9-rc1 is out (which will include Mark's
> alternative nop patches).
> arch/arm64/Kconfig | 8 ++
> arch/arm64/include/asm/assembler.h | 33 +++++++
> arch/arm64/include/asm/cpufeature.h | 6 ++
> arch/arm64/include/asm/efi.h | 26 ++++-
> arch/arm64/include/asm/futex.h | 14 +--
> arch/arm64/include/asm/kernel-pgtable.h | 7 ++
> arch/arm64/include/asm/mmu_context.h | 51 +++++++---
> arch/arm64/include/asm/ptrace.h | 2 +
> arch/arm64/include/asm/thread_info.h | 3 +
> arch/arm64/include/asm/uaccess.h | 163 ++++++++++++++++++++++++++++++--
> arch/arm64/kernel/armv8_deprecated.c | 10 +-
> arch/arm64/kernel/asm-offsets.c | 3 +
> arch/arm64/kernel/cpufeature.c | 1 +
> arch/arm64/kernel/entry.S | 71 +++++++++++++-
> arch/arm64/kernel/head.S | 6 +-
> arch/arm64/kernel/setup.c | 9 ++
> arch/arm64/kernel/vmlinux.lds.S | 5 +
> arch/arm64/lib/clear_user.S | 8 +-
> arch/arm64/lib/copy_from_user.S | 8 +-
> arch/arm64/lib/copy_in_user.S | 8 +-
> arch/arm64/lib/copy_to_user.S | 8 +-
> arch/arm64/mm/context.c | 7 +-
> arch/arm64/mm/fault.c | 22 +++--
> arch/arm64/mm/proc.S | 11 +--
> arch/arm64/xen/hypercall.S | 19 ++++
> 25 files changed, 428 insertions(+), 81 deletions(-)
I don't seee traps.c there. Don't we need to fix up do_sysinstr() (which
performs raw cache maintenance ops on __user addresses) with
uaccess_{enable,disable}_not_uao()?
Likewise, how do we handle __flush_cache_user_range and
flush_icache_range? Some callers (e.g. __do_compat_cache_op) pass in
__user addresses.
I hope we have some tests lying around for those. ;)
Thanks,
Mark.
next prev parent reply other threads:[~2016-09-15 16:20 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-13 17:46 [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-09-13 17:46 ` [PATCH v3 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-09-15 15:10 ` Mark Rutland
2016-09-13 17:46 ` [PATCH v3 2/7] arm64: Factor out TTBR0_EL1 post-update workaround into a specific asm macro Catalin Marinas
2016-09-15 15:19 ` Mark Rutland
2016-09-13 17:46 ` [PATCH v3 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-09-13 20:45 ` [PATCH v3 3/7] arm64: Introduce uaccess_{disable,enable} " Kees Cook
2016-09-14 8:52 ` Mark Rutland
2016-09-14 16:27 ` [kernel-hardening] " Kees Cook
2016-09-13 17:46 ` [PATCH v3 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-09-14 16:45 ` Will Deacon
2016-09-13 17:46 ` [PATCH v3 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-09-16 11:33 ` Mark Rutland
2016-09-16 15:55 ` Catalin Marinas
2016-09-13 17:46 ` [PATCH v3 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-09-13 17:46 ` [PATCH v3 7/7] arm64: Enable CONFIG_ARM64_SW_TTBR0_PAN Catalin Marinas
2016-09-14 10:13 ` [PATCH v3 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Ard Biesheuvel
2016-09-14 10:27 ` Mark Rutland
2016-09-14 10:30 ` Ard Biesheuvel
2016-09-14 10:36 ` Mark Rutland
2016-09-14 10:48 ` Mark Rutland
2016-09-14 20:54 ` [kernel-hardening] " David Brown
2016-09-15 9:52 ` Catalin Marinas
2016-09-15 16:20 ` Mark Rutland [this message]
2016-09-15 16:41 ` Mark Rutland
2016-09-29 22:44 ` [kernel-hardening] " Sami Tolvanen
2016-09-30 18:42 ` Kees Cook
2016-10-27 14:54 ` Catalin Marinas
2016-10-27 21:23 ` Kees Cook
2016-10-14 21:44 ` Kees Cook
2016-10-15 14:35 ` Catalin Marinas
2016-10-16 2:04 ` Kees Cook
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