[PATCH v4 0/9] arm64: Allwinner A64 support based on sunxi-ng

[PATCH v4 0/9] arm64: Allwinner A64 support based on sunxi-ng

[Maxime Ripard]

Hi,

As it was in the first iteration, this is the A64 support based on the
new sunxi-ng clock framework.

The support for it is quite minimal at the moment, but it should be
fairly easy to add new devices, as most of the design is shared with
older SoCs.

Let me know what you think,
Maxime

Changes from v3:
  - Fix patch split

Changes from v2:
  - Added pull-ups on the Pine64 i2c bus
  - Removed the PMU since it doesn't work
  - Refactored the sunxi-ng framework to deal with the specifities of
    the A64 CCU, especially in terms of minimum factors.
  - Fixed a few things in the CCU driver: added CLK_SET_RATE PARENT
    flags, fixed some mux width, etc.
  - Converted the CCU driver to a platform driver
  - Added the DRAM reset line
  - Added IDs for the USB muxes (even though we're not using them yet)

Changes from v1:
  - Split the A64 CCU support out of the H3 driver
  - Added the PMU support
  - Removed the clocks node
  - Rebased on top of current sunxi/clk-for-4.9 branch

Andre Przywara (3):
  arm64: dts: add Allwinner A64 SoC .dtsi
  Documentation: devicetree: add vendor prefix for Pine64
  arm64: dts: add Pine64 support

Maxime Ripard (6):
  clk: sunxi-ng: Rename the internal structures
  clk: sunxi-ng: Remove the use of rational computations
  clk: sunxi-ng: Finish to convert to structures for arguments
  clk: sunxi-ng: Add minimums for all the relevant structures and clocks
  clk: sunxi-ng: Implement minimum for multipliers
  clk: sunxi-ng: Add A64 clocks

 Documentation/devicetree/bindings/arm/sunxi.txt          |   1 +-
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt    |   1 +-
 Documentation/devicetree/bindings/vendor-prefixes.txt    |   1 +-
 MAINTAINERS                                              |   1 +-
 arch/arm64/boot/dts/Makefile                             |   1 +-
 arch/arm64/boot/dts/allwinner/Makefile                   |   5 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts |  50 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts      |  74 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi            | 263 ++-
 drivers/clk/sunxi-ng/Kconfig                             |  14 +-
 drivers/clk/sunxi-ng/Makefile                            |   1 +-
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c                    | 918 ++++++++-
 drivers/clk/sunxi-ng/ccu-sun50i-a64.h                    |  72 +-
 drivers/clk/sunxi-ng/ccu_div.h                           |   6 +-
 drivers/clk/sunxi-ng/ccu_frac.c                          |  12 +-
 drivers/clk/sunxi-ng/ccu_frac.h                          |  14 +-
 drivers/clk/sunxi-ng/ccu_mp.h                            |   4 +-
 drivers/clk/sunxi-ng/ccu_mult.c                          |  33 +-
 drivers/clk/sunxi-ng/ccu_mult.h                          |  17 +-
 drivers/clk/sunxi-ng/ccu_nk.c                            |  43 +-
 drivers/clk/sunxi-ng/ccu_nk.h                            |   4 +-
 drivers/clk/sunxi-ng/ccu_nkm.c                           |  45 +-
 drivers/clk/sunxi-ng/ccu_nkm.h                           |   6 +-
 drivers/clk/sunxi-ng/ccu_nkmp.c                          |  55 +-
 drivers/clk/sunxi-ng/ccu_nkmp.h                          |   8 +-
 drivers/clk/sunxi-ng/ccu_nm.c                            |  58 +-
 drivers/clk/sunxi-ng/ccu_nm.h                            |   6 +-
 include/dt-bindings/clock/sun50i-a64-ccu.h               | 134 +-
 include/dt-bindings/reset/sun50i-a64-ccu.h               |  98 +-
 29 files changed, 1824 insertions(+), 121 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
 create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h

-- 
git-series 0.8.10

[PATCH v4 1/9] clk: sunxi-ng: Rename the internal structures

[Maxime Ripard]

Rename the structures meant to be embedded in other structures to make it
consistent with the mux structure name

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu_div.h  |  6 +++---
 drivers/clk/sunxi-ng/ccu_frac.c | 12 ++++++------
 drivers/clk/sunxi-ng/ccu_frac.h | 14 +++++++-------
 drivers/clk/sunxi-ng/ccu_mp.h   |  4 ++--
 drivers/clk/sunxi-ng/ccu_mult.h |  4 ++--
 drivers/clk/sunxi-ng/ccu_nk.h   |  4 ++--
 drivers/clk/sunxi-ng/ccu_nkm.h  |  6 +++---
 drivers/clk/sunxi-ng/ccu_nkmp.h |  8 ++++----
 drivers/clk/sunxi-ng/ccu_nm.h   |  6 +++---
 9 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index 34c338832c0d..06540f7cf41c 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -20,7 +20,7 @@
 #include "ccu_mux.h"
 
 /**
- * struct _ccu_div - Internal divider description
+ * struct ccu_div_internal - Internal divider description
  * @shift: Bit offset of the divider in its register
  * @width: Width of the divider field in its register
  * @max: Maximum value allowed for that divider. This is the
@@ -36,7 +36,7 @@
  * It is basically a wrapper around the clk_divider functions
  * arguments.
  */
-struct _ccu_div {
+struct ccu_div_internal {
 	u8			shift;
 	u8			width;
 
@@ -78,7 +78,7 @@ struct _ccu_div {
 struct ccu_div {
 	u32			enable;
 
-	struct _ccu_div		div;
+	struct ccu_div_internal		div;
 	struct ccu_mux_internal	mux;
 	struct ccu_common	common;
 };
diff --git a/drivers/clk/sunxi-ng/ccu_frac.c b/drivers/clk/sunxi-ng/ccu_frac.c
index 5c4b10cd15b5..8b5eb7756bf7 100644
--- a/drivers/clk/sunxi-ng/ccu_frac.c
+++ b/drivers/clk/sunxi-ng/ccu_frac.c
@@ -14,7 +14,7 @@
 #include "ccu_frac.h"
 
 bool ccu_frac_helper_is_enabled(struct ccu_common *common,
-				struct _ccu_frac *cf)
+				struct ccu_frac_internal *cf)
 {
 	if (!(common->features & CCU_FEATURE_FRACTIONAL))
 		return false;
@@ -23,7 +23,7 @@ bool ccu_frac_helper_is_enabled(struct ccu_common *common,
 }
 
 void ccu_frac_helper_enable(struct ccu_common *common,
-			    struct _ccu_frac *cf)
+			    struct ccu_frac_internal *cf)
 {
 	unsigned long flags;
 	u32 reg;
@@ -38,7 +38,7 @@ void ccu_frac_helper_enable(struct ccu_common *common,
 }
 
 void ccu_frac_helper_disable(struct ccu_common *common,
-			     struct _ccu_frac *cf)
+			     struct ccu_frac_internal *cf)
 {
 	unsigned long flags;
 	u32 reg;
@@ -53,7 +53,7 @@ void ccu_frac_helper_disable(struct ccu_common *common,
 }
 
 bool ccu_frac_helper_has_rate(struct ccu_common *common,
-			      struct _ccu_frac *cf,
+			      struct ccu_frac_internal *cf,
 			      unsigned long rate)
 {
 	if (!(common->features & CCU_FEATURE_FRACTIONAL))
@@ -63,7 +63,7 @@ bool ccu_frac_helper_has_rate(struct ccu_common *common,
 }
 
 unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
-					struct _ccu_frac *cf)
+					struct ccu_frac_internal *cf)
 {
 	u32 reg;
 
@@ -84,7 +84,7 @@ unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
 }
 
 int ccu_frac_helper_set_rate(struct ccu_common *common,
-			     struct _ccu_frac *cf,
+			     struct ccu_frac_internal *cf,
 			     unsigned long rate)
 {
 	unsigned long flags;
diff --git a/drivers/clk/sunxi-ng/ccu_frac.h b/drivers/clk/sunxi-ng/ccu_frac.h
index e4c670b1cdfe..7b1ee380156f 100644
--- a/drivers/clk/sunxi-ng/ccu_frac.h
+++ b/drivers/clk/sunxi-ng/ccu_frac.h
@@ -18,7 +18,7 @@
 
 #include "ccu_common.h"
 
-struct _ccu_frac {
+struct ccu_frac_internal {
 	u32		enable;
 	u32		select;
 
@@ -33,21 +33,21 @@ struct _ccu_frac {
 	}
 
 bool ccu_frac_helper_is_enabled(struct ccu_common *common,
-				struct _ccu_frac *cf);
+				struct ccu_frac_internal *cf);
 void ccu_frac_helper_enable(struct ccu_common *common,
-			    struct _ccu_frac *cf);
+			    struct ccu_frac_internal *cf);
 void ccu_frac_helper_disable(struct ccu_common *common,
-			     struct _ccu_frac *cf);
+			     struct ccu_frac_internal *cf);
 
 bool ccu_frac_helper_has_rate(struct ccu_common *common,
-			      struct _ccu_frac *cf,
+			      struct ccu_frac_internal *cf,
 			      unsigned long rate);
 
 unsigned long ccu_frac_helper_read_rate(struct ccu_common *common,
-					struct _ccu_frac *cf);
+					struct ccu_frac_internal *cf);
 
 int ccu_frac_helper_set_rate(struct ccu_common *common,
-			     struct _ccu_frac *cf,
+			     struct ccu_frac_internal *cf,
 			     unsigned long rate);
 
 #endif /* _CCU_FRAC_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h
index edf9215ea8cc..915625e97d98 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.h
+++ b/drivers/clk/sunxi-ng/ccu_mp.h
@@ -29,8 +29,8 @@
 struct ccu_mp {
 	u32			enable;
 
-	struct _ccu_div		m;
-	struct _ccu_div		p;
+	struct ccu_div_internal		m;
+	struct ccu_div_internal		p;
 	struct ccu_mux_internal	mux;
 	struct ccu_common	common;
 };
diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
index 5d2c8dc14073..113780b7558e 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.h
+++ b/drivers/clk/sunxi-ng/ccu_mult.h
@@ -4,7 +4,7 @@
 #include "ccu_common.h"
 #include "ccu_mux.h"
 
-struct _ccu_mult {
+struct ccu_mult_internal {
 	u8	shift;
 	u8	width;
 };
@@ -18,7 +18,7 @@ struct _ccu_mult {
 struct ccu_mult {
 	u32			enable;
 
-	struct _ccu_mult	mult;
+	struct ccu_mult_internal	mult;
 	struct ccu_mux_internal	mux;
 	struct ccu_common	common;
 };
diff --git a/drivers/clk/sunxi-ng/ccu_nk.h b/drivers/clk/sunxi-ng/ccu_nk.h
index 4b52da0c29fe..437836b80696 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.h
+++ b/drivers/clk/sunxi-ng/ccu_nk.h
@@ -30,8 +30,8 @@ struct ccu_nk {
 	u32			enable;
 	u32			lock;
 
-	struct _ccu_mult	n;
-	struct _ccu_mult	k;
+	struct ccu_mult_internal	n;
+	struct ccu_mult_internal	k;
 
 	unsigned int		fixed_post_div;
 
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index 35493fddd8ab..34580894f4d1 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -29,9 +29,9 @@ struct ccu_nkm {
 	u32			enable;
 	u32			lock;
 
-	struct _ccu_mult	n;
-	struct _ccu_mult	k;
-	struct _ccu_div		m;
+	struct ccu_mult_internal	n;
+	struct ccu_mult_internal	k;
+	struct ccu_div_internal		m;
 	struct ccu_mux_internal	mux;
 
 	struct ccu_common	common;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.h b/drivers/clk/sunxi-ng/ccu_nkmp.h
index 5adb0c92a614..a82facbc6144 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.h
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.h
@@ -29,10 +29,10 @@ struct ccu_nkmp {
 	u32			enable;
 	u32			lock;
 
-	struct _ccu_mult	n;
-	struct _ccu_mult	k;
-	struct _ccu_div		m;
-	struct _ccu_div		p;
+	struct ccu_mult_internal	n;
+	struct ccu_mult_internal	k;
+	struct ccu_div_internal		m;
+	struct ccu_div_internal		p;
 
 	struct ccu_common	common;
 };
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index 0b7bcd33a2df..e87fd186da78 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -30,9 +30,9 @@ struct ccu_nm {
 	u32			enable;
 	u32			lock;
 
-	struct _ccu_mult	n;
-	struct _ccu_div		m;
-	struct _ccu_frac	frac;
+	struct ccu_mult_internal	n;
+	struct ccu_div_internal		m;
+	struct ccu_frac_internal	frac;
 
 	struct ccu_common	common;
 };
-- 
git-series 0.8.10

[linux-sunxi] [PATCH v4 1/9] clk: sunxi-ng: Rename the internal structures

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Rename the structures meant to be embedded in other structures to make it
> consistent with the mux structure name
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[linux-sunxi] [PATCH v4 1/9] clk: sunxi-ng: Rename the internal structures

[Maxime Ripard]

On Thu, Oct 20, 2016 at 10:27:48PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Rename the structures meant to be embedded in other structures to make it
> > consistent with the mux structure name
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 2/9] clk: sunxi-ng: Remove the use of rational computations

[Maxime Ripard]

While the rational library works great, it doesn't really allow us to add
more constraints, like the minimum.

Remove that in order to be able to deal with the constraints we'll need.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/Kconfig    |  3 +--
 drivers/clk/sunxi-ng/ccu_nkm.c  | 31 +++++++++-----------
 drivers/clk/sunxi-ng/ccu_nkmp.c | 45 +++++++++++++---------------
 drivers/clk/sunxi-ng/ccu_nm.c   | 54 +++++++++++++++++++++++++---------
 4 files changed, 78 insertions(+), 55 deletions(-)

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 254d9526c018..1b4c55a53d7a 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -35,17 +35,14 @@ config SUNXI_CCU_NK
 
 config SUNXI_CCU_NKM
 	bool
-	select RATIONAL
 	select SUNXI_CCU_GATE
 
 config SUNXI_CCU_NKMP
 	bool
-	select RATIONAL
 	select SUNXI_CCU_GATE
 
 config SUNXI_CCU_NM
 	bool
-	select RATIONAL
 	select SUNXI_CCU_FRAC
 	select SUNXI_CCU_GATE
 
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 059fdc3b4f96..0b08d000eb38 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/rational.h>
 
 #include "ccu_gate.h"
 #include "ccu_nkm.h"
@@ -28,21 +27,21 @@ static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
 	unsigned long _n, _k, _m;
 
 	for (_k = 1; _k <= nkm->max_k; _k++) {
-		unsigned long tmp_rate;
-
-		rational_best_approximation(rate / _k, parent,
-					    nkm->max_n, nkm->max_m, &_n, &_m);
-
-		tmp_rate = parent * _n * _k / _m;
-
-		if (tmp_rate > rate)
-			continue;
-
-		if ((rate - tmp_rate) < (rate - best_rate)) {
-			best_rate = tmp_rate;
-			best_n = _n;
-			best_k = _k;
-			best_m = _m;
+		for (_n = 1; _n <= nkm->max_n; _n++) {
+			for (_m = 1; _n <= nkm->max_m; _m++) {
+				unsigned long tmp_rate;
+
+				tmp_rate = parent * _n * _k / _m;
+
+				if (tmp_rate > rate)
+					continue;
+				if ((rate - tmp_rate) < (rate - best_rate)) {
+					best_rate = tmp_rate;
+					best_n = _n;
+					best_k = _k;
+					best_m = _m;
+				}
+			}
 		}
 	}
 
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 9769dee99511..4b457d8cce11 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -9,16 +9,15 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/rational.h>
 
 #include "ccu_gate.h"
 #include "ccu_nkmp.h"
 
 struct _ccu_nkmp {
-	unsigned long	n, max_n;
-	unsigned long	k, max_k;
-	unsigned long	m, max_m;
-	unsigned long	p, max_p;
+	unsigned long	n, min_n, max_n;
+	unsigned long	k, min_k, max_k;
+	unsigned long	m, min_m, max_m;
+	unsigned long	p, min_p, max_p;
 };
 
 static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
@@ -29,24 +28,24 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
 	unsigned long _n, _k, _m, _p;
 
 	for (_k = 1; _k <= nkmp->max_k; _k++) {
-		for (_p = 1; _p <= nkmp->max_p; _p <<= 1) {
-			unsigned long tmp_rate;
-
-			rational_best_approximation(rate / _k, parent / _p,
-						    nkmp->max_n, nkmp->max_m,
-						    &_n, &_m);
-
-			tmp_rate = parent * _n * _k / (_m * _p);
-
-			if (tmp_rate > rate)
-				continue;
-
-			if ((rate - tmp_rate) < (rate - best_rate)) {
-				best_rate = tmp_rate;
-				best_n = _n;
-				best_k = _k;
-				best_m = _m;
-				best_p = _p;
+		for (_n = 1; _n <= nkm->max_n; _n++) {
+			for (_m = 1; _n <= nkm->max_m; _m++) {
+				for (_p = 1; _p <= nkmp->max_p; _p <<= 1) {
+					unsigned long tmp_rate;
+
+					tmp_rate = parent * _n * _k / (_m * _p);
+
+					if (tmp_rate > rate)
+						continue;
+
+					if ((rate - tmp_rate) < (rate - best_rate)) {
+						best_rate = tmp_rate;
+						best_n = _n;
+						best_k = _k;
+						best_m = _m;
+						best_p = _p;
+					}
+				}
 			}
 		}
 	}
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index b61bdd8c7a7f..c6d652289320 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -9,12 +9,42 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/rational.h>
 
 #include "ccu_frac.h"
 #include "ccu_gate.h"
 #include "ccu_nm.h"
 
+struct _ccu_nm {
+	unsigned long	n, max_n;
+	unsigned long	m, max_m;
+};
+
+static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
+			     struct _ccu_nm *nm)
+{
+	unsigned long best_rate = 0;
+	unsigned long best_n = 0, best_m = 0;
+	unsigned long _n, _m;
+
+	for (_n = 1; _n <= nm->max_n; _n++) {
+		for (_m = 1; _n <= nm->max_m; _m++) {
+			unsigned long tmp_rate = parent * _n  / _m;
+
+			if (tmp_rate > rate)
+				continue;
+
+			if ((rate - tmp_rate) < (rate - best_rate)) {
+				best_rate = tmp_rate;
+				best_n = _n;
+				best_m = _m;
+			}
+		}
+	}
+
+	nm->n = best_n;
+	nm->m = best_m;
+}
+
 static void ccu_nm_disable(struct clk_hw *hw)
 {
 	struct ccu_nm *nm = hw_to_ccu_nm(hw);
@@ -61,24 +91,22 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
 			      unsigned long *parent_rate)
 {
 	struct ccu_nm *nm = hw_to_ccu_nm(hw);
-	unsigned long max_n, max_m;
-	unsigned long n, m;
+	struct _ccu_nm _nm;
 
-	max_n = 1 << nm->n.width;
-	max_m = nm->m.max ?: 1 << nm->m.width;
+	_nm.max_n = 1 << nm->n.width;
+	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
 
-	rational_best_approximation(rate, *parent_rate, max_n, max_m, &n, &m);
+	ccu_nm_find_best(*parent_rate, rate, &_nm);
 
-	return *parent_rate * n / m;
+	return *parent_rate * _nm.n / _nm.m;
 }
 
 static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
 			   unsigned long parent_rate)
 {
 	struct ccu_nm *nm = hw_to_ccu_nm(hw);
+	struct _ccu_nm _nm;
 	unsigned long flags;
-	unsigned long max_n, max_m;
-	unsigned long n, m;
 	u32 reg;
 
 	if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
@@ -86,10 +114,10 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
 	else
 		ccu_frac_helper_disable(&nm->common, &nm->frac);
 
-	max_n = 1 << nm->n.width;
-	max_m = nm->m.max ?: 1 << nm->m.width;
+	_nm.max_n = 1 << nm->n.width;
+	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
 
-	rational_best_approximation(rate, parent_rate, max_n, max_m, &n, &m);
+	ccu_nm_find_best(parent_rate, rate, &_nm);
 
 	spin_lock_irqsave(nm->common.lock, flags);
 
@@ -97,7 +125,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
 	reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift);
 	reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift);
 
-	writel(reg | ((m - 1) << nm->m.shift) | ((n - 1) << nm->n.shift),
+	writel(reg | ((_nm.m - 1) << nm->m.shift) | ((_nm.n - 1) << nm->n.shift),
 	       nm->common.base + nm->common.reg);
 
 	spin_unlock_irqrestore(nm->common.lock, flags);
-- 
git-series 0.8.10

[PATCH v4 2/9] clk: sunxi-ng: Remove the use of rational computations

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> While the rational library works great, it doesn't really allow us to add
> more constraints, like the minimum.
>
> Remove that in order to be able to deal with the constraints we'll need.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi-ng/Kconfig    |  3 +--
>  drivers/clk/sunxi-ng/ccu_nkm.c  | 31 +++++++++-----------
>  drivers/clk/sunxi-ng/ccu_nkmp.c | 45 +++++++++++++---------------
>  drivers/clk/sunxi-ng/ccu_nm.c   | 54 +++++++++++++++++++++++++---------
>  4 files changed, 78 insertions(+), 55 deletions(-)
>

[...]

> diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> index 9769dee99511..4b457d8cce11 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> @@ -9,16 +9,15 @@
>   */
>
>  #include <linux/clk-provider.h>
> -#include <linux/rational.h>
>
>  #include "ccu_gate.h"
>  #include "ccu_nkmp.h"
>
>  struct _ccu_nkmp {
> -       unsigned long   n, max_n;
> -       unsigned long   k, max_k;
> -       unsigned long   m, max_m;
> -       unsigned long   p, max_p;
> +       unsigned long   n, min_n, max_n;
> +       unsigned long   k, min_k, max_k;
> +       unsigned long   m, min_m, max_m;
> +       unsigned long   p, min_p, max_p;

Wrong patch? Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v4 2/9] clk: sunxi-ng: Remove the use of rational computations

[Maxime Ripard]

On Thu, Oct 20, 2016 at 10:30:36PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > While the rational library works great, it doesn't really allow us to add
> > more constraints, like the minimum.
> >
> > Remove that in order to be able to deal with the constraints we'll need.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/clk/sunxi-ng/Kconfig    |  3 +--
> >  drivers/clk/sunxi-ng/ccu_nkm.c  | 31 +++++++++-----------
> >  drivers/clk/sunxi-ng/ccu_nkmp.c | 45 +++++++++++++---------------
> >  drivers/clk/sunxi-ng/ccu_nm.c   | 54 +++++++++++++++++++++++++---------
> >  4 files changed, 78 insertions(+), 55 deletions(-)
> >
> 
> [...]
> 
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > index 9769dee99511..4b457d8cce11 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > @@ -9,16 +9,15 @@
> >   */
> >
> >  #include <linux/clk-provider.h>
> > -#include <linux/rational.h>
> >
> >  #include "ccu_gate.h"
> >  #include "ccu_nkmp.h"
> >
> >  struct _ccu_nkmp {
> > -       unsigned long   n, max_n;
> > -       unsigned long   k, max_k;
> > -       unsigned long   m, max_m;
> > -       unsigned long   p, max_p;
> > +       unsigned long   n, min_n, max_n;
> > +       unsigned long   k, min_k, max_k;
> > +       unsigned long   m, min_m, max_m;
> > +       unsigned long   p, min_p, max_p;
> 
> Wrong patch? Otherwise,
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Indeed, fixed and applied.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 3/9] clk: sunxi-ng: Finish to convert to structures for arguments

[Maxime Ripard]

Some clocks still use an explicit list of arguments, which make it a bit
more tedious to add new parameters.

Convert those over to a structure pointer argument to add as many
arguments as possible without having to many noise in our patches, or a
very long list of arguments.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu_mult.c | 28 +++++++++++++++++-------
 drivers/clk/sunxi-ng/ccu_nk.c   | 39 +++++++++++++++++++---------------
 2 files changed, 42 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 010e9424691d..32a1964439a2 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -13,10 +13,20 @@
 #include "ccu_gate.h"
 #include "ccu_mult.h"
 
+struct _ccu_mult {
+	unsigned long	mult, max;
+};
+
 static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
-			       unsigned int max_n, unsigned int *n)
+			       struct _ccu_mult *mult)
 {
-	*n = rate / parent;
+	int _mult;
+
+	_mult = rate / parent;
+	if (_mult > mult->max)
+		_mult = mult->max;
+
+	mult->mult = _mult;
 }
 
 static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
@@ -25,11 +35,12 @@ static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
 					void *data)
 {
 	struct ccu_mult *cm = data;
-	unsigned int n;
+	struct _ccu_mult _cm;
 
-	ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n);
+	_cm.max = 1 << cm->mult.width;
+	ccu_mult_find_best(parent_rate, rate, &_cm);
 
-	return parent_rate * n;
+	return parent_rate * _cm.mult;
 }
 
 static void ccu_mult_disable(struct clk_hw *hw)
@@ -83,21 +94,22 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
 			   unsigned long parent_rate)
 {
 	struct ccu_mult *cm = hw_to_ccu_mult(hw);
+	struct _ccu_mult _cm;
 	unsigned long flags;
-	unsigned int n;
 	u32 reg;
 
 	ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
 						&parent_rate);
 
-	ccu_mult_find_best(parent_rate, rate, 1 << cm->mult.width, &n);
+	_cm.max = 1 << cm->mult.width;
+	ccu_mult_find_best(parent_rate, rate, &_cm);
 
 	spin_lock_irqsave(cm->common.lock, flags);
 
 	reg = readl(cm->common.base + cm->common.reg);
 	reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift);
 
-	writel(reg | ((n - 1) << cm->mult.shift),
+	writel(reg | ((_cm.mult - 1) << cm->mult.shift),
 	       cm->common.base + cm->common.reg);
 
 	spin_unlock_irqrestore(cm->common.lock, flags);
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index d6fafb397489..e7e2e75618ef 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -9,21 +9,24 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/rational.h>
 
 #include "ccu_gate.h"
 #include "ccu_nk.h"
 
+struct _ccu_nk {
+	unsigned long	n, max_n;
+	unsigned long	k, max_k;
+};
+
 static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
-			     unsigned int max_n, unsigned int max_k,
-			     unsigned int *n, unsigned int *k)
+			     struct _ccu_nk *nk)
 {
 	unsigned long best_rate = 0;
 	unsigned int best_k = 0, best_n = 0;
 	unsigned int _k, _n;
 
-	for (_k = 1; _k <= max_k; _k++) {
-		for (_n = 1; _n <= max_n; _n++) {
+	for (_k = 1; _k <= nk->max_k; _k++) {
+		for (_n = 1; _n <= nk->max_n; _n++) {
 			unsigned long tmp_rate = parent * _n * _k;
 
 			if (tmp_rate > rate)
@@ -37,8 +40,8 @@ static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
 		}
 	}
 
-	*k = best_k;
-	*n = best_n;
+	nk->k = best_k;
+	nk->n = best_n;
 }
 
 static void ccu_nk_disable(struct clk_hw *hw)
@@ -89,16 +92,17 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
 			      unsigned long *parent_rate)
 {
 	struct ccu_nk *nk = hw_to_ccu_nk(hw);
-	unsigned int n, k;
+	struct _ccu_nk _nk;
 
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate *= nk->fixed_post_div;
 
-	ccu_nk_find_best(*parent_rate, rate,
-			 1 << nk->n.width, 1 << nk->k.width,
-			 &n, &k);
+	_nk.max_n = 1 << nk->n.width;
+	_nk.max_k = 1 << nk->k.width;
+
+	ccu_nk_find_best(*parent_rate, rate, &_nk);
+	rate = *parent_rate * _nk.n * _nk.k;
 
-	rate = *parent_rate * n * k;
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate = rate / nk->fixed_post_div;
 
@@ -110,15 +114,16 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
 {
 	struct ccu_nk *nk = hw_to_ccu_nk(hw);
 	unsigned long flags;
-	unsigned int n, k;
+	struct _ccu_nk _nk;
 	u32 reg;
 
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate = rate * nk->fixed_post_div;
 
-	ccu_nk_find_best(parent_rate, rate,
-			 1 << nk->n.width, 1 << nk->k.width,
-			 &n, &k);
+	_nk.max_n = 1 << nk->n.width;
+	_nk.max_k = 1 << nk->k.width;
+
+	ccu_nk_find_best(parent_rate, rate, &_nk);
 
 	spin_lock_irqsave(nk->common.lock, flags);
 
@@ -126,7 +131,7 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
 	reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
 	reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
 
-	writel(reg | ((k - 1) << nk->k.shift) | ((n - 1) << nk->n.shift),
+	writel(reg | ((_nk.k - 1) << nk->k.shift) | ((_nk.n - 1) << nk->n.shift),
 	       nk->common.base + nk->common.reg);
 
 	spin_unlock_irqrestore(nk->common.lock, flags);
-- 
git-series 0.8.10

[PATCH v4 3/9] clk: sunxi-ng: Finish to convert to structures for arguments

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some clocks still use an explicit list of arguments, which make it a bit
> more tedious to add new parameters.
>
> Convert those over to a structure pointer argument to add as many
> arguments as possible without having to many noise in our patches, or a
> very long list of arguments.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v4 3/9] clk: sunxi-ng: Finish to convert to structures for arguments

[Maxime Ripard]

On Thu, Oct 20, 2016 at 10:35:18PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Some clocks still use an explicit list of arguments, which make it a bit
> > more tedious to add new parameters.
> >
> > Convert those over to a structure pointer argument to add as many
> > arguments as possible without having to many noise in our patches, or a
> > very long list of arguments.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks

[Maxime Ripard]

Modify the current clocks we have to be able to specify the minimum for
each clocks we support, just like we support the max.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu_mult.c |  7 ++++++-
 drivers/clk/sunxi-ng/ccu_nk.c   | 12 ++++++++----
 drivers/clk/sunxi-ng/ccu_nkm.c  | 18 ++++++++++++------
 drivers/clk/sunxi-ng/ccu_nkmp.c | 16 ++++++++++++----
 drivers/clk/sunxi-ng/ccu_nm.c   | 12 ++++++++----
 5 files changed, 46 insertions(+), 19 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 32a1964439a2..6a02ffee5386 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -14,7 +14,7 @@
 #include "ccu_mult.h"
 
 struct _ccu_mult {
-	unsigned long	mult, max;
+	unsigned long	mult, min, max;
 };
 
 static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
@@ -23,6 +23,9 @@ static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
 	int _mult;
 
 	_mult = rate / parent;
+	if (_mult < mult->min)
+		_mult = mult->min;
+
 	if (_mult > mult->max)
 		_mult = mult->max;
 
@@ -37,6 +40,7 @@ static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
 	struct ccu_mult *cm = data;
 	struct _ccu_mult _cm;
 
+	_cm.min = 1;
 	_cm.max = 1 << cm->mult.width;
 	ccu_mult_find_best(parent_rate, rate, &_cm);
 
@@ -101,6 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
 	ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
 						&parent_rate);
 
+	_cm.min = 1;
 	_cm.max = 1 << cm->mult.width;
 	ccu_mult_find_best(parent_rate, rate, &_cm);
 
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index e7e2e75618ef..a42d870ba0ef 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -14,8 +14,8 @@
 #include "ccu_nk.h"
 
 struct _ccu_nk {
-	unsigned long	n, max_n;
-	unsigned long	k, max_k;
+	unsigned long	n, min_n, max_n;
+	unsigned long	k, min_k, max_k;
 };
 
 static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
@@ -25,8 +25,8 @@ static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
 	unsigned int best_k = 0, best_n = 0;
 	unsigned int _k, _n;
 
-	for (_k = 1; _k <= nk->max_k; _k++) {
-		for (_n = 1; _n <= nk->max_n; _n++) {
+	for (_k = nk->min_k; _k <= nk->max_k; _k++) {
+		for (_n = nk->min_n; _n <= nk->max_n; _n++) {
 			unsigned long tmp_rate = parent * _n * _k;
 
 			if (tmp_rate > rate)
@@ -97,7 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate *= nk->fixed_post_div;
 
+	_nk.min_n = 1;
 	_nk.max_n = 1 << nk->n.width;
+	_nk.min_k = 1;
 	_nk.max_k = 1 << nk->k.width;
 
 	ccu_nk_find_best(*parent_rate, rate, &_nk);
@@ -120,7 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate = rate * nk->fixed_post_div;
 
+	_nk.min_n = 1;
 	_nk.max_n = 1 << nk->n.width;
+	_nk.min_k = 1;
 	_nk.max_k = 1 << nk->k.width;
 
 	ccu_nk_find_best(parent_rate, rate, &_nk);
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 0b08d000eb38..b2a5fccf2f8c 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -14,9 +14,9 @@
 #include "ccu_nkm.h"
 
 struct _ccu_nkm {
-	unsigned long	n, max_n;
-	unsigned long	k, max_k;
-	unsigned long	m, max_m;
+	unsigned long	n, min_n, max_n;
+	unsigned long	k, min_k, max_k;
+	unsigned long	m, min_m, max_m;
 };
 
 static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
@@ -26,9 +26,9 @@ static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
 	unsigned long best_n = 0, best_k = 0, best_m = 0;
 	unsigned long _n, _k, _m;
 
-	for (_k = 1; _k <= nkm->max_k; _k++) {
-		for (_n = 1; _n <= nkm->max_n; _n++) {
-			for (_m = 1; _n <= nkm->max_m; _m++) {
+	for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
+		for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
+			for (_m = nkm->min_m; _n <= nkm->max_m; _m++) {
 				unsigned long tmp_rate;
 
 				tmp_rate = parent * _n * _k / _m;
@@ -100,8 +100,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
 	struct ccu_nkm *nkm = data;
 	struct _ccu_nkm _nkm;
 
+	_nkm.min_n = 1;
 	_nkm.max_n = 1 << nkm->n.width;
+	_nkm.min_k = 1;
 	_nkm.max_k = 1 << nkm->k.width;
+	_nkm.min_m = 1;
 	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
 
 	ccu_nkm_find_best(parent_rate, rate, &_nkm);
@@ -126,8 +129,11 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long flags;
 	u32 reg;
 
+	_nkm.min_n = 1;
 	_nkm.max_n = 1 << nkm->n.width;
+	_nkm.min_k = 1;
 	_nkm.max_k = 1 << nkm->k.width;
+	_nkm.min_m = 1;
 	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
 
 	ccu_nkm_find_best(parent_rate, rate, &_nkm);
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 4b457d8cce11..2c1398192e48 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -27,10 +27,10 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
 	unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
 	unsigned long _n, _k, _m, _p;
 
-	for (_k = 1; _k <= nkmp->max_k; _k++) {
-		for (_n = 1; _n <= nkm->max_n; _n++) {
-			for (_m = 1; _n <= nkm->max_m; _m++) {
-				for (_p = 1; _p <= nkmp->max_p; _p <<= 1) {
+	for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
+		for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
+			for (_m = nkmp->min_m; _n <= nkmp->max_m; _m++) {
+				for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
 					unsigned long tmp_rate;
 
 					tmp_rate = parent * _n * _k / (_m * _p);
@@ -107,9 +107,13 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
 	struct _ccu_nkmp _nkmp;
 
+	_nkmp.min_n = 1;
 	_nkmp.max_n = 1 << nkmp->n.width;
+	_nkmp.min_k = 1;
 	_nkmp.max_k = 1 << nkmp->k.width;
+	_nkmp.min_m = 1;
 	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
+	_nkmp.min_p = 1;
 	_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
 
 	ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
@@ -125,9 +129,13 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long flags;
 	u32 reg;
 
+	_nkmp.min_n = 1;
 	_nkmp.max_n = 1 << nkmp->n.width;
+	_nkmp.min_k = 1;
 	_nkmp.max_k = 1 << nkmp->k.width;
+	_nkmp.min_m = 1;
 	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
+	_nkmp.min_p = 1;
 	_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
 
 	ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index c6d652289320..2a190bc032a9 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -15,8 +15,8 @@
 #include "ccu_nm.h"
 
 struct _ccu_nm {
-	unsigned long	n, max_n;
-	unsigned long	m, max_m;
+	unsigned long	n, min_n, max_n;
+	unsigned long	m, min_m, max_m;
 };
 
 static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
@@ -26,8 +26,8 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
 	unsigned long best_n = 0, best_m = 0;
 	unsigned long _n, _m;
 
-	for (_n = 1; _n <= nm->max_n; _n++) {
-		for (_m = 1; _n <= nm->max_m; _m++) {
+	for (_n = nm->min_n; _n <= nm->max_n; _n++) {
+		for (_m = nm->min_m; _n <= nm->max_m; _m++) {
 			unsigned long tmp_rate = parent * _n  / _m;
 
 			if (tmp_rate > rate)
@@ -93,7 +93,9 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct ccu_nm *nm = hw_to_ccu_nm(hw);
 	struct _ccu_nm _nm;
 
+	_nm.min_n = 1;
 	_nm.max_n = 1 << nm->n.width;
+	_nm.min_m = 1;
 	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
 
 	ccu_nm_find_best(*parent_rate, rate, &_nm);
@@ -114,7 +116,9 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
 	else
 		ccu_frac_helper_disable(&nm->common, &nm->frac);
 
+	_nm.min_n = 1;
 	_nm.max_n = 1 << nm->n.width;
+	_nm.min_m = 1;
 	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
 
 	ccu_nm_find_best(parent_rate, rate, &_nm);
-- 
git-series 0.8.10

[PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Modify the current clocks we have to be able to specify the minimum for
> each clocks we support, just like we support the max.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Including the bits from patch 2.

[PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks

[Maxime Ripard]

On Thu, Oct 20, 2016 at 11:04:18PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Modify the current clocks we have to be able to specify the minimum for
> > each clocks we support, just like we support the max.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> 
> Including the bits from patch 2.

Applied with those bits merged in this patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks

[André Przywara]

Salut,

On 11/10/16 15:28, Maxime Ripard wrote:
> Modify the current clocks we have to be able to specify the minimum for
> each clocks we support, just like we support the max.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi-ng/ccu_mult.c |  7 ++++++-
>  drivers/clk/sunxi-ng/ccu_nk.c   | 12 ++++++++----
>  drivers/clk/sunxi-ng/ccu_nkm.c  | 18 ++++++++++++------
>  drivers/clk/sunxi-ng/ccu_nkmp.c | 16 ++++++++++++----
>  drivers/clk/sunxi-ng/ccu_nm.c   | 12 ++++++++----
>  5 files changed, 46 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> index 32a1964439a2..6a02ffee5386 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.c
> +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> @@ -14,7 +14,7 @@
>  #include "ccu_mult.h"
>  
>  struct _ccu_mult {
> -	unsigned long	mult, max;
> +	unsigned long	mult, min, max;
>  };
>  
>  static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
> @@ -23,6 +23,9 @@ static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
>  	int _mult;
>  
>  	_mult = rate / parent;
> +	if (_mult < mult->min)
> +		_mult = mult->min;
> +
>  	if (_mult > mult->max)
>  		_mult = mult->max;
>  
> @@ -37,6 +40,7 @@ static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
>  	struct ccu_mult *cm = data;
>  	struct _ccu_mult _cm;
>  
> +	_cm.min = 1;
>  	_cm.max = 1 << cm->mult.width;
>  	ccu_mult_find_best(parent_rate, rate, &_cm);
>  
> @@ -101,6 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
>  	ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
>  						&parent_rate);
>  
> +	_cm.min = 1;
>  	_cm.max = 1 << cm->mult.width;
>  	ccu_mult_find_best(parent_rate, rate, &_cm);
>  
> diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> index e7e2e75618ef..a42d870ba0ef 100644
> --- a/drivers/clk/sunxi-ng/ccu_nk.c
> +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> @@ -14,8 +14,8 @@
>  #include "ccu_nk.h"
>  
>  struct _ccu_nk {
> -	unsigned long	n, max_n;
> -	unsigned long	k, max_k;
> +	unsigned long	n, min_n, max_n;
> +	unsigned long	k, min_k, max_k;
>  };
>  
>  static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
> @@ -25,8 +25,8 @@ static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
>  	unsigned int best_k = 0, best_n = 0;
>  	unsigned int _k, _n;
>  
> -	for (_k = 1; _k <= nk->max_k; _k++) {
> -		for (_n = 1; _n <= nk->max_n; _n++) {
> +	for (_k = nk->min_k; _k <= nk->max_k; _k++) {
> +		for (_n = nk->min_n; _n <= nk->max_n; _n++) {
>  			unsigned long tmp_rate = parent * _n * _k;
>  
>  			if (tmp_rate > rate)
> @@ -97,7 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
>  	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
>  		rate *= nk->fixed_post_div;
>  
> +	_nk.min_n = 1;
>  	_nk.max_n = 1 << nk->n.width;
> +	_nk.min_k = 1;
>  	_nk.max_k = 1 << nk->k.width;
>  
>  	ccu_nk_find_best(*parent_rate, rate, &_nk);
> @@ -120,7 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
>  	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
>  		rate = rate * nk->fixed_post_div;
>  
> +	_nk.min_n = 1;
>  	_nk.max_n = 1 << nk->n.width;
> +	_nk.min_k = 1;
>  	_nk.max_k = 1 << nk->k.width;
>  
>  	ccu_nk_find_best(parent_rate, rate, &_nk);
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index 0b08d000eb38..b2a5fccf2f8c 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -14,9 +14,9 @@
>  #include "ccu_nkm.h"
>  
>  struct _ccu_nkm {
> -	unsigned long	n, max_n;
> -	unsigned long	k, max_k;
> -	unsigned long	m, max_m;
> +	unsigned long	n, min_n, max_n;
> +	unsigned long	k, min_k, max_k;
> +	unsigned long	m, min_m, max_m;
>  };
>  
>  static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
> @@ -26,9 +26,9 @@ static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
>  	unsigned long best_n = 0, best_k = 0, best_m = 0;
>  	unsigned long _n, _k, _m;
>  
> -	for (_k = 1; _k <= nkm->max_k; _k++) {
> -		for (_n = 1; _n <= nkm->max_n; _n++) {
> -			for (_m = 1; _n <= nkm->max_m; _m++) {
> +	for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
> +		for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
> +			for (_m = nkm->min_m; _n <= nkm->max_m; _m++) {

should be _m in the condition

>  				unsigned long tmp_rate;
>  
>  				tmp_rate = parent * _n * _k / _m;
> @@ -100,8 +100,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>  	struct ccu_nkm *nkm = data;
>  	struct _ccu_nkm _nkm;
>  
> +	_nkm.min_n = 1;
>  	_nkm.max_n = 1 << nkm->n.width;
> +	_nkm.min_k = 1;
>  	_nkm.max_k = 1 << nkm->k.width;
> +	_nkm.min_m = 1;
>  	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
>  
>  	ccu_nkm_find_best(parent_rate, rate, &_nkm);
> @@ -126,8 +129,11 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
>  	unsigned long flags;
>  	u32 reg;
>  
> +	_nkm.min_n = 1;
>  	_nkm.max_n = 1 << nkm->n.width;
> +	_nkm.min_k = 1;
>  	_nkm.max_k = 1 << nkm->k.width;
> +	_nkm.min_m = 1;
>  	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
>  
>  	ccu_nkm_find_best(parent_rate, rate, &_nkm);
> diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> index 4b457d8cce11..2c1398192e48 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> @@ -27,10 +27,10 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
>  	unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
>  	unsigned long _n, _k, _m, _p;
>  
> -	for (_k = 1; _k <= nkmp->max_k; _k++) {
> -		for (_n = 1; _n <= nkm->max_n; _n++) {
> -			for (_m = 1; _n <= nkm->max_m; _m++) {
> -				for (_p = 1; _p <= nkmp->max_p; _p <<= 1) {
> +	for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
> +		for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
> +			for (_m = nkmp->min_m; _n <= nkmp->max_m; _m++) {

Same here: _m <= ...

> +				for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
>  					unsigned long tmp_rate;
>  
>  					tmp_rate = parent * _n * _k / (_m * _p);
> @@ -107,9 +107,13 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
>  	struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
>  	struct _ccu_nkmp _nkmp;
>  
> +	_nkmp.min_n = 1;
>  	_nkmp.max_n = 1 << nkmp->n.width;
> +	_nkmp.min_k = 1;
>  	_nkmp.max_k = 1 << nkmp->k.width;
> +	_nkmp.min_m = 1;
>  	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> +	_nkmp.min_p = 1;
>  	_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
>  
>  	ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
> @@ -125,9 +129,13 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
>  	unsigned long flags;
>  	u32 reg;
>  
> +	_nkmp.min_n = 1;
>  	_nkmp.max_n = 1 << nkmp->n.width;
> +	_nkmp.min_k = 1;
>  	_nkmp.max_k = 1 << nkmp->k.width;
> +	_nkmp.min_m = 1;
>  	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> +	_nkmp.min_p = 1;
>  	_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
>  
>  	ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
> diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> index c6d652289320..2a190bc032a9 100644
> --- a/drivers/clk/sunxi-ng/ccu_nm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> @@ -15,8 +15,8 @@
>  #include "ccu_nm.h"
>  
>  struct _ccu_nm {
> -	unsigned long	n, max_n;
> -	unsigned long	m, max_m;
> +	unsigned long	n, min_n, max_n;
> +	unsigned long	m, min_m, max_m;
>  };
>  
>  static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
> @@ -26,8 +26,8 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
>  	unsigned long best_n = 0, best_m = 0;
>  	unsigned long _n, _m;
>  
> -	for (_n = 1; _n <= nm->max_n; _n++) {
> -		for (_m = 1; _n <= nm->max_m; _m++) {
> +	for (_n = nm->min_n; _n <= nm->max_n; _n++) {
> +		for (_m = nm->min_m; _n <= nm->max_m; _m++) {

And here: _m <= ...

Interestingly those typos were already in the code before.

Lets hope I don't dream of m's and k's tonight.

Cheers,
Andre.

>  			unsigned long tmp_rate = parent * _n  / _m;
>  
>  			if (tmp_rate > rate)
> @@ -93,7 +93,9 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
>  	struct ccu_nm *nm = hw_to_ccu_nm(hw);
>  	struct _ccu_nm _nm;
>  
> +	_nm.min_n = 1;
>  	_nm.max_n = 1 << nm->n.width;
> +	_nm.min_m = 1;
>  	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
>  
>  	ccu_nm_find_best(*parent_rate, rate, &_nm);
> @@ -114,7 +116,9 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
>  	else
>  		ccu_frac_helper_disable(&nm->common, &nm->frac);
>  
> +	_nm.min_n = 1;
>  	_nm.max_n = 1 << nm->n.width;
> +	_nm.min_m = 1;
>  	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
>  
>  	ccu_nm_find_best(parent_rate, rate, &_nm);
> 

[PATCH v4 4/9] clk: sunxi-ng: Add minimums for all the relevant structures and clocks

[Maxime Ripard]

On Fri, Oct 21, 2016 at 11:57:11PM +0100, Andr? Przywara wrote:
> Salut,
> 
> On 11/10/16 15:28, Maxime Ripard wrote:
> > Modify the current clocks we have to be able to specify the minimum for
> > each clocks we support, just like we support the max.
> > 
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/clk/sunxi-ng/ccu_mult.c |  7 ++++++-
> >  drivers/clk/sunxi-ng/ccu_nk.c   | 12 ++++++++----
> >  drivers/clk/sunxi-ng/ccu_nkm.c  | 18 ++++++++++++------
> >  drivers/clk/sunxi-ng/ccu_nkmp.c | 16 ++++++++++++----
> >  drivers/clk/sunxi-ng/ccu_nm.c   | 12 ++++++++----
> >  5 files changed, 46 insertions(+), 19 deletions(-)
> > 
> > diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> > index 32a1964439a2..6a02ffee5386 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mult.c
> > +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> > @@ -14,7 +14,7 @@
> >  #include "ccu_mult.h"
> >  
> >  struct _ccu_mult {
> > -	unsigned long	mult, max;
> > +	unsigned long	mult, min, max;
> >  };
> >  
> >  static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
> > @@ -23,6 +23,9 @@ static void ccu_mult_find_best(unsigned long parent, unsigned long rate,
> >  	int _mult;
> >  
> >  	_mult = rate / parent;
> > +	if (_mult < mult->min)
> > +		_mult = mult->min;
> > +
> >  	if (_mult > mult->max)
> >  		_mult = mult->max;
> >  
> > @@ -37,6 +40,7 @@ static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
> >  	struct ccu_mult *cm = data;
> >  	struct _ccu_mult _cm;
> >  
> > +	_cm.min = 1;
> >  	_cm.max = 1 << cm->mult.width;
> >  	ccu_mult_find_best(parent_rate, rate, &_cm);
> >  
> > @@ -101,6 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
> >  	ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
> >  						&parent_rate);
> >  
> > +	_cm.min = 1;
> >  	_cm.max = 1 << cm->mult.width;
> >  	ccu_mult_find_best(parent_rate, rate, &_cm);
> >  
> > diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> > index e7e2e75618ef..a42d870ba0ef 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nk.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> > @@ -14,8 +14,8 @@
> >  #include "ccu_nk.h"
> >  
> >  struct _ccu_nk {
> > -	unsigned long	n, max_n;
> > -	unsigned long	k, max_k;
> > +	unsigned long	n, min_n, max_n;
> > +	unsigned long	k, min_k, max_k;
> >  };
> >  
> >  static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
> > @@ -25,8 +25,8 @@ static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
> >  	unsigned int best_k = 0, best_n = 0;
> >  	unsigned int _k, _n;
> >  
> > -	for (_k = 1; _k <= nk->max_k; _k++) {
> > -		for (_n = 1; _n <= nk->max_n; _n++) {
> > +	for (_k = nk->min_k; _k <= nk->max_k; _k++) {
> > +		for (_n = nk->min_n; _n <= nk->max_n; _n++) {
> >  			unsigned long tmp_rate = parent * _n * _k;
> >  
> >  			if (tmp_rate > rate)
> > @@ -97,7 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
> >  	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> >  		rate *= nk->fixed_post_div;
> >  
> > +	_nk.min_n = 1;
> >  	_nk.max_n = 1 << nk->n.width;
> > +	_nk.min_k = 1;
> >  	_nk.max_k = 1 << nk->k.width;
> >  
> >  	ccu_nk_find_best(*parent_rate, rate, &_nk);
> > @@ -120,7 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
> >  	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> >  		rate = rate * nk->fixed_post_div;
> >  
> > +	_nk.min_n = 1;
> >  	_nk.max_n = 1 << nk->n.width;
> > +	_nk.min_k = 1;
> >  	_nk.max_k = 1 << nk->k.width;
> >  
> >  	ccu_nk_find_best(parent_rate, rate, &_nk);
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > index 0b08d000eb38..b2a5fccf2f8c 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > @@ -14,9 +14,9 @@
> >  #include "ccu_nkm.h"
> >  
> >  struct _ccu_nkm {
> > -	unsigned long	n, max_n;
> > -	unsigned long	k, max_k;
> > -	unsigned long	m, max_m;
> > +	unsigned long	n, min_n, max_n;
> > +	unsigned long	k, min_k, max_k;
> > +	unsigned long	m, min_m, max_m;
> >  };
> >  
> >  static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
> > @@ -26,9 +26,9 @@ static void ccu_nkm_find_best(unsigned long parent, unsigned long rate,
> >  	unsigned long best_n = 0, best_k = 0, best_m = 0;
> >  	unsigned long _n, _k, _m;
> >  
> > -	for (_k = 1; _k <= nkm->max_k; _k++) {
> > -		for (_n = 1; _n <= nkm->max_n; _n++) {
> > -			for (_m = 1; _n <= nkm->max_m; _m++) {
> > +	for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
> > +		for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
> > +			for (_m = nkm->min_m; _n <= nkm->max_m; _m++) {
> 
> should be _m in the condition
> 
> >  				unsigned long tmp_rate;
> >  
> >  				tmp_rate = parent * _n * _k / _m;
> > @@ -100,8 +100,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> >  	struct ccu_nkm *nkm = data;
> >  	struct _ccu_nkm _nkm;
> >  
> > +	_nkm.min_n = 1;
> >  	_nkm.max_n = 1 << nkm->n.width;
> > +	_nkm.min_k = 1;
> >  	_nkm.max_k = 1 << nkm->k.width;
> > +	_nkm.min_m = 1;
> >  	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> >  
> >  	ccu_nkm_find_best(parent_rate, rate, &_nkm);
> > @@ -126,8 +129,11 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
> >  	unsigned long flags;
> >  	u32 reg;
> >  
> > +	_nkm.min_n = 1;
> >  	_nkm.max_n = 1 << nkm->n.width;
> > +	_nkm.min_k = 1;
> >  	_nkm.max_k = 1 << nkm->k.width;
> > +	_nkm.min_m = 1;
> >  	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> >  
> >  	ccu_nkm_find_best(parent_rate, rate, &_nkm);
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > index 4b457d8cce11..2c1398192e48 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > @@ -27,10 +27,10 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
> >  	unsigned long best_n = 0, best_k = 0, best_m = 0, best_p = 0;
> >  	unsigned long _n, _k, _m, _p;
> >  
> > -	for (_k = 1; _k <= nkmp->max_k; _k++) {
> > -		for (_n = 1; _n <= nkm->max_n; _n++) {
> > -			for (_m = 1; _n <= nkm->max_m; _m++) {
> > -				for (_p = 1; _p <= nkmp->max_p; _p <<= 1) {
> > +	for (_k = nkmp->min_k; _k <= nkmp->max_k; _k++) {
> > +		for (_n = nkmp->min_n; _n <= nkmp->max_n; _n++) {
> > +			for (_m = nkmp->min_m; _n <= nkmp->max_m; _m++) {
> 
> Same here: _m <= ...
> 
> > +				for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
> >  					unsigned long tmp_rate;
> >  
> >  					tmp_rate = parent * _n * _k / (_m * _p);
> > @@ -107,9 +107,13 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
> >  	struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
> >  	struct _ccu_nkmp _nkmp;
> >  
> > +	_nkmp.min_n = 1;
> >  	_nkmp.max_n = 1 << nkmp->n.width;
> > +	_nkmp.min_k = 1;
> >  	_nkmp.max_k = 1 << nkmp->k.width;
> > +	_nkmp.min_m = 1;
> >  	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> > +	_nkmp.min_p = 1;
> >  	_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
> >  
> >  	ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
> > @@ -125,9 +129,13 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
> >  	unsigned long flags;
> >  	u32 reg;
> >  
> > +	_nkmp.min_n = 1;
> >  	_nkmp.max_n = 1 << nkmp->n.width;
> > +	_nkmp.min_k = 1;
> >  	_nkmp.max_k = 1 << nkmp->k.width;
> > +	_nkmp.min_m = 1;
> >  	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> > +	_nkmp.min_p = 1;
> >  	_nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1);
> >  
> >  	ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
> > diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> > index c6d652289320..2a190bc032a9 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> > @@ -15,8 +15,8 @@
> >  #include "ccu_nm.h"
> >  
> >  struct _ccu_nm {
> > -	unsigned long	n, max_n;
> > -	unsigned long	m, max_m;
> > +	unsigned long	n, min_n, max_n;
> > +	unsigned long	m, min_m, max_m;
> >  };
> >  
> >  static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
> > @@ -26,8 +26,8 @@ static void ccu_nm_find_best(unsigned long parent, unsigned long rate,
> >  	unsigned long best_n = 0, best_m = 0;
> >  	unsigned long _n, _m;
> >  
> > -	for (_n = 1; _n <= nm->max_n; _n++) {
> > -		for (_m = 1; _n <= nm->max_m; _m++) {
> > +	for (_n = nm->min_n; _n <= nm->max_n; _n++) {
> > +		for (_m = nm->min_m; _n <= nm->max_m; _m++) {
> 
> And here: _m <= ...
> 
> Interestingly those typos were already in the code before.

Good catches, I've amended the commit in my branch (since I apparently
forgot to push...). Thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 5/9] clk: sunxi-ng: Implement minimum for multipliers

[Maxime Ripard]

Allow the CCU drivers to specify a multiplier for their clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/ccu_mult.c |  2 +-
 drivers/clk/sunxi-ng/ccu_mult.h | 13 +++++++++----
 drivers/clk/sunxi-ng/ccu_nk.c   |  8 ++++----
 drivers/clk/sunxi-ng/ccu_nkm.c  |  8 ++++----
 drivers/clk/sunxi-ng/ccu_nkmp.c |  4 ++--
 drivers/clk/sunxi-ng/ccu_nm.c   |  2 +-
 6 files changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 6a02ffee5386..678b6cb49f01 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -105,7 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
 	ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
 						&parent_rate);
 
-	_cm.min = 1;
+	_cm.min = cm->mult.min;
 	_cm.max = 1 << cm->mult.width;
 	ccu_mult_find_best(parent_rate, rate, &_cm);
 
diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
index 113780b7558e..c1a2134bdc71 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.h
+++ b/drivers/clk/sunxi-ng/ccu_mult.h
@@ -7,14 +7,19 @@
 struct ccu_mult_internal {
 	u8	shift;
 	u8	width;
+	u8	min;
 };
 
-#define _SUNXI_CCU_MULT(_shift, _width)		\
-	{					\
-		.shift	= _shift,		\
-		.width	= _width,		\
+#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min)	\
+	{						\
+		.shift	= _shift,			\
+		.width	= _width,			\
+		.min	= _min,				\
 	}
 
+#define _SUNXI_CCU_MULT(_shift, _width)		\
+	_SUNXI_CCU_MULT_MIN(_shift, _width, 1)
+
 struct ccu_mult {
 	u32			enable;
 
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index a42d870ba0ef..eaf0fdf78d2b 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -97,9 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate *= nk->fixed_post_div;
 
-	_nk.min_n = 1;
+	_nk.min_n = nk->n.min;
 	_nk.max_n = 1 << nk->n.width;
-	_nk.min_k = 1;
+	_nk.min_k = nk->k.min;
 	_nk.max_k = 1 << nk->k.width;
 
 	ccu_nk_find_best(*parent_rate, rate, &_nk);
@@ -122,9 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
 		rate = rate * nk->fixed_post_div;
 
-	_nk.min_n = 1;
+	_nk.min_n = nk->n.min;
 	_nk.max_n = 1 << nk->n.width;
-	_nk.min_k = 1;
+	_nk.min_k = nk->k.min;
 	_nk.max_k = 1 << nk->k.width;
 
 	ccu_nk_find_best(parent_rate, rate, &_nk);
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index b2a5fccf2f8c..715b49211ddb 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -100,9 +100,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
 	struct ccu_nkm *nkm = data;
 	struct _ccu_nkm _nkm;
 
-	_nkm.min_n = 1;
+	_nkm.min_n = nkm->n.min;
 	_nkm.max_n = 1 << nkm->n.width;
-	_nkm.min_k = 1;
+	_nkm.min_n = nkm->k.min;
 	_nkm.max_k = 1 << nkm->k.width;
 	_nkm.min_m = 1;
 	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
@@ -129,9 +129,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned long flags;
 	u32 reg;
 
-	_nkm.min_n = 1;
+	_nkm.min_n = nkm->n.min;
 	_nkm.max_n = 1 << nkm->n.width;
-	_nkm.min_k = 1;
+	_nkm.min_n = nkm->k.min;
 	_nkm.max_k = 1 << nkm->k.width;
 	_nkm.min_m = 1;
 	_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 2c1398192e48..7968e0bac5db 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -107,9 +107,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
 	struct _ccu_nkmp _nkmp;
 
-	_nkmp.min_n = 1;
+	_nkmp.min_n = nkmp->n.min;
 	_nkmp.max_n = 1 << nkmp->n.width;
-	_nkmp.min_k = 1;
+	_nkmp.min_n = nkmp->k.min;
 	_nkmp.max_k = 1 << nkmp->k.width;
 	_nkmp.min_m = 1;
 	_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 2a190bc032a9..b1f3f0e8899d 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -93,7 +93,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
 	struct ccu_nm *nm = hw_to_ccu_nm(hw);
 	struct _ccu_nm _nm;
 
-	_nm.min_n = 1;
+	_nm.min_n = nm->n.min;
 	_nm.max_n = 1 << nm->n.width;
 	_nm.min_m = 1;
 	_nm.max_m = nm->m.max ?: 1 << nm->m.width;
-- 
git-series 0.8.10

[PATCH v4 5/9] clk: sunxi-ng: Implement minimum for multipliers

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Allow the CCU drivers to specify a multiplier for their clocks.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  drivers/clk/sunxi-ng/ccu_mult.c |  2 +-
>  drivers/clk/sunxi-ng/ccu_mult.h | 13 +++++++++----
>  drivers/clk/sunxi-ng/ccu_nk.c   |  8 ++++----
>  drivers/clk/sunxi-ng/ccu_nkm.c  |  8 ++++----
>  drivers/clk/sunxi-ng/ccu_nkmp.c |  4 ++--
>  drivers/clk/sunxi-ng/ccu_nm.c   |  2 +-
>  6 files changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> index 6a02ffee5386..678b6cb49f01 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.c
> +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> @@ -105,7 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
>         ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
>                                                 &parent_rate);
>
> -       _cm.min = 1;
> +       _cm.min = cm->mult.min;
>         _cm.max = 1 << cm->mult.width;
>         ccu_mult_find_best(parent_rate, rate, &_cm);
>
> diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> index 113780b7558e..c1a2134bdc71 100644
> --- a/drivers/clk/sunxi-ng/ccu_mult.h
> +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> @@ -7,14 +7,19 @@
>  struct ccu_mult_internal {
>         u8      shift;
>         u8      width;
> +       u8      min;
>  };
>
> -#define _SUNXI_CCU_MULT(_shift, _width)                \
> -       {                                       \
> -               .shift  = _shift,               \
> -               .width  = _width,               \
> +#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min)      \
> +       {                                               \
> +               .shift  = _shift,                       \
> +               .width  = _width,                       \
> +               .min    = _min,                         \
>         }
>
> +#define _SUNXI_CCU_MULT(_shift, _width)                \
> +       _SUNXI_CCU_MULT_MIN(_shift, _width, 1)
> +
>  struct ccu_mult {
>         u32                     enable;
>
> diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> index a42d870ba0ef..eaf0fdf78d2b 100644
> --- a/drivers/clk/sunxi-ng/ccu_nk.c
> +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> @@ -97,9 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
>         if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
>                 rate *= nk->fixed_post_div;
>
> -       _nk.min_n = 1;
> +       _nk.min_n = nk->n.min;
>         _nk.max_n = 1 << nk->n.width;
> -       _nk.min_k = 1;
> +       _nk.min_k = nk->k.min;
>         _nk.max_k = 1 << nk->k.width;
>
>         ccu_nk_find_best(*parent_rate, rate, &_nk);
> @@ -122,9 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
>         if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
>                 rate = rate * nk->fixed_post_div;
>
> -       _nk.min_n = 1;
> +       _nk.min_n = nk->n.min;
>         _nk.max_n = 1 << nk->n.width;
> -       _nk.min_k = 1;
> +       _nk.min_k = nk->k.min;
>         _nk.max_k = 1 << nk->k.width;
>
>         ccu_nk_find_best(parent_rate, rate, &_nk);
> diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> index b2a5fccf2f8c..715b49211ddb 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> @@ -100,9 +100,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
>         struct ccu_nkm *nkm = data;
>         struct _ccu_nkm _nkm;
>
> -       _nkm.min_n = 1;
> +       _nkm.min_n = nkm->n.min;
>         _nkm.max_n = 1 << nkm->n.width;
> -       _nkm.min_k = 1;
> +       _nkm.min_n = nkm->k.min;

Typo here.

>         _nkm.max_k = 1 << nkm->k.width;
>         _nkm.min_m = 1;
>         _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> @@ -129,9 +129,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
>         unsigned long flags;
>         u32 reg;
>
> -       _nkm.min_n = 1;
> +       _nkm.min_n = nkm->n.min;
>         _nkm.max_n = 1 << nkm->n.width;
> -       _nkm.min_k = 1;
> +       _nkm.min_n = nkm->k.min;

And here.

>         _nkm.max_k = 1 << nkm->k.width;
>         _nkm.min_m = 1;
>         _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> index 2c1398192e48..7968e0bac5db 100644
> --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> @@ -107,9 +107,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
>         struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
>         struct _ccu_nkmp _nkmp;
>
> -       _nkmp.min_n = 1;
> +       _nkmp.min_n = nkmp->n.min;
>         _nkmp.max_n = 1 << nkmp->n.width;
> -       _nkmp.min_k = 1;
> +       _nkmp.min_n = nkmp->k.min;

And here.

>         _nkmp.max_k = 1 << nkmp->k.width;
>         _nkmp.min_m = 1;
>         _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> index 2a190bc032a9..b1f3f0e8899d 100644
> --- a/drivers/clk/sunxi-ng/ccu_nm.c
> +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> @@ -93,7 +93,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
>         struct ccu_nm *nm = hw_to_ccu_nm(hw);
>         struct _ccu_nm _nm;
>
> -       _nm.min_n = 1;
> +       _nm.min_n = nm->n.min;
>         _nm.max_n = 1 << nm->n.width;
>         _nm.min_m = 1;
>         _nm.max_m = nm->m.max ?: 1 << nm->m.width;
> --
> git-series 0.8.10

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH v4 5/9] clk: sunxi-ng: Implement minimum for multipliers

[Maxime Ripard]

On Thu, Oct 20, 2016 at 11:06:21PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Allow the CCU drivers to specify a multiplier for their clocks.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  drivers/clk/sunxi-ng/ccu_mult.c |  2 +-
> >  drivers/clk/sunxi-ng/ccu_mult.h | 13 +++++++++----
> >  drivers/clk/sunxi-ng/ccu_nk.c   |  8 ++++----
> >  drivers/clk/sunxi-ng/ccu_nkm.c  |  8 ++++----
> >  drivers/clk/sunxi-ng/ccu_nkmp.c |  4 ++--
> >  drivers/clk/sunxi-ng/ccu_nm.c   |  2 +-
> >  6 files changed, 21 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
> > index 6a02ffee5386..678b6cb49f01 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mult.c
> > +++ b/drivers/clk/sunxi-ng/ccu_mult.c
> > @@ -105,7 +105,7 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
> >         ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1,
> >                                                 &parent_rate);
> >
> > -       _cm.min = 1;
> > +       _cm.min = cm->mult.min;
> >         _cm.max = 1 << cm->mult.width;
> >         ccu_mult_find_best(parent_rate, rate, &_cm);
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
> > index 113780b7558e..c1a2134bdc71 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mult.h
> > +++ b/drivers/clk/sunxi-ng/ccu_mult.h
> > @@ -7,14 +7,19 @@
> >  struct ccu_mult_internal {
> >         u8      shift;
> >         u8      width;
> > +       u8      min;
> >  };
> >
> > -#define _SUNXI_CCU_MULT(_shift, _width)                \
> > -       {                                       \
> > -               .shift  = _shift,               \
> > -               .width  = _width,               \
> > +#define _SUNXI_CCU_MULT_MIN(_shift, _width, _min)      \
> > +       {                                               \
> > +               .shift  = _shift,                       \
> > +               .width  = _width,                       \
> > +               .min    = _min,                         \
> >         }
> >
> > +#define _SUNXI_CCU_MULT(_shift, _width)                \
> > +       _SUNXI_CCU_MULT_MIN(_shift, _width, 1)
> > +
> >  struct ccu_mult {
> >         u32                     enable;
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
> > index a42d870ba0ef..eaf0fdf78d2b 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nk.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nk.c
> > @@ -97,9 +97,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
> >         if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> >                 rate *= nk->fixed_post_div;
> >
> > -       _nk.min_n = 1;
> > +       _nk.min_n = nk->n.min;
> >         _nk.max_n = 1 << nk->n.width;
> > -       _nk.min_k = 1;
> > +       _nk.min_k = nk->k.min;
> >         _nk.max_k = 1 << nk->k.width;
> >
> >         ccu_nk_find_best(*parent_rate, rate, &_nk);
> > @@ -122,9 +122,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
> >         if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
> >                 rate = rate * nk->fixed_post_div;
> >
> > -       _nk.min_n = 1;
> > +       _nk.min_n = nk->n.min;
> >         _nk.max_n = 1 << nk->n.width;
> > -       _nk.min_k = 1;
> > +       _nk.min_k = nk->k.min;
> >         _nk.max_k = 1 << nk->k.width;
> >
> >         ccu_nk_find_best(parent_rate, rate, &_nk);
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
> > index b2a5fccf2f8c..715b49211ddb 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkm.c
> > @@ -100,9 +100,9 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
> >         struct ccu_nkm *nkm = data;
> >         struct _ccu_nkm _nkm;
> >
> > -       _nkm.min_n = 1;
> > +       _nkm.min_n = nkm->n.min;
> >         _nkm.max_n = 1 << nkm->n.width;
> > -       _nkm.min_k = 1;
> > +       _nkm.min_n = nkm->k.min;
> 
> Typo here.
> 
> >         _nkm.max_k = 1 << nkm->k.width;
> >         _nkm.min_m = 1;
> >         _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> > @@ -129,9 +129,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
> >         unsigned long flags;
> >         u32 reg;
> >
> > -       _nkm.min_n = 1;
> > +       _nkm.min_n = nkm->n.min;
> >         _nkm.max_n = 1 << nkm->n.width;
> > -       _nkm.min_k = 1;
> > +       _nkm.min_n = nkm->k.min;
> 
> And here.
> 
> >         _nkm.max_k = 1 << nkm->k.width;
> >         _nkm.min_m = 1;
> >         _nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > index 2c1398192e48..7968e0bac5db 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > @@ -107,9 +107,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
> >         struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
> >         struct _ccu_nkmp _nkmp;
> >
> > -       _nkmp.min_n = 1;
> > +       _nkmp.min_n = nkmp->n.min;
> >         _nkmp.max_n = 1 << nkmp->n.width;
> > -       _nkmp.min_k = 1;
> > +       _nkmp.min_n = nkmp->k.min;
> 
> And here.
> 
> >         _nkmp.max_k = 1 << nkmp->k.width;
> >         _nkmp.min_m = 1;
> >         _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
> > diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
> > index 2a190bc032a9..b1f3f0e8899d 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nm.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nm.c
> > @@ -93,7 +93,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
> >         struct ccu_nm *nm = hw_to_ccu_nm(hw);
> >         struct _ccu_nm _nm;
> >
> > -       _nm.min_n = 1;
> > +       _nm.min_n = nm->n.min;
> >         _nm.max_n = 1 << nm->n.width;
> >         _nm.min_m = 1;
> >         _nm.max_m = nm->m.max ?: 1 << nm->m.width;
> > --
> > git-series 0.8.10
> 
> Otherwise,
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Fixed and applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks

[Maxime Ripard]

Add the A64 CCU clocks set.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt |   1 +-
 drivers/clk/sunxi-ng/Kconfig                          |  11 +-
 drivers/clk/sunxi-ng/Makefile                         |   1 +-
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c                 | 918 +++++++++++-
 drivers/clk/sunxi-ng/ccu-sun50i-a64.h                 |  72 +-
 include/dt-bindings/clock/sun50i-a64-ccu.h            | 134 ++-
 include/dt-bindings/reset/sun50i-a64-ccu.h            |  98 +-
 7 files changed, 1235 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
 create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
 create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 3868458a5feb..74d44a4273f2 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -7,6 +7,7 @@ Required properties :
 		- "allwinner,sun8i-a23-ccu"
 		- "allwinner,sun8i-a33-ccu"
 		- "allwinner,sun8i-h3-ccu"
+		- "allwinner,sun50i-a64-ccu"
 
 - reg: Must contain the registers base address and length
 - clocks: phandle to the oscillators feeding the CCU. Two are needed:
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 1b4c55a53d7a..8454c6e3dd65 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -53,6 +53,17 @@ config SUNXI_CCU_MP
 
 # SoC Drivers
 
+config SUN50I_A64_CCU
+	bool "Support for the Allwinner A64 CCU"
+	select SUNXI_CCU_DIV
+	select SUNXI_CCU_NK
+	select SUNXI_CCU_NKM
+	select SUNXI_CCU_NKMP
+	select SUNXI_CCU_NM
+	select SUNXI_CCU_MP
+	select SUNXI_CCU_PHASE
+	default ARM64 && ARCH_SUNXI
+
 config SUN6I_A31_CCU
 	bool "Support for the Allwinner A31/A31s CCU"
 	select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 106cba27c331..24fbc6e5deb8 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM)	+= ccu_nm.o
 obj-$(CONFIG_SUNXI_CCU_MP)	+= ccu_mp.o
 
 # SoC support
+obj-$(CONFIG_SUN50I_A64_CCU)	+= ccu-sun50i-a64.o
 obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o
 obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
new file mode 100644
index 000000000000..c0e96bf6d104
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -0,0 +1,918 @@
+/*
+ * Copyright (c) 2016 Maxime Ripard. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun50i-a64.h"
+
+static struct ccu_nkmp pll_cpux_clk = {
+	.enable		= BIT(31),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT(8, 5),
+	.k		= _SUNXI_CCU_MULT(4, 2),
+	.m		= _SUNXI_CCU_DIV(0, 2),
+	.p		= _SUNXI_CCU_DIV_MAX(16, 2, 4),
+	.common		= {
+		.reg		= 0x000,
+		.hw.init	= CLK_HW_INIT("pll-cpux",
+					      "osc24M",
+					      &ccu_nkmp_ops,
+					      0),
+	},
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN50I_A64_PLL_AUDIO_REG	0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+				   "osc24M", 0x008,
+				   8, 7,	/* N */
+				   0, 5,	/* M */
+				   BIT(31),	/* gate */
+				   BIT(28),	/* lock */
+				   0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
+					"osc24M", 0x010,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
+					"osc24M", 0x018,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
+				    "osc24M", 0x020,
+				    8, 5,	/* N */
+				    4, 2,	/* K */
+				    0, 2,	/* M */
+				    BIT(31),	/* gate */
+				    BIT(28),	/* lock */
+				    0);
+
+static struct ccu_nk pll_periph0_clk = {
+	.enable		= BIT(31),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT(8, 5),
+	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
+	.fixed_post_div	= 2,
+	.common		= {
+		.reg		= 0x028,
+		.features	= CCU_FEATURE_FIXED_POSTDIV,
+		.hw.init	= CLK_HW_INIT("pll-periph0", "osc24M",
+					      &ccu_nk_ops, 0),
+	},
+};
+
+static struct ccu_nk pll_periph1_clk = {
+	.enable		= BIT(31),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT(8, 5),
+	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
+	.fixed_post_div	= 2,
+	.common		= {
+		.reg		= 0x02c,
+		.features	= CCU_FEATURE_FIXED_POSTDIV,
+		.hw.init	= CLK_HW_INIT("pll-periph1", "osc24M",
+					      &ccu_nk_ops, 0),
+	},
+};
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
+					"osc24M", 0x030,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
+					"osc24M", 0x038,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+/*
+ * The output function can be changed to something more complex that
+ * we do not handle yet.
+ *
+ * Hardcode the mode so that we don't fall in that case.
+ */
+#define SUN50I_A64_PLL_MIPI_REG		0x040
+
+struct ccu_nkm pll_mipi_clk = {
+	.enable		= BIT(31),
+	.lock		= BIT(28),
+	.n		= _SUNXI_CCU_MULT(8, 4),
+	.k		= _SUNXI_CCU_MULT_MIN(4, 2, 2),
+	.m		= _SUNXI_CCU_DIV(0, 4),
+	.common		= {
+		.reg		= 0x040,
+		.hw.init	= CLK_HW_INIT("pll-mipi", "pll-video0",
+					      &ccu_nkm_ops, 0),
+	},
+};
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
+					"osc24M", 0x044,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
+					"osc24M", 0x048,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
+				   "osc24M", 0x04c,
+				   8, 7,	/* N */
+				   0, 2,	/* M */
+				   BIT(31),	/* gate */
+				   BIT(28),	/* lock */
+				   0);
+
+static const char * const cpux_parents[] = { "osc32k", "osc24M",
+					     "pll-cpux" , "pll-cpux" };
+static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
+		     0x050, 16, 2, CLK_IS_CRITICAL);
+
+static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
+
+static const char * const ahb1_parents[] = { "osc32k", "osc24M",
+					     "axi" , "pll-periph0" };
+static struct ccu_div ahb1_clk = {
+	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+	.mux		= {
+		.shift	= 12,
+		.width	= 2,
+
+		.variable_prediv	= {
+			.index	= 3,
+			.shift	= 6,
+			.width	= 2,
+		},
+	},
+
+	.common		= {
+		.reg		= 0x054,
+		.features	= CCU_FEATURE_VARIABLE_PREDIV,
+		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
+						      ahb1_parents,
+						      &ccu_div_ops,
+						      0),
+	},
+};
+
+static struct clk_div_table apb1_div_table[] = {
+	{ .val = 0, .div = 2 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 4 },
+	{ .val = 3, .div = 8 },
+	{ /* Sentinel */ },
+};
+static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
+			   0x054, 8, 2, apb1_div_table, 0);
+
+static const char * const apb2_parents[] = { "osc32k", "osc24M",
+					     "pll-periph0-2x" ,
+					     "pll-periph0-2x" };
+static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
+			     0, 5,	/* M */
+			     16, 2,	/* P */
+			     24, 2,	/* mux */
+			     0);
+
+static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
+static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
+	{ .index = 1, .div = 2 },
+};
+static struct ccu_mux ahb2_clk = {
+	.mux		= {
+		.shift	= 0,
+		.width	= 1,
+		.fixed_predivs	= ahb2_fixed_predivs,
+		.n_predivs	= ARRAY_SIZE(ahb2_fixed_predivs),
+	},
+
+	.common		= {
+		.reg		= 0x05c,
+		.features	= CCU_FEATURE_FIXED_PREDIV,
+		.hw.init	= CLK_HW_INIT_PARENTS("ahb2",
+						      ahb2_parents,
+						      &ccu_mux_ops,
+						      0),
+	},
+};
+
+static SUNXI_CCU_GATE(bus_mipi_dsi_clk,	"bus-mipi-dsi",	"ahb1",
+		      0x060, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
+		      0x060, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
+		      0x060, BIT(6), 0);
+static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
+		      0x060, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
+		      0x060, BIT(9), 0);
+static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
+		      0x060, BIT(10), 0);
+static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
+		      0x060, BIT(13), 0);
+static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
+		      0x060, BIT(14), 0);
+static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb2",
+		      0x060, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
+		      0x060, BIT(18), 0);
+static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
+		      0x060, BIT(19), 0);
+static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
+		      0x060, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
+		      0x060, BIT(21), 0);
+static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
+		      0x060, BIT(23), 0);
+static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
+		      0x060, BIT(24), 0);
+static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb2",
+		      0x060, BIT(25), 0);
+static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
+		      0x060, BIT(28), 0);
+static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb2",
+		      0x060, BIT(29), 0);
+
+static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
+		      0x064, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_tcon0_clk,	"bus-tcon0",	"ahb1",
+		      0x064, BIT(3), 0);
+static SUNXI_CCU_GATE(bus_tcon1_clk,	"bus-tcon1",	"ahb1",
+		      0x064, BIT(4), 0);
+static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
+		      0x064, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
+		      0x064, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_hdmi_clk,	"bus-hdmi",	"ahb1",
+		      0x064, BIT(11), 0);
+static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
+		      0x064, BIT(12), 0);
+static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
+		      0x064, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_msgbox_clk,	"bus-msgbox",	"ahb1",
+		      0x064, BIT(21), 0);
+static SUNXI_CCU_GATE(bus_spinlock_clk,	"bus-spinlock",	"ahb1",
+		      0x064, BIT(22), 0);
+
+static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
+		      0x068, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
+		      0x068, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
+		      0x068, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
+		      0x068, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
+		      0x068, BIT(12), 0);
+static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
+		      0x068, BIT(13), 0);
+static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
+		      0x068, BIT(14), 0);
+
+static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
+		      0x06c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
+		      0x06c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
+		      0x06c, BIT(2), 0);
+static SUNXI_CCU_GATE(bus_scr_clk,	"bus-scr",	"apb2",
+		      0x06c, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
+		      0x06c, BIT(16), 0);
+static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
+		      0x06c, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
+		      0x06c, BIT(18), 0);
+static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
+		      0x06c, BIT(19), 0);
+static SUNXI_CCU_GATE(bus_uart4_clk,	"bus-uart4",	"apb2",
+		      0x06c, BIT(20), 0);
+
+static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
+		      0x070, BIT(7), 0);
+
+static struct clk_div_table ths_div_table[] = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 4 },
+	{ .val = 3, .div = 6 },
+};
+static const char * const ths_parents[] = { "osc24M" };
+static struct ccu_div ths_clk = {
+	.enable	= BIT(31),
+	.div	= _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
+	.mux	= _SUNXI_CCU_MUX(24, 2),
+	.common	= {
+		.reg		= 0x074,
+		.hw.init	= CLK_HW_INIT_PARENTS("ths",
+						      ths_parents,
+						      &ccu_div_ops,
+						      0),
+	},
+};
+
+static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
+						     "pll-periph1" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",
+						    "pll-periph1-2x" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
+static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 4,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
+					    "pll-audio-2x", "pll-audio" };
+static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
+			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
+			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
+			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
+			     0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
+		      0x0cc, BIT(8), 0);
+static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
+		      0x0cc, BIT(9), 0);
+static SUNXI_CCU_GATE(usb_hsic_clk,	"usb-hsic",	"pll-hsic",
+		      0x0cc, BIT(10), 0);
+static SUNXI_CCU_GATE(usb_hsic_12m_clk,	"usb-hsic-12M",	"osc12M",
+		      0x0cc, BIT(11), 0);
+static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc12M",
+		      0x0cc, BIT(16), 0);
+static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"usb-ohci0",
+		      0x0cc, BIT(17), 0);
+
+static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
+static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
+			    0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
+		      0x100, BIT(0), 0);
+static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
+		      0x100, BIT(1), 0);
+static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
+		      0x100, BIT(2), 0);
+static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
+		      0x100, BIT(3), 0);
+
+static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
+static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
+				 0x104, 0, 4, 24, 3, BIT(31), 0);
+
+static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
+static const u8 tcon0_table[] = { 0, 2, };
+static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
+				     tcon0_table, 0x118, 24, 3, BIT(31),
+				     CLK_SET_RATE_PARENT);
+
+static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
+static const u8 tcon1_table[] = { 0, 2, };
+struct ccu_div tcon1_clk = {
+	.enable		= BIT(31),
+	.div		= _SUNXI_CCU_DIV(0, 4),
+	.mux		= _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),
+	.common		= {
+		.reg		= 0x11c,
+		.hw.init	= CLK_HW_INIT_PARENTS("tcon1",
+						      tcon1_parents,
+						      &ccu_div_ops,
+						      CLK_SET_RATE_PARENT),
+	},
+};
+
+static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
+				 0x124, 0, 4, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_GATE(csi_misc_clk,	"csi-misc",	"osc24M",
+		      0x130, BIT(31), 0);
+
+static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
+				 0x134, 16, 4, 24, 3, BIT(31), 0);
+
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
+				 0x134, 0, 5, 8, 3, BIT(15), 0);
+
+static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
+			     0x13c, 16, 3, BIT(31), 0);
+
+static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
+		      0x140, BIT(31), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(ac_dig_4x_clk,	"ac-dig-4x",	"pll-audio-4x",
+		      0x140, BIT(30), CLK_SET_RATE_PARENT);
+
+static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
+		      0x144, BIT(31), 0);
+
+static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
+				 0x150, 0, 4, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_GATE(hdmi_ddc_clk,	"hdmi-ddc",	"osc24M",
+		      0x154, BIT(31), 0);
+
+static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
+						 "pll-ddr0", "pll-ddr1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
+				 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
+
+static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
+static const u8 dsi_dphy_table[] = { 0, 2, };
+static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
+				       dsi_dphy_parents, dsi_dphy_table,
+				       0x168, 0, 3, 24, 2, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
+			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
+
+/* Fixed Factor clocks */
+static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0);
+
+/* We hardcode the divider to 4 for now */
+static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
+			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
+			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
+			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
+			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
+			"pll-periph0", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
+			"pll-periph1", 1, 2, 0);
+static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
+			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
+
+static struct ccu_common *sun50i_a64_ccu_clks[] = {
+	&pll_cpux_clk.common,
+	&pll_audio_base_clk.common,
+	&pll_video0_clk.common,
+	&pll_ve_clk.common,
+	&pll_ddr0_clk.common,
+	&pll_periph0_clk.common,
+	&pll_periph1_clk.common,
+	&pll_video1_clk.common,
+	&pll_gpu_clk.common,
+	&pll_mipi_clk.common,
+	&pll_hsic_clk.common,
+	&pll_de_clk.common,
+	&pll_ddr1_clk.common,
+	&cpux_clk.common,
+	&axi_clk.common,
+	&ahb1_clk.common,
+	&apb1_clk.common,
+	&apb2_clk.common,
+	&ahb2_clk.common,
+	&bus_mipi_dsi_clk.common,
+	&bus_ce_clk.common,
+	&bus_dma_clk.common,
+	&bus_mmc0_clk.common,
+	&bus_mmc1_clk.common,
+	&bus_mmc2_clk.common,
+	&bus_nand_clk.common,
+	&bus_dram_clk.common,
+	&bus_emac_clk.common,
+	&bus_ts_clk.common,
+	&bus_hstimer_clk.common,
+	&bus_spi0_clk.common,
+	&bus_spi1_clk.common,
+	&bus_otg_clk.common,
+	&bus_ehci0_clk.common,
+	&bus_ehci1_clk.common,
+	&bus_ohci0_clk.common,
+	&bus_ohci1_clk.common,
+	&bus_ve_clk.common,
+	&bus_tcon0_clk.common,
+	&bus_tcon1_clk.common,
+	&bus_deinterlace_clk.common,
+	&bus_csi_clk.common,
+	&bus_hdmi_clk.common,
+	&bus_de_clk.common,
+	&bus_gpu_clk.common,
+	&bus_msgbox_clk.common,
+	&bus_spinlock_clk.common,
+	&bus_codec_clk.common,
+	&bus_spdif_clk.common,
+	&bus_pio_clk.common,
+	&bus_ths_clk.common,
+	&bus_i2s0_clk.common,
+	&bus_i2s1_clk.common,
+	&bus_i2s2_clk.common,
+	&bus_i2c0_clk.common,
+	&bus_i2c1_clk.common,
+	&bus_i2c2_clk.common,
+	&bus_scr_clk.common,
+	&bus_uart0_clk.common,
+	&bus_uart1_clk.common,
+	&bus_uart2_clk.common,
+	&bus_uart3_clk.common,
+	&bus_uart4_clk.common,
+	&bus_dbg_clk.common,
+	&ths_clk.common,
+	&nand_clk.common,
+	&mmc0_clk.common,
+	&mmc1_clk.common,
+	&mmc2_clk.common,
+	&ts_clk.common,
+	&ce_clk.common,
+	&spi0_clk.common,
+	&spi1_clk.common,
+	&i2s0_clk.common,
+	&i2s1_clk.common,
+	&i2s2_clk.common,
+	&spdif_clk.common,
+	&usb_phy0_clk.common,
+	&usb_phy1_clk.common,
+	&usb_hsic_clk.common,
+	&usb_hsic_12m_clk.common,
+	&usb_ohci0_clk.common,
+	&usb_ohci1_clk.common,
+	&dram_clk.common,
+	&dram_ve_clk.common,
+	&dram_csi_clk.common,
+	&dram_deinterlace_clk.common,
+	&dram_ts_clk.common,
+	&de_clk.common,
+	&tcon0_clk.common,
+	&tcon1_clk.common,
+	&deinterlace_clk.common,
+	&csi_misc_clk.common,
+	&csi_sclk_clk.common,
+	&csi_mclk_clk.common,
+	&ve_clk.common,
+	&ac_dig_clk.common,
+	&ac_dig_4x_clk.common,
+	&avs_clk.common,
+	&hdmi_clk.common,
+	&hdmi_ddc_clk.common,
+	&mbus_clk.common,
+	&dsi_dphy_clk.common,
+	&gpu_clk.common,
+};
+
+static struct clk_hw_onecell_data sun50i_a64_hw_clks = {
+	.hws	= {
+		[CLK_OSC_12M]		= &osc12M_clk.hw,
+		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
+		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
+		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
+		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
+		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
+		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
+		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
+		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
+		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
+		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
+		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
+		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
+		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
+		[CLK_PLL_PERIPH1_2X]	= &pll_periph1_2x_clk.hw,
+		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
+		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
+		[CLK_PLL_MIPI]  	= &pll_mipi_clk.common.hw,
+		[CLK_PLL_HSIC]		= &pll_hsic_clk.common.hw,
+		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
+		[CLK_PLL_DDR1]		= &pll_ddr1_clk.common.hw,
+		[CLK_CPUX]		= &cpux_clk.common.hw,
+		[CLK_AXI]		= &axi_clk.common.hw,
+		[CLK_AHB1]		= &ahb1_clk.common.hw,
+		[CLK_APB1]		= &apb1_clk.common.hw,
+		[CLK_APB2]		= &apb2_clk.common.hw,
+		[CLK_AHB2]		= &ahb2_clk.common.hw,
+		[CLK_BUS_MIPI_DSI]	= &bus_mipi_dsi_clk.common.hw,
+		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
+		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
+		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
+		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
+		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
+		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
+		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
+		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
+		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
+		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
+		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
+		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
+		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
+		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
+		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
+		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
+		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
+		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
+		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
+		[CLK_BUS_TCON1]		= &bus_tcon1_clk.common.hw,
+		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
+		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
+		[CLK_BUS_HDMI]		= &bus_hdmi_clk.common.hw,
+		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
+		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
+		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
+		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
+		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
+		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
+		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
+		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
+		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
+		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
+		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
+		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
+		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
+		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
+		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
+		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
+		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
+		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
+		[CLK_BUS_UART4]		= &bus_uart4_clk.common.hw,
+		[CLK_BUS_SCR]		= &bus_scr_clk.common.hw,
+		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
+		[CLK_THS]		= &ths_clk.common.hw,
+		[CLK_NAND]		= &nand_clk.common.hw,
+		[CLK_MMC0]		= &mmc0_clk.common.hw,
+		[CLK_MMC1]		= &mmc1_clk.common.hw,
+		[CLK_MMC2]		= &mmc2_clk.common.hw,
+		[CLK_TS]		= &ts_clk.common.hw,
+		[CLK_CE]		= &ce_clk.common.hw,
+		[CLK_SPI0]		= &spi0_clk.common.hw,
+		[CLK_SPI1]		= &spi1_clk.common.hw,
+		[CLK_I2S0]		= &i2s0_clk.common.hw,
+		[CLK_I2S1]		= &i2s1_clk.common.hw,
+		[CLK_I2S2]		= &i2s2_clk.common.hw,
+		[CLK_SPDIF]		= &spdif_clk.common.hw,
+		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
+		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
+		[CLK_USB_HSIC]		= &usb_hsic_clk.common.hw,
+		[CLK_USB_HSIC_12M]	= &usb_hsic_12m_clk.common.hw,
+		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
+		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
+		[CLK_DRAM]		= &dram_clk.common.hw,
+		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
+		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
+		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
+		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
+		[CLK_DE]		= &de_clk.common.hw,
+		[CLK_TCON0]		= &tcon0_clk.common.hw,
+		[CLK_TCON1]		= &tcon1_clk.common.hw,
+		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
+		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
+		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
+		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
+		[CLK_VE]		= &ve_clk.common.hw,
+		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
+		[CLK_AC_DIG_4X]		= &ac_dig_4x_clk.common.hw,
+		[CLK_AVS]		= &avs_clk.common.hw,
+		[CLK_HDMI]		= &hdmi_clk.common.hw,
+		[CLK_HDMI_DDC]		= &hdmi_ddc_clk.common.hw,
+		[CLK_MBUS]		= &mbus_clk.common.hw,
+		[CLK_DSI_DPHY]		= &dsi_dphy_clk.common.hw,
+		[CLK_GPU]		= &gpu_clk.common.hw,
+	},
+	.num	= CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun50i_a64_ccu_resets[] = {
+	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
+	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
+	[RST_USB_HSIC]		=  { 0x0cc, BIT(2) },
+
+	[RST_DRAM]		=  { 0x0f4, BIT(31) },
+	[RST_MBUS]		=  { 0x0fc, BIT(31) },
+
+	[RST_BUS_MIPI_DSI]	=  { 0x2c0, BIT(1) },
+	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
+	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
+	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
+	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
+	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
+	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
+	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
+	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
+	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
+	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
+	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
+	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
+	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
+	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
+
+	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
+	[RST_BUS_TCON0]		=  { 0x2c4, BIT(3) },
+	[RST_BUS_TCON1]		=  { 0x2c4, BIT(4) },
+	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
+	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
+	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
+	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
+	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
+	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
+	[RST_BUS_MSGBOX]	=  { 0x2c4, BIT(21) },
+	[RST_BUS_SPINLOCK]	=  { 0x2c4, BIT(22) },
+	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
+
+	[RST_BUS_LVDS]		=  { 0x2c8, BIT(0) },
+
+	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
+	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
+	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
+	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
+	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
+	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
+
+	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
+	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
+	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
+	[RST_BUS_SCR]		=  { 0x2d8, BIT(5) },
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
+	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
+	[RST_BUS_UART4]		=  { 0x2d8, BIT(20) },
+};
+
+static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
+	.ccu_clks	= sun50i_a64_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun50i_a64_ccu_clks),
+
+	.hw_clks	= &sun50i_a64_hw_clks,
+
+	.resets		= sun50i_a64_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun50i_a64_ccu_resets),
+};
+
+static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	void __iomem *reg;
+	u32 val;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	reg = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(reg)) {
+		dev_err(&pdev->dev, "Could not map the clock registers\n");
+		return PTR_ERR(reg);
+	}
+
+	/* Force the PLL-Audio-1x divider to 4 */
+	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
+	val &= ~GENMASK(19, 16);
+	writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
+
+	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+
+	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
+}
+
+static const struct of_device_id sun50i_a64_ccu_ids[] = {
+	{ .compatible = "allwinner,sun50i-a64-ccu" },
+	{ },
+};
+
+static struct platform_driver sun50i_a64_ccu_driver = {
+	.probe	= sun50i_a64_ccu_probe,
+	.driver	= {
+		.name	= "sun50i-a64-ccu",
+		.of_match_table	= sun50i_a64_ccu_ids,
+	},
+};
+builtin_platform_driver(sun50i_a64_ccu_driver);
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
new file mode 100644
index 000000000000..9b3cd24b78d2
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN50I_A64_H_
+#define _CCU_SUN50I_A64_H_
+
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+#define CLK_OSC_12M			0
+#define CLK_PLL_CPUX			1
+#define CLK_PLL_AUDIO_BASE		2
+#define CLK_PLL_AUDIO			3
+#define CLK_PLL_AUDIO_2X		4
+#define CLK_PLL_AUDIO_4X		5
+#define CLK_PLL_AUDIO_8X		6
+#define CLK_PLL_VIDEO0			7
+#define CLK_PLL_VIDEO0_2X		8
+#define CLK_PLL_VE			9
+#define CLK_PLL_DDR0			10
+#define CLK_PLL_PERIPH0			11
+#define CLK_PLL_PERIPH0_2X		12
+#define CLK_PLL_PERIPH1			13
+#define CLK_PLL_PERIPH1_2X		14
+#define CLK_PLL_VIDEO1			15
+#define CLK_PLL_GPU			16
+#define CLK_PLL_MIPI			17
+#define CLK_PLL_HSIC			18
+#define CLK_PLL_DE			19
+#define CLK_PLL_DDR1			20
+#define CLK_CPUX			21
+#define CLK_AXI				22
+#define CLK_APB				23
+#define CLK_AHB1			24
+#define CLK_APB1			25
+#define CLK_APB2			26
+#define CLK_AHB2			27
+
+/* All the bus gates are exported */
+
+/* The first bunch of module clocks are exported */
+
+#define CLK_USB_OHCI0_12M		90
+
+#define CLK_USB_OHCI1_12M		92
+
+#define CLK_DRAM			94
+
+/* All the DRAM gates are exported */
+
+/* Some more module clocks are exported */
+
+#define CLK_MBUS			112
+
+/* And the DSI and GPU module clock is exported */
+
+#define CLK_NUMBER			(CLK_GPU + 1)
+
+#endif /* _CCU_SUN50I_A64_H_ */
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
new file mode 100644
index 000000000000..370c0a0473fc
--- /dev/null
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+
+#define CLK_BUS_MIPI_DSI	28
+#define CLK_BUS_CE		29
+#define CLK_BUS_DMA		30
+#define CLK_BUS_MMC0		31
+#define CLK_BUS_MMC1		32
+#define CLK_BUS_MMC2		33
+#define CLK_BUS_NAND		34
+#define CLK_BUS_DRAM		35
+#define CLK_BUS_EMAC		36
+#define CLK_BUS_TS		37
+#define CLK_BUS_HSTIMER		38
+#define CLK_BUS_SPI0		39
+#define CLK_BUS_SPI1		40
+#define CLK_BUS_OTG		41
+#define CLK_BUS_EHCI0		42
+#define CLK_BUS_EHCI1		43
+#define CLK_BUS_OHCI0		44
+#define CLK_BUS_OHCI1		45
+#define CLK_BUS_VE		46
+#define CLK_BUS_TCON0		47
+#define CLK_BUS_TCON1		48
+#define CLK_BUS_DEINTERLACE	49
+#define CLK_BUS_CSI		50
+#define CLK_BUS_HDMI		51
+#define CLK_BUS_DE		52
+#define CLK_BUS_GPU		53
+#define CLK_BUS_MSGBOX		54
+#define CLK_BUS_SPINLOCK	55
+#define CLK_BUS_CODEC		56
+#define CLK_BUS_SPDIF		57
+#define CLK_BUS_PIO		58
+#define CLK_BUS_THS		59
+#define CLK_BUS_I2S0		60
+#define CLK_BUS_I2S1		61
+#define CLK_BUS_I2S2		62
+#define CLK_BUS_I2C0		63
+#define CLK_BUS_I2C1		64
+#define CLK_BUS_I2C2		65
+#define CLK_BUS_SCR		66
+#define CLK_BUS_UART0		67
+#define CLK_BUS_UART1		68
+#define CLK_BUS_UART2		69
+#define CLK_BUS_UART3		70
+#define CLK_BUS_UART4		71
+#define CLK_BUS_DBG		72
+#define CLK_THS			73
+#define CLK_NAND		74
+#define CLK_MMC0		75
+#define CLK_MMC1		76
+#define CLK_MMC2		77
+#define CLK_TS			78
+#define CLK_CE			79
+#define CLK_SPI0		80
+#define CLK_SPI1		81
+#define CLK_I2S0		82
+#define CLK_I2S1		83
+#define CLK_I2S2		84
+#define CLK_SPDIF		85
+#define CLK_USB_PHY0		86
+#define CLK_USB_PHY1		87
+#define CLK_USB_HSIC		88
+#define CLK_USB_HSIC_12M	89
+
+#define CLK_USB_OHCI0		91
+
+#define CLK_USB_OHCI1		93
+
+#define CLK_DRAM_VE		95
+#define CLK_DRAM_CSI		96
+#define CLK_DRAM_DEINTERLACE	97
+#define CLK_DRAM_TS		98
+#define CLK_DE			99
+#define CLK_TCON0		100
+#define CLK_TCON1		101
+#define CLK_DEINTERLACE		102
+#define CLK_CSI_MISC		103
+#define CLK_CSI_SCLK		104
+#define CLK_CSI_MCLK		105
+#define CLK_VE			106
+#define CLK_AC_DIG		107
+#define CLK_AC_DIG_4X		108
+#define CLK_AVS			109
+#define CLK_HDMI		110
+#define CLK_HDMI_DDC		111
+
+#define CLK_DSI_DPHY		113
+#define CLK_GPU			114
+
+#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */
diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h
new file mode 100644
index 000000000000..db60b29ddb11
--- /dev/null
+++ b/include/dt-bindings/reset/sun50i-a64-ccu.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_
+#define _DT_BINDINGS_RST_SUN50I_A64_H_
+
+#define RST_USB_PHY0		0
+#define RST_USB_PHY1		1
+#define RST_USB_HSIC		2
+#define RST_DRAM		3
+#define RST_MBUS		4
+#define RST_BUS_MIPI_DSI	5
+#define RST_BUS_CE		6
+#define RST_BUS_DMA		7
+#define RST_BUS_MMC0		8
+#define RST_BUS_MMC1		9
+#define RST_BUS_MMC2		10
+#define RST_BUS_NAND		11
+#define RST_BUS_DRAM		12
+#define RST_BUS_EMAC		13
+#define RST_BUS_TS		14
+#define RST_BUS_HSTIMER		15
+#define RST_BUS_SPI0		16
+#define RST_BUS_SPI1		17
+#define RST_BUS_OTG		18
+#define RST_BUS_EHCI0		19
+#define RST_BUS_EHCI1		20
+#define RST_BUS_OHCI0		21
+#define RST_BUS_OHCI1		22
+#define RST_BUS_VE		23
+#define RST_BUS_TCON0		24
+#define RST_BUS_TCON1		25
+#define RST_BUS_DEINTERLACE	26
+#define RST_BUS_CSI		27
+#define RST_BUS_HDMI0		28
+#define RST_BUS_HDMI1		29
+#define RST_BUS_DE		30
+#define RST_BUS_GPU		31
+#define RST_BUS_MSGBOX		32
+#define RST_BUS_SPINLOCK	33
+#define RST_BUS_DBG		34
+#define RST_BUS_LVDS		35
+#define RST_BUS_CODEC		36
+#define RST_BUS_SPDIF		37
+#define RST_BUS_THS		38
+#define RST_BUS_I2S0		39
+#define RST_BUS_I2S1		40
+#define RST_BUS_I2S2		41
+#define RST_BUS_I2C0		42
+#define RST_BUS_I2C1		43
+#define RST_BUS_I2C2		44
+#define RST_BUS_SCR		45
+#define RST_BUS_UART0		46
+#define RST_BUS_UART1		47
+#define RST_BUS_UART2		48
+#define RST_BUS_UART3		49
+#define RST_BUS_UART4		50
+
+#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */
-- 
git-series 0.8.10

[linux-sunxi] [PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Add the A64 CCU clocks set.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi-ccu.txt |   1 +-
>  drivers/clk/sunxi-ng/Kconfig                          |  11 +-
>  drivers/clk/sunxi-ng/Makefile                         |   1 +-
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.c                 | 918 +++++++++++-
>  drivers/clk/sunxi-ng/ccu-sun50i-a64.h                 |  72 +-
>  include/dt-bindings/clock/sun50i-a64-ccu.h            | 134 ++-
>  include/dt-bindings/reset/sun50i-a64-ccu.h            |  98 +-
>  7 files changed, 1235 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
>  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> index 3868458a5feb..74d44a4273f2 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> @@ -7,6 +7,7 @@ Required properties :
>                 - "allwinner,sun8i-a23-ccu"
>                 - "allwinner,sun8i-a33-ccu"
>                 - "allwinner,sun8i-h3-ccu"
> +               - "allwinner,sun50i-a64-ccu"
>
>  - reg: Must contain the registers base address and length
>  - clocks: phandle to the oscillators feeding the CCU. Two are needed:
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 1b4c55a53d7a..8454c6e3dd65 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -53,6 +53,17 @@ config SUNXI_CCU_MP
>
>  # SoC Drivers
>
> +config SUN50I_A64_CCU
> +       bool "Support for the Allwinner A64 CCU"
> +       select SUNXI_CCU_DIV
> +       select SUNXI_CCU_NK
> +       select SUNXI_CCU_NKM
> +       select SUNXI_CCU_NKMP
> +       select SUNXI_CCU_NM
> +       select SUNXI_CCU_MP
> +       select SUNXI_CCU_PHASE
> +       default ARM64 && ARCH_SUNXI
> +
>  config SUN6I_A31_CCU
>         bool "Support for the Allwinner A31/A31s CCU"
>         select SUNXI_CCU_DIV
> diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> index 106cba27c331..24fbc6e5deb8 100644
> --- a/drivers/clk/sunxi-ng/Makefile
> +++ b/drivers/clk/sunxi-ng/Makefile
> @@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM)    += ccu_nm.o
>  obj-$(CONFIG_SUNXI_CCU_MP)     += ccu_mp.o
>
>  # SoC support
> +obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
>  obj-$(CONFIG_SUN6I_A31_CCU)    += ccu-sun6i-a31.o
>  obj-$(CONFIG_SUN8I_A23_CCU)    += ccu-sun8i-a23.o
>  obj-$(CONFIG_SUN8I_A33_CCU)    += ccu-sun8i-a33.o
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> new file mode 100644
> index 000000000000..c0e96bf6d104
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> @@ -0,0 +1,918 @@
> +/*
> + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +
> +#include "ccu_common.h"
> +#include "ccu_reset.h"
> +
> +#include "ccu_div.h"
> +#include "ccu_gate.h"
> +#include "ccu_mp.h"
> +#include "ccu_mult.h"
> +#include "ccu_nk.h"
> +#include "ccu_nkm.h"
> +#include "ccu_nkmp.h"
> +#include "ccu_nm.h"
> +#include "ccu_phase.h"
> +
> +#include "ccu-sun50i-a64.h"
> +
> +static struct ccu_nkmp pll_cpux_clk = {
> +       .enable         = BIT(31),
> +       .lock           = BIT(28),
> +       .n              = _SUNXI_CCU_MULT(8, 5),
> +       .k              = _SUNXI_CCU_MULT(4, 2),
> +       .m              = _SUNXI_CCU_DIV(0, 2),
> +       .p              = _SUNXI_CCU_DIV_MAX(16, 2, 4),
> +       .common         = {
> +               .reg            = 0x000,
> +               .hw.init        = CLK_HW_INIT("pll-cpux",
> +                                             "osc24M",
> +                                             &ccu_nkmp_ops,
> +                                             0),
> +       },
> +};
> +
> +/*
> + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> + * the base (2x, 4x and 8x), and one variable divider (the one true
> + * pll audio).
> + *
> + * We don't have any need for the variable divider for now, so we just
> + * hardcode it to match with the clock names
> + */
> +#define SUN50I_A64_PLL_AUDIO_REG       0x008
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> +                                  "osc24M", 0x008,
> +                                  8, 7,        /* N */
> +                                  0, 5,        /* M */
> +                                  BIT(31),     /* gate */
> +                                  BIT(28),     /* lock */
> +                                  0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> +                                       "osc24M", 0x010,
> +                                       8, 7,           /* N */
> +                                       0, 4,           /* M */
> +                                       BIT(24),        /* frac enable */
> +                                       BIT(25),        /* frac select */
> +                                       270000000,      /* frac rate 0 */
> +                                       297000000,      /* frac rate 1 */
> +                                       BIT(31),        /* gate */
> +                                       BIT(28),        /* lock */
> +                                       0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
> +                                       "osc24M", 0x018,
> +                                       8, 7,           /* N */
> +                                       0, 4,           /* M */
> +                                       BIT(24),        /* frac enable */
> +                                       BIT(25),        /* frac select */
> +                                       270000000,      /* frac rate 0 */
> +                                       297000000,      /* frac rate 1 */
> +                                       BIT(31),        /* gate */
> +                                       BIT(28),        /* lock */
> +                                       0);
> +
> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
> +                                   "osc24M", 0x020,
> +                                   8, 5,       /* N */
> +                                   4, 2,       /* K */
> +                                   0, 2,       /* M */
> +                                   BIT(31),    /* gate */
> +                                   BIT(28),    /* lock */
> +                                   0);
> +
> +static struct ccu_nk pll_periph0_clk = {
> +       .enable         = BIT(31),
> +       .lock           = BIT(28),
> +       .n              = _SUNXI_CCU_MULT(8, 5),
> +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> +       .fixed_post_div = 2,
> +       .common         = {
> +               .reg            = 0x028,
> +               .features       = CCU_FEATURE_FIXED_POSTDIV,
> +               .hw.init        = CLK_HW_INIT("pll-periph0", "osc24M",
> +                                             &ccu_nk_ops, 0),
> +       },
> +};
> +
> +static struct ccu_nk pll_periph1_clk = {
> +       .enable         = BIT(31),
> +       .lock           = BIT(28),
> +       .n              = _SUNXI_CCU_MULT(8, 5),
> +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> +       .fixed_post_div = 2,
> +       .common         = {
> +               .reg            = 0x02c,
> +               .features       = CCU_FEATURE_FIXED_POSTDIV,
> +               .hw.init        = CLK_HW_INIT("pll-periph1", "osc24M",
> +                                             &ccu_nk_ops, 0),
> +       },
> +};
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
> +                                       "osc24M", 0x030,
> +                                       8, 7,           /* N */
> +                                       0, 4,           /* M */
> +                                       BIT(24),        /* frac enable */
> +                                       BIT(25),        /* frac select */
> +                                       270000000,      /* frac rate 0 */
> +                                       297000000,      /* frac rate 1 */
> +                                       BIT(31),        /* gate */
> +                                       BIT(28),        /* lock */
> +                                       0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
> +                                       "osc24M", 0x038,
> +                                       8, 7,           /* N */
> +                                       0, 4,           /* M */
> +                                       BIT(24),        /* frac enable */
> +                                       BIT(25),        /* frac select */
> +                                       270000000,      /* frac rate 0 */
> +                                       297000000,      /* frac rate 1 */
> +                                       BIT(31),        /* gate */
> +                                       BIT(28),        /* lock */
> +                                       0);
> +
> +/*
> + * The output function can be changed to something more complex that
> + * we do not handle yet.
> + *
> + * Hardcode the mode so that we don't fall in that case.
> + */
> +#define SUN50I_A64_PLL_MIPI_REG                0x040
> +
> +struct ccu_nkm pll_mipi_clk = {
> +       .enable         = BIT(31),
> +       .lock           = BIT(28),
> +       .n              = _SUNXI_CCU_MULT(8, 4),
> +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> +       .m              = _SUNXI_CCU_DIV(0, 4),
> +       .common         = {
> +               .reg            = 0x040,
> +               .hw.init        = CLK_HW_INIT("pll-mipi", "pll-video0",
> +                                             &ccu_nkm_ops, 0),
> +       },
> +};
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
> +                                       "osc24M", 0x044,
> +                                       8, 7,           /* N */
> +                                       0, 4,           /* M */
> +                                       BIT(24),        /* frac enable */
> +                                       BIT(25),        /* frac select */
> +                                       270000000,      /* frac rate 0 */
> +                                       297000000,      /* frac rate 1 */
> +                                       BIT(31),        /* gate */
> +                                       BIT(28),        /* lock */
> +                                       0);
> +
> +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
> +                                       "osc24M", 0x048,
> +                                       8, 7,           /* N */
> +                                       0, 4,           /* M */
> +                                       BIT(24),        /* frac enable */
> +                                       BIT(25),        /* frac select */
> +                                       270000000,      /* frac rate 0 */
> +                                       297000000,      /* frac rate 1 */
> +                                       BIT(31),        /* gate */
> +                                       BIT(28),        /* lock */
> +                                       0);
> +
> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
> +                                  "osc24M", 0x04c,
> +                                  8, 7,        /* N */
> +                                  0, 2,        /* M */
> +                                  BIT(31),     /* gate */
> +                                  BIT(28),     /* lock */
> +                                  0);

CLK_SET_RATE_UNGATE for all the PLLs?

> +
> +static const char * const cpux_parents[] = { "osc32k", "osc24M",
> +                                            "pll-cpux" , "pll-cpux" };
> +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> +                    0x050, 16, 2, CLK_IS_CRITICAL);

CLK_SET_RATE_PARENT.

[...]

> +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
> +                                 0, 4,         /* M */
> +                                 16, 2,        /* P */
> +                                 24, 2,        /* mux */
> +                                 BIT(31),      /* gate */
> +                                 0);
> +
> +

Extra newline.

[...]

> +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
> +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
> +                           0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);

The divider is only 2 bits wide.

> +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> +static const u8 tcon1_table[] = { 0, 2, };
> +struct ccu_div tcon1_clk = {
> +       .enable         = BIT(31),
> +       .div            = _SUNXI_CCU_DIV(0, 4),
> +       .mux            = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),

Mux is only 2 bits wide.

> +       .common         = {
> +               .reg            = 0x11c,
> +               .hw.init        = CLK_HW_INIT_PARENTS("tcon1",
> +                                                     tcon1_parents,
> +                                                     &ccu_div_ops,
> +                                                     CLK_SET_RATE_PARENT),
> +       },
> +};
> +

[...]

> +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
> +static const u8 dsi_dphy_table[] = { 0, 2, };
> +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
> +                                      dsi_dphy_parents, dsi_dphy_table,
> +                                      0x168, 0, 3, 24, 2, BIT(31), 0);

Divider is 4 bits wide, and mux offset is 8.

[...]

Regards
ChenYu

[linux-sunxi] [PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks

[Maxime Ripard]

On Thu, Oct 20, 2016 at 11:50:21PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Add the A64 CCU clocks set.
> >
> > Acked-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  Documentation/devicetree/bindings/clock/sunxi-ccu.txt |   1 +-
> >  drivers/clk/sunxi-ng/Kconfig                          |  11 +-
> >  drivers/clk/sunxi-ng/Makefile                         |   1 +-
> >  drivers/clk/sunxi-ng/ccu-sun50i-a64.c                 | 918 +++++++++++-
> >  drivers/clk/sunxi-ng/ccu-sun50i-a64.h                 |  72 +-
> >  include/dt-bindings/clock/sun50i-a64-ccu.h            | 134 ++-
> >  include/dt-bindings/reset/sun50i-a64-ccu.h            |  98 +-
> >  7 files changed, 1235 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> >  create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-a64.h
> >  create mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h
> >  create mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> > index 3868458a5feb..74d44a4273f2 100644
> > --- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> > +++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
> > @@ -7,6 +7,7 @@ Required properties :
> >                 - "allwinner,sun8i-a23-ccu"
> >                 - "allwinner,sun8i-a33-ccu"
> >                 - "allwinner,sun8i-h3-ccu"
> > +               - "allwinner,sun50i-a64-ccu"
> >
> >  - reg: Must contain the registers base address and length
> >  - clocks: phandle to the oscillators feeding the CCU. Two are needed:
> > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> > index 1b4c55a53d7a..8454c6e3dd65 100644
> > --- a/drivers/clk/sunxi-ng/Kconfig
> > +++ b/drivers/clk/sunxi-ng/Kconfig
> > @@ -53,6 +53,17 @@ config SUNXI_CCU_MP
> >
> >  # SoC Drivers
> >
> > +config SUN50I_A64_CCU
> > +       bool "Support for the Allwinner A64 CCU"
> > +       select SUNXI_CCU_DIV
> > +       select SUNXI_CCU_NK
> > +       select SUNXI_CCU_NKM
> > +       select SUNXI_CCU_NKMP
> > +       select SUNXI_CCU_NM
> > +       select SUNXI_CCU_MP
> > +       select SUNXI_CCU_PHASE
> > +       default ARM64 && ARCH_SUNXI
> > +
> >  config SUN6I_A31_CCU
> >         bool "Support for the Allwinner A31/A31s CCU"
> >         select SUNXI_CCU_DIV
> > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
> > index 106cba27c331..24fbc6e5deb8 100644
> > --- a/drivers/clk/sunxi-ng/Makefile
> > +++ b/drivers/clk/sunxi-ng/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_SUNXI_CCU_NM)    += ccu_nm.o
> >  obj-$(CONFIG_SUNXI_CCU_MP)     += ccu_mp.o
> >
> >  # SoC support
> > +obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
> >  obj-$(CONFIG_SUN6I_A31_CCU)    += ccu-sun6i-a31.o
> >  obj-$(CONFIG_SUN8I_A23_CCU)    += ccu-sun8i-a23.o
> >  obj-$(CONFIG_SUN8I_A33_CCU)    += ccu-sun8i-a33.o
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > new file mode 100644
> > index 000000000000..c0e96bf6d104
> > --- /dev/null
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > @@ -0,0 +1,918 @@
> > +/*
> > + * Copyright (c) 2016 Maxime Ripard. All rights reserved.
> > + *
> > + * This software is licensed under the terms of the GNU General Public
> > + * License version 2, as published by the Free Software Foundation, and
> > + * may be copied, distributed, and modified under those terms.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of_address.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "ccu_common.h"
> > +#include "ccu_reset.h"
> > +
> > +#include "ccu_div.h"
> > +#include "ccu_gate.h"
> > +#include "ccu_mp.h"
> > +#include "ccu_mult.h"
> > +#include "ccu_nk.h"
> > +#include "ccu_nkm.h"
> > +#include "ccu_nkmp.h"
> > +#include "ccu_nm.h"
> > +#include "ccu_phase.h"
> > +
> > +#include "ccu-sun50i-a64.h"
> > +
> > +static struct ccu_nkmp pll_cpux_clk = {
> > +       .enable         = BIT(31),
> > +       .lock           = BIT(28),
> > +       .n              = _SUNXI_CCU_MULT(8, 5),
> > +       .k              = _SUNXI_CCU_MULT(4, 2),
> > +       .m              = _SUNXI_CCU_DIV(0, 2),
> > +       .p              = _SUNXI_CCU_DIV_MAX(16, 2, 4),
> > +       .common         = {
> > +               .reg            = 0x000,
> > +               .hw.init        = CLK_HW_INIT("pll-cpux",
> > +                                             "osc24M",
> > +                                             &ccu_nkmp_ops,
> > +                                             0),
> > +       },
> > +};
> > +
> > +/*
> > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
> > + * the base (2x, 4x and 8x), and one variable divider (the one true
> > + * pll audio).
> > + *
> > + * We don't have any need for the variable divider for now, so we just
> > + * hardcode it to match with the clock names
> > + */
> > +#define SUN50I_A64_PLL_AUDIO_REG       0x008
> > +
> > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
> > +                                  "osc24M", 0x008,
> > +                                  8, 7,        /* N */
> > +                                  0, 5,        /* M */
> > +                                  BIT(31),     /* gate */
> > +                                  BIT(28),     /* lock */
> > +                                  0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
> > +                                       "osc24M", 0x010,
> > +                                       8, 7,           /* N */
> > +                                       0, 4,           /* M */
> > +                                       BIT(24),        /* frac enable */
> > +                                       BIT(25),        /* frac select */
> > +                                       270000000,      /* frac rate 0 */
> > +                                       297000000,      /* frac rate 1 */
> > +                                       BIT(31),        /* gate */
> > +                                       BIT(28),        /* lock */
> > +                                       0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
> > +                                       "osc24M", 0x018,
> > +                                       8, 7,           /* N */
> > +                                       0, 4,           /* M */
> > +                                       BIT(24),        /* frac enable */
> > +                                       BIT(25),        /* frac select */
> > +                                       270000000,      /* frac rate 0 */
> > +                                       297000000,      /* frac rate 1 */
> > +                                       BIT(31),        /* gate */
> > +                                       BIT(28),        /* lock */
> > +                                       0);
> > +
> > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
> > +                                   "osc24M", 0x020,
> > +                                   8, 5,       /* N */
> > +                                   4, 2,       /* K */
> > +                                   0, 2,       /* M */
> > +                                   BIT(31),    /* gate */
> > +                                   BIT(28),    /* lock */
> > +                                   0);
> > +
> > +static struct ccu_nk pll_periph0_clk = {
> > +       .enable         = BIT(31),
> > +       .lock           = BIT(28),
> > +       .n              = _SUNXI_CCU_MULT(8, 5),
> > +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > +       .fixed_post_div = 2,
> > +       .common         = {
> > +               .reg            = 0x028,
> > +               .features       = CCU_FEATURE_FIXED_POSTDIV,
> > +               .hw.init        = CLK_HW_INIT("pll-periph0", "osc24M",
> > +                                             &ccu_nk_ops, 0),
> > +       },
> > +};
> > +
> > +static struct ccu_nk pll_periph1_clk = {
> > +       .enable         = BIT(31),
> > +       .lock           = BIT(28),
> > +       .n              = _SUNXI_CCU_MULT(8, 5),
> > +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > +       .fixed_post_div = 2,
> > +       .common         = {
> > +               .reg            = 0x02c,
> > +               .features       = CCU_FEATURE_FIXED_POSTDIV,
> > +               .hw.init        = CLK_HW_INIT("pll-periph1", "osc24M",
> > +                                             &ccu_nk_ops, 0),
> > +       },
> > +};
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
> > +                                       "osc24M", 0x030,
> > +                                       8, 7,           /* N */
> > +                                       0, 4,           /* M */
> > +                                       BIT(24),        /* frac enable */
> > +                                       BIT(25),        /* frac select */
> > +                                       270000000,      /* frac rate 0 */
> > +                                       297000000,      /* frac rate 1 */
> > +                                       BIT(31),        /* gate */
> > +                                       BIT(28),        /* lock */
> > +                                       0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
> > +                                       "osc24M", 0x038,
> > +                                       8, 7,           /* N */
> > +                                       0, 4,           /* M */
> > +                                       BIT(24),        /* frac enable */
> > +                                       BIT(25),        /* frac select */
> > +                                       270000000,      /* frac rate 0 */
> > +                                       297000000,      /* frac rate 1 */
> > +                                       BIT(31),        /* gate */
> > +                                       BIT(28),        /* lock */
> > +                                       0);
> > +
> > +/*
> > + * The output function can be changed to something more complex that
> > + * we do not handle yet.
> > + *
> > + * Hardcode the mode so that we don't fall in that case.
> > + */
> > +#define SUN50I_A64_PLL_MIPI_REG                0x040
> > +
> > +struct ccu_nkm pll_mipi_clk = {
> > +       .enable         = BIT(31),
> > +       .lock           = BIT(28),
> > +       .n              = _SUNXI_CCU_MULT(8, 4),
> > +       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
> > +       .m              = _SUNXI_CCU_DIV(0, 4),
> > +       .common         = {
> > +               .reg            = 0x040,
> > +               .hw.init        = CLK_HW_INIT("pll-mipi", "pll-video0",
> > +                                             &ccu_nkm_ops, 0),
> > +       },
> > +};
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
> > +                                       "osc24M", 0x044,
> > +                                       8, 7,           /* N */
> > +                                       0, 4,           /* M */
> > +                                       BIT(24),        /* frac enable */
> > +                                       BIT(25),        /* frac select */
> > +                                       270000000,      /* frac rate 0 */
> > +                                       297000000,      /* frac rate 1 */
> > +                                       BIT(31),        /* gate */
> > +                                       BIT(28),        /* lock */
> > +                                       0);
> > +
> > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
> > +                                       "osc24M", 0x048,
> > +                                       8, 7,           /* N */
> > +                                       0, 4,           /* M */
> > +                                       BIT(24),        /* frac enable */
> > +                                       BIT(25),        /* frac select */
> > +                                       270000000,      /* frac rate 0 */
> > +                                       297000000,      /* frac rate 1 */
> > +                                       BIT(31),        /* gate */
> > +                                       BIT(28),        /* lock */
> > +                                       0);
> > +
> > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
> > +                                  "osc24M", 0x04c,
> > +                                  8, 7,        /* N */
> > +                                  0, 2,        /* M */
> > +                                  BIT(31),     /* gate */
> > +                                  BIT(28),     /* lock */
> > +                                  0);
> 
> CLK_SET_RATE_UNGATE for all the PLLs?
> 
> > +
> > +static const char * const cpux_parents[] = { "osc32k", "osc24M",
> > +                                            "pll-cpux" , "pll-cpux" };
> > +static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> > +                    0x050, 16, 2, CLK_IS_CRITICAL);
> 
> CLK_SET_RATE_PARENT.
> 
> [...]
> 
> > +static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
> > +                                 0, 4,         /* M */
> > +                                 16, 2,        /* P */
> > +                                 24, 2,        /* mux */
> > +                                 BIT(31),      /* gate */
> > +                                 0);
> > +
> > +
> 
> Extra newline.
> 
> [...]
> 
> > +static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
> > +static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
> > +                           0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
> 
> The divider is only 2 bits wide.
> 
> > +static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
> > +static const u8 tcon1_table[] = { 0, 2, };
> > +struct ccu_div tcon1_clk = {
> > +       .enable         = BIT(31),
> > +       .div            = _SUNXI_CCU_DIV(0, 4),
> > +       .mux            = _SUNXI_CCU_MUX_TABLE(24, 3, tcon1_table),
> 
> Mux is only 2 bits wide.
> 
> > +       .common         = {
> > +               .reg            = 0x11c,
> > +               .hw.init        = CLK_HW_INIT_PARENTS("tcon1",
> > +                                                     tcon1_parents,
> > +                                                     &ccu_div_ops,
> > +                                                     CLK_SET_RATE_PARENT),
> > +       },
> > +};
> > +
> 
> [...]
> 
> > +static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
> > +static const u8 dsi_dphy_table[] = { 0, 2, };
> > +static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
> > +                                      dsi_dphy_parents, dsi_dphy_table,
> > +                                      0x168, 0, 3, 24, 2, BIT(31), 0);
> 
> Divider is 4 bits wide, and mux offset is 8.

Good catches.

This is fixed, and I'll resend a new serie.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks

[Stephen Boyd]

On 10/11, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> new file mode 100644
> index 000000000000..c0e96bf6d104
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +
> +static int sun50i_a64_ccu_probe(struct platform_device *pdev)
> +{
> +	struct resource *res;
> +	void __iomem *reg;
> +	u32 val;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	reg = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(reg)) {
> +		dev_err(&pdev->dev, "Could not map the clock registers\n");

devm_ioremap_resource() should already spit out an error.

> +		return PTR_ERR(reg);
> +	}
> +
> +	/* Force the PLL-Audio-1x divider to 4 */
> +	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
> +	val &= ~GENMASK(19, 16);
> +	writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
> +
> +	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
> +
> +	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
> +}
> +
> +static const struct of_device_id sun50i_a64_ccu_ids[] = {
> +	{ .compatible = "allwinner,sun50i-a64-ccu" },
> +	{ },

Nitpick: drop the comma

> +};
> +
> +static struct platform_driver sun50i_a64_ccu_driver = {
> +	.probe	= sun50i_a64_ccu_probe,
> +	.driver	= {
> +		.name	= "sun50i-a64-ccu",
> +		.of_match_table	= sun50i_a64_ccu_ids,
> +	},
> +};
> +builtin_platform_driver(sun50i_a64_ccu_driver);

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v4 6/9] clk: sunxi-ng: Add A64 clocks

[Maxime Ripard]

Hi Stephen,

On Thu, Oct 20, 2016 at 11:46:01AM -0700, Stephen Boyd wrote:
> On 10/11, Maxime Ripard wrote:
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > new file mode 100644
> > index 000000000000..c0e96bf6d104
> > --- /dev/null
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> > +
> > +static int sun50i_a64_ccu_probe(struct platform_device *pdev)
> > +{
> > +	struct resource *res;
> > +	void __iomem *reg;
> > +	u32 val;
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	reg = devm_ioremap_resource(&pdev->dev, res);
> > +	if (IS_ERR(reg)) {
> > +		dev_err(&pdev->dev, "Could not map the clock registers\n");
> 
> devm_ioremap_resource() should already spit out an error.
> 
> > +		return PTR_ERR(reg);
> > +	}
> > +
> > +	/* Force the PLL-Audio-1x divider to 4 */
> > +	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
> > +	val &= ~GENMASK(19, 16);
> > +	writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
> > +
> > +	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
> > +
> > +	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
> > +}
> > +
> > +static const struct of_device_id sun50i_a64_ccu_ids[] = {
> > +	{ .compatible = "allwinner,sun50i-a64-ccu" },
> > +	{ },
> 
> Nitpick: drop the comma

Thanks for your comments, it's fixed.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 7/9] arm64: dts: add Allwinner A64 SoC .dtsi

[Maxime Ripard]

From: Andre Przywara <andre.przywara@arm.com>

The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
and the typical tablet / TV box peripherals.
The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
the peripherals and the memory map.
Although the cores are proper 64-bit ones, the whole SoC is actually
limited to 4GB (including all the supported DRAM), so we use 32-bit
address and size cells. This has the nice feature of us being able to
reuse the DT for 32-bit kernels as well.
This .dtsi lists the hardware that we support so far.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
[Maxime: Convert to CCU binding, drop the MMC support for now]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/arm/sunxi.txt |   1 +-
 MAINTAINERS                                     |   1 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi   | 263 +++++++++++++++++-
 3 files changed, 265 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 3975d0a0e4c2..4d6467cc2aa2 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,4 +14,5 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h3
   allwinner,sun9i-a80
+  allwinner,sun50i-a64
   nextthing,gr8
diff --git a/MAINTAINERS b/MAINTAINERS
index 7be47efb2159..926879c05dc6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -983,6 +983,7 @@ L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 N:	sun[x456789]i
 F:	arch/arm/boot/dts/ntc-gr8*
+F:	arch/arm64/boot/dts/allwinner/
 
 ARM/Allwinner SoC Clock Support
 M:	Emilio L?pez <emilio@elopez.com.ar>
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
new file mode 100644
index 000000000000..0f75fec23dc9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ * based on the Allwinner H3 dtsi:
+ *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu at 2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu at 3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			device_type = "cpu";
+			reg = <3>;
+			enable-method = "psci";
+		};
+	};
+
+	osc24M: osc24M_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "osc24M";
+	};
+
+	osc32k: osc32k_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "osc32k";
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		ccu: clock at 01c20000 {
+			compatible = "allwinner,sun50i-a64-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		pio: pinctrl at 1c20800 {
+			compatible = "allwinner,sun50i-a64-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_PIO>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			i2c1_pins: i2c1_pins {
+				allwinner,pins = "PH2", "PH3";
+				allwinner,function = "i2c1";
+			};
+
+			uart0_pins_a: uart0 at 0 {
+				allwinner,pins = "PB8", "PB9";
+				allwinner,function = "uart0";
+			};
+		};
+
+		uart0: serial at 1c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
+			status = "disabled";
+		};
+
+		uart1: serial at 1c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			status = "disabled";
+		};
+
+		uart2: serial at 1c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			status = "disabled";
+		};
+
+		uart3: serial at 1c28c00 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART3>;
+			resets = <&ccu RST_BUS_UART3>;
+			status = "disabled";
+		};
+
+		uart4: serial at 1c29000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c29000 0x400>;
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART4>;
+			resets = <&ccu RST_BUS_UART4>;
+			status = "disabled";
+		};
+
+		rtc: rtc at 1f00000 {
+			compatible = "allwinner,sun6i-a31-rtc";
+			reg = <0x01f00000 0x54>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		i2c0: i2c at 1c2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c at 1c2b000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c at 1c2b400 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C2>;
+			resets = <&ccu RST_BUS_I2C2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gic: interrupt-controller at 1c81000 {
+			compatible = "arm,gic-400";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x2000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+	};
+};
-- 
git-series 0.8.10

[linux-sunxi] [PATCH v4 7/9] arm64: dts: add Allwinner A64 SoC .dtsi

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Andre Przywara <andre.przywara@arm.com>
>
> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> the peripherals and the memory map.
> Although the cores are proper 64-bit ones, the whole SoC is actually
> limited to 4GB (including all the supported DRAM), so we use 32-bit
> address and size cells. This has the nice feature of us being able to
> reuse the DT for 32-bit kernels as well.
> This .dtsi lists the hardware that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> [Maxime: Convert to CCU binding, drop the MMC support for now]
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt |   1 +-
>  MAINTAINERS                                     |   1 +-
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi   | 263 +++++++++++++++++-
>  3 files changed, 265 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 3975d0a0e4c2..4d6467cc2aa2 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,4 +14,5 @@ using one of the following compatible strings:
>    allwinner,sun8i-a83t
>    allwinner,sun8i-h3
>    allwinner,sun9i-a80
> +  allwinner,sun50i-a64
>    nextthing,gr8
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7be47efb2159..926879c05dc6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -983,6 +983,7 @@ L:  linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>  S:     Maintained
>  N:     sun[x456789]i
>  F:     arch/arm/boot/dts/ntc-gr8*
> +F:     arch/arm64/boot/dts/allwinner/
>
>  ARM/Allwinner SoC Clock Support
>  M:     Emilio L?pez <emilio@elopez.com.ar>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> new file mode 100644
> index 000000000000..0f75fec23dc9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -0,0 +1,263 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + * based on the Allwinner H3 dtsi:
> + *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/clock/sun50i-a64-ccu.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +#include <dt-bindings/reset/sun50i-a64-ccu.h>
> +
> +/ {
> +       interrupt-parent = <&gic>;
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu0: cpu at 0 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       reg = <0>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu1: cpu at 1 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       reg = <1>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu2: cpu at 2 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       reg = <2>;
> +                       enable-method = "psci";
> +               };
> +
> +               cpu3: cpu at 3 {
> +                       compatible = "arm,cortex-a53", "arm,armv8";
> +                       device_type = "cpu";
> +                       reg = <3>;
> +                       enable-method = "psci";
> +               };
> +       };
> +
> +       osc24M: osc24M_clk {
> +               #clock-cells = <0>;
> +               compatible = "fixed-clock";
> +               clock-frequency = <24000000>;
> +               clock-output-names = "osc24M";
> +       };
> +
> +       osc32k: osc32k_clk {
> +               #clock-cells = <0>;
> +               compatible = "fixed-clock";
> +               clock-frequency = <32768>;
> +               clock-output-names = "osc32k";
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-0.2";
> +               method = "smc";
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 13
> +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                            <GIC_PPI 14
> +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                            <GIC_PPI 11
> +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> +                            <GIC_PPI 10
> +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +       };
> +
> +       soc {
> +               compatible = "simple-bus";
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges;
> +
> +               ccu: clock at 01c20000 {
> +                       compatible = "allwinner,sun50i-a64-ccu";
> +                       reg = <0x01c20000 0x400>;
> +                       clocks = <&osc24M>, <&osc32k>;
> +                       clock-names = "hosc", "losc";
> +                       #clock-cells = <1>;
> +                       #reset-cells = <1>;
> +               };
> +
> +               pio: pinctrl at 1c20800 {
> +                       compatible = "allwinner,sun50i-a64-pinctrl";
> +                       reg = <0x01c20800 0x400>;
> +                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_PIO>;
> +                       gpio-controller;
> +                       #gpio-cells = <3>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;

I think this should be 3? <bank index flags>?

> +
> +                       i2c1_pins: i2c1_pins {
> +                               allwinner,pins = "PH2", "PH3";
> +                               allwinner,function = "i2c1";
> +                       };
> +
> +                       uart0_pins_a: uart0 at 0 {
> +                               allwinner,pins = "PB8", "PB9";
> +                               allwinner,function = "uart0";
> +                       };
> +               };
> +
> +               uart0: serial at 1c28000 {
> +                       compatible = "snps,dw-apb-uart";
> +                       reg = <0x01c28000 0x400>;
> +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       clocks = <&ccu CLK_BUS_UART0>;
> +                       resets = <&ccu RST_BUS_UART0>;
> +                       status = "disabled";
> +               };
> +
> +               uart1: serial at 1c28400 {
> +                       compatible = "snps,dw-apb-uart";
> +                       reg = <0x01c28400 0x400>;
> +                       interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       clocks = <&ccu CLK_BUS_UART1>;
> +                       resets = <&ccu RST_BUS_UART1>;
> +                       status = "disabled";
> +               };
> +
> +               uart2: serial at 1c28800 {
> +                       compatible = "snps,dw-apb-uart";
> +                       reg = <0x01c28800 0x400>;
> +                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       clocks = <&ccu CLK_BUS_UART2>;
> +                       resets = <&ccu RST_BUS_UART2>;
> +                       status = "disabled";
> +               };
> +
> +               uart3: serial at 1c28c00 {
> +                       compatible = "snps,dw-apb-uart";
> +                       reg = <0x01c28c00 0x400>;
> +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       clocks = <&ccu CLK_BUS_UART3>;
> +                       resets = <&ccu RST_BUS_UART3>;
> +                       status = "disabled";
> +               };
> +
> +               uart4: serial at 1c29000 {
> +                       compatible = "snps,dw-apb-uart";
> +                       reg = <0x01c29000 0x400>;
> +                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +                       reg-shift = <2>;
> +                       reg-io-width = <4>;
> +                       clocks = <&ccu CLK_BUS_UART4>;
> +                       resets = <&ccu RST_BUS_UART4>;
> +                       status = "disabled";
> +               };
> +
> +               rtc: rtc at 1f00000 {
> +                       compatible = "allwinner,sun6i-a31-rtc";
> +                       reg = <0x01f00000 0x54>;
> +                       interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +               };

Should sort by address.

You can keep my Ack after fixing these.

ChenYu

> +
> +               i2c0: i2c at 1c2ac00 {
> +                       compatible = "allwinner,sun6i-a31-i2c";
> +                       reg = <0x01c2ac00 0x400>;
> +                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_I2C0>;
> +                       resets = <&ccu RST_BUS_I2C0>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               i2c1: i2c at 1c2b000 {
> +                       compatible = "allwinner,sun6i-a31-i2c";
> +                       reg = <0x01c2b000 0x400>;
> +                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_I2C1>;
> +                       resets = <&ccu RST_BUS_I2C1>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               i2c2: i2c at 1c2b400 {
> +                       compatible = "allwinner,sun6i-a31-i2c";
> +                       reg = <0x01c2b400 0x400>;
> +                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_I2C2>;
> +                       resets = <&ccu RST_BUS_I2C2>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               gic: interrupt-controller at 1c81000 {
> +                       compatible = "arm,gic-400";
> +                       reg = <0x01c81000 0x1000>,
> +                             <0x01c82000 0x2000>,
> +                             <0x01c84000 0x2000>,
> +                             <0x01c86000 0x2000>;
> +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +                       interrupt-controller;
> +                       #interrupt-cells = <3>;
> +               };
> +       };
> +};
> --
> git-series 0.8.10
>
> --
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> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
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[linux-sunxi] [PATCH v4 7/9] arm64: dts: add Allwinner A64 SoC .dtsi

[Maxime Ripard]

On Thu, Oct 20, 2016 at 11:14:05PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > From: Andre Przywara <andre.przywara@arm.com>
> >
> > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> > and the typical tablet / TV box peripherals.
> > The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
> > the peripherals and the memory map.
> > Although the cores are proper 64-bit ones, the whole SoC is actually
> > limited to 4GB (including all the supported DRAM), so we use 32-bit
> > address and size cells. This has the nice feature of us being able to
> > reuse the DT for 32-bit kernels as well.
> > This .dtsi lists the hardware that we support so far.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> > [Maxime: Convert to CCU binding, drop the MMC support for now]
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> >  Documentation/devicetree/bindings/arm/sunxi.txt |   1 +-
> >  MAINTAINERS                                     |   1 +-
> >  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi   | 263 +++++++++++++++++-
> >  3 files changed, 265 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >
> > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> > index 3975d0a0e4c2..4d6467cc2aa2 100644
> > --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> > @@ -14,4 +14,5 @@ using one of the following compatible strings:
> >    allwinner,sun8i-a83t
> >    allwinner,sun8i-h3
> >    allwinner,sun9i-a80
> > +  allwinner,sun50i-a64
> >    nextthing,gr8
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7be47efb2159..926879c05dc6 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -983,6 +983,7 @@ L:  linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> >  S:     Maintained
> >  N:     sun[x456789]i
> >  F:     arch/arm/boot/dts/ntc-gr8*
> > +F:     arch/arm64/boot/dts/allwinner/
> >
> >  ARM/Allwinner SoC Clock Support
> >  M:     Emilio L?pez <emilio@elopez.com.ar>
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > new file mode 100644
> > index 000000000000..0f75fec23dc9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -0,0 +1,263 @@
> > +/*
> > + * Copyright (C) 2016 ARM Ltd.
> > + * based on the Allwinner H3 dtsi:
> > + *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + *     modify it under the terms of the GNU General Public License as
> > + *     published by the Free Software Foundation; either version 2 of the
> > + *     License, or (at your option) any later version.
> > + *
> > + *     This file is distributed in the hope that it will be useful,
> > + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *     GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + *     obtaining a copy of this software and associated documentation
> > + *     files (the "Software"), to deal in the Software without
> > + *     restriction, including without limitation the rights to use,
> > + *     copy, modify, merge, publish, distribute, sublicense, and/or
> > + *     sell copies of the Software, and to permit persons to whom the
> > + *     Software is furnished to do so, subject to the following
> > + *     conditions:
> > + *
> > + *     The above copyright notice and this permission notice shall be
> > + *     included in all copies or substantial portions of the Software.
> > + *
> > + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + *     OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#include <dt-bindings/clock/sun50i-a64-ccu.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/sun4i-a10.h>
> > +#include <dt-bindings/reset/sun50i-a64-ccu.h>
> > +
> > +/ {
> > +       interrupt-parent = <&gic>;
> > +       #address-cells = <1>;
> > +       #size-cells = <1>;
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu at 0 {
> > +                       compatible = "arm,cortex-a53", "arm,armv8";
> > +                       device_type = "cpu";
> > +                       reg = <0>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu1: cpu at 1 {
> > +                       compatible = "arm,cortex-a53", "arm,armv8";
> > +                       device_type = "cpu";
> > +                       reg = <1>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu2: cpu at 2 {
> > +                       compatible = "arm,cortex-a53", "arm,armv8";
> > +                       device_type = "cpu";
> > +                       reg = <2>;
> > +                       enable-method = "psci";
> > +               };
> > +
> > +               cpu3: cpu at 3 {
> > +                       compatible = "arm,cortex-a53", "arm,armv8";
> > +                       device_type = "cpu";
> > +                       reg = <3>;
> > +                       enable-method = "psci";
> > +               };
> > +       };
> > +
> > +       osc24M: osc24M_clk {
> > +               #clock-cells = <0>;
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <24000000>;
> > +               clock-output-names = "osc24M";
> > +       };
> > +
> > +       osc32k: osc32k_clk {
> > +               #clock-cells = <0>;
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <32768>;
> > +               clock-output-names = "osc32k";
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci-0.2";
> > +               method = "smc";
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts = <GIC_PPI 13
> > +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > +                            <GIC_PPI 14
> > +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > +                            <GIC_PPI 11
> > +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > +                            <GIC_PPI 10
> > +                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > +       };
> > +
> > +       soc {
> > +               compatible = "simple-bus";
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
> > +               ranges;
> > +
> > +               ccu: clock at 01c20000 {
> > +                       compatible = "allwinner,sun50i-a64-ccu";
> > +                       reg = <0x01c20000 0x400>;
> > +                       clocks = <&osc24M>, <&osc32k>;
> > +                       clock-names = "hosc", "losc";
> > +                       #clock-cells = <1>;
> > +                       #reset-cells = <1>;
> > +               };
> > +
> > +               pio: pinctrl at 1c20800 {
> > +                       compatible = "allwinner,sun50i-a64-pinctrl";
> > +                       reg = <0x01c20800 0x400>;
> > +                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&ccu CLK_BUS_PIO>;
> > +                       gpio-controller;
> > +                       #gpio-cells = <3>;
> > +                       interrupt-controller;
> > +                       #interrupt-cells = <2>;
> 
> I think this should be 3? <bank index flags>?
> 
> > +
> > +                       i2c1_pins: i2c1_pins {
> > +                               allwinner,pins = "PH2", "PH3";
> > +                               allwinner,function = "i2c1";
> > +                       };
> > +
> > +                       uart0_pins_a: uart0 at 0 {
> > +                               allwinner,pins = "PB8", "PB9";
> > +                               allwinner,function = "uart0";
> > +                       };
> > +               };
> > +
> > +               uart0: serial at 1c28000 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x01c28000 0x400>;
> > +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > +                       reg-shift = <2>;
> > +                       reg-io-width = <4>;
> > +                       clocks = <&ccu CLK_BUS_UART0>;
> > +                       resets = <&ccu RST_BUS_UART0>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart1: serial at 1c28400 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x01c28400 0x400>;
> > +                       interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> > +                       reg-shift = <2>;
> > +                       reg-io-width = <4>;
> > +                       clocks = <&ccu CLK_BUS_UART1>;
> > +                       resets = <&ccu RST_BUS_UART1>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart2: serial at 1c28800 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x01c28800 0x400>;
> > +                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > +                       reg-shift = <2>;
> > +                       reg-io-width = <4>;
> > +                       clocks = <&ccu CLK_BUS_UART2>;
> > +                       resets = <&ccu RST_BUS_UART2>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart3: serial at 1c28c00 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x01c28c00 0x400>;
> > +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > +                       reg-shift = <2>;
> > +                       reg-io-width = <4>;
> > +                       clocks = <&ccu CLK_BUS_UART3>;
> > +                       resets = <&ccu RST_BUS_UART3>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               uart4: serial at 1c29000 {
> > +                       compatible = "snps,dw-apb-uart";
> > +                       reg = <0x01c29000 0x400>;
> > +                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > +                       reg-shift = <2>;
> > +                       reg-io-width = <4>;
> > +                       clocks = <&ccu CLK_BUS_UART4>;
> > +                       resets = <&ccu RST_BUS_UART4>;
> > +                       status = "disabled";
> > +               };
> > +
> > +               rtc: rtc at 1f00000 {
> > +                       compatible = "allwinner,sun6i-a31-rtc";
> > +                       reg = <0x01f00000 0x54>;
> > +                       interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > +               };
> 
> Should sort by address.
> 
> You can keep my Ack after fixing these.

Indeed, fixed.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v4 8/9] Documentation: devicetree: add vendor prefix for Pine64

[Maxime Ripard]

From: Andre Przywara <andre.przywara@arm.com>

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
[Maxime: Change title prefix to match the usual style]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 7b6bda3b4189..3dd1d77c1c30 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -200,6 +200,7 @@ parade	Parade Technologies Inc.
 pericom	Pericom Technology Inc.
 phytec	PHYTEC Messtechnik GmbH
 picochip	Picochip Ltd
+pine64	Pine64
 plathome	Plat'Home Co., Ltd.
 plda	PLDA
 pixcir  PIXCIR MICROELECTRONICS Co., Ltd
-- 
git-series 0.8.10

[PATCH v4 9/9] arm64: dts: add Pine64 support

[Maxime Ripard]

From: Andre Przywara <andre.przywara@arm.com>

The Pine64 is a cost-efficient development board based on the
Allwinner A64 SoC.
There are three models: the basic version with Fast Ethernet and
512 MB of DRAM (Pine64) and two Pine64+ versions, which both
feature Gigabit Ethernet and additional connectors for touchscreens
and a camera. Or as my son put it: "Those are smaller and these are
missing." ;-)
The two Pine64+ models just differ in the amount of DRAM
(1GB vs. 2GB). Since U-Boot will figure out the right size for us and
patches the DT accordingly we just need to provide one DT for the
Pine64+.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Maxime: Removed the common DTSI and include directly the pine64 DTS]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm64/boot/dts/Makefile                             |  1 +-
 arch/arm64/boot/dts/allwinner/Makefile                   |  5 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 50 ++++++-
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts      | 74 +++++++++-
 4 files changed, 130 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/Makefile
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 6e199c903676..ddcbf5a2c17e 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,4 +1,5 @@
 dts-dirs += al
+dts-dirs += allwinner
 dts-dirs += altera
 dts-dirs += amd
 dts-dirs += amlogic
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
new file mode 100644
index 000000000000..1e29a5ae8282
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
new file mode 100644
index 000000000000..790d14daaa6a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun50i-a64-pine64.dts"
+
+/ {
+	model = "Pine64+";
+	compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
+
+	/* TODO: Camera, Ethernet PHY, touchscreen, etc. */
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
new file mode 100644
index 000000000000..9f127b3d0e33
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2016 ARM Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+/ {
+	model = "Pine64";
+	compatible = "pine64,pine64", "allwinner,sun50i-a64";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+&i2c1_pins {
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
-- 
git-series 0.8.10

[linux-sunxi] [PATCH v4 9/9] arm64: dts: add Pine64 support

[Chen-Yu Tsai]

On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Andre Przywara <andre.przywara@arm.com>
>
> The Pine64 is a cost-efficient development board based on the
> Allwinner A64 SoC.
> There are three models: the basic version with Fast Ethernet and
> 512 MB of DRAM (Pine64) and two Pine64+ versions, which both
> feature Gigabit Ethernet and additional connectors for touchscreens
> and a camera. Or as my son put it: "Those are smaller and these are
> missing." ;-)
> The two Pine64+ models just differ in the amount of DRAM
> (1GB vs. 2GB). Since U-Boot will figure out the right size for us and
> patches the DT accordingly we just need to provide one DT for the
> Pine64+.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> [Maxime: Removed the common DTSI and include directly the pine64 DTS]
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>