[PATCH 0/6] ARM: sun5i: chip: Misc improvements

[PATCH 0/6] ARM: sun5i: chip: Misc improvements

[Maxime Ripard]

Hi,

This is a bunch of patches I gathered for the CHIP, that enables a few
things, like the WiFi regulators (and its associated power sequence), a few
optional buses, etc.

Let me know what you think,
Maxime

Antoine Tenart (1):
  ARM: sun5i: chip: add a node for the w1 gpio controller

Maxime Ripard (5):
  ARM: sun5i: chip: Enable Wi-Fi SDIO chip
  ARM: sun5i: Rename A10s pins
  ARM: sun5i: Add SPI2 pins
  ARM: sun5i: Add RGB 565 LCD pins
  ARM: sun5i: chip: Add optional buses

 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts |  4 +-
 arch/arm/boot/dts/sun5i-a10s.dtsi                |  4 +-
 arch/arm/boot/dts/sun5i-r8-chip.dts              | 69 +++++++++++++++++-
 arch/arm/boot/dts/sun5i.dtsi                     | 24 ++++++-
 4 files changed, 97 insertions(+), 4 deletions(-)

-- 
git-series 0.8.10

[PATCH 1/6] ARM: sun5i: chip: Enable Wi-Fi SDIO chip

[Maxime Ripard]

The WiFi chip is powered through a GPIO and two regulators in parallel.
Since that case is not supported yet, just set them as always on before we
rework the regulator framework to deal with those.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i-r8-chip.dts | 41 ++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index b68a12374b35..e616084b9495 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -74,6 +74,13 @@
 			default-state = "on";
 		};
 	};
+
+	mmc0_pwrseq: mmc0_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&chip_wifi_reg_on_pin>;
+		reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+	};
 };
 
 &be0 {
@@ -131,10 +138,15 @@
 	};
 };
 
+&mmc0_pins_a {
+	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
 &mmc0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins_a>;
 	vmmc-supply = <&reg_vcc3v3>;
+	mmc-pwrseq = <&mmc0_pwrseq>;
 	bus-width = <4>;
 	non-removable;
 	status = "okay";
@@ -156,6 +168,13 @@
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 
+	chip_wifi_reg_on_pin: chip_wifi_reg_on_pin at 0 {
+	        allwinner,pins = "PC19";
+	        allwinner,function = "gpio_out";
+	        allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+	        allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+	};
+
 	chip_id_det_pin: chip_id_det_pin at 0 {
 		allwinner,pins = "PG2";
 		allwinner,function = "gpio_in";
@@ -189,6 +208,28 @@
 	regulator-always-on;
 };
 
+/*
+ * Both LDO3 and LDO4 are used in parallel to power up the WiFi/BT
+ * Chip.
+ *
+ * If those are not enabled, the SDIO part will not enumerate, and
+ * since there's no way currently to pass DT infos to an SDIO device,
+ * we cannot really do better than this ugly hack for now.
+ */
+&reg_ldo3 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-1";
+	regulator-always-on;
+};
+
+&reg_ldo4 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-2";
+	regulator-always-on;
+};
+
 &reg_ldo5 {
 	regulator-min-microvolt = <1800000>;
 	regulator-max-microvolt = <1800000>;
-- 
git-series 0.8.10

[PATCH 2/6] ARM: sun5i: chip: add a node for the w1 gpio controller

[Maxime Ripard]

From: Antoine Tenart <antoine.tenart@free-electrons.com>

The CHIP uses a 1-Wire bus to discover the DIPs. Enable the bus in the DT.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
 arch/arm/boot/dts/sun5i-r8-chip.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index e616084b9495..059d86865b73 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -81,6 +81,13 @@
 		pinctrl-0 = <&chip_wifi_reg_on_pin>;
 		reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
 	};
+
+	onewire {
+		compatible = "w1-gpio";
+		gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+		pinctrl-names = "default";
+		pinctrl-0 = <&chip_w1_pin>;
+	};
 };
 
 &be0 {
@@ -181,6 +188,13 @@
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
+
+	chip_w1_pin: chip_w1_pin at 0 {
+		allwinner,pins = "PD2";
+		allwinner,function = "gpio_in";
+	        allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+	        allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
 };
 
 &reg_dcdc2 {
-- 
git-series 0.8.10

[PATCH 3/6] ARM: sun5i: Rename A10s pins

[Maxime Ripard]

The SPI2 pins on the sun5i PB bank are only available on the A10s. Rename
the A10s only bank so that it doesn't confuse people on the other SoCs
whose indexing would start at b.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 4 ++--
 arch/arm/boot/dts/sun5i-a10s.dtsi                | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index aef91476f9ae..0684d7930d65 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -250,8 +250,8 @@
 
 &spi2 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&spi2_pins_a>,
-		    <&spi2_cs0_pins_a>;
+	pinctrl-0 = <&spi2_pins_b>,
+		    <&spi2_cs0_pins_b>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index c41a2ba34dde..7aa8c7aa0153 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -243,14 +243,14 @@
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 
-	spi2_pins_a: spi2 at 0 {
+	spi2_pins_b: spi2 at 1 {
 		allwinner,pins = "PB12", "PB13", "PB14";
 		allwinner,function = "spi2";
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 	};
 
-	spi2_cs0_pins_a: spi2_cs0 at 0 {
+	spi2_cs0_pins_b: spi2_cs0 at 1 {
 		allwinner,pins = "PB11";
 		allwinner,function = "spi2";
 		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-- 
git-series 0.8.10

[PATCH 4/6] ARM: sun5i: Add SPI2 pins

[Maxime Ripard]

All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the
DT.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index e374f4fc8073..245cee14cf1d 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -591,6 +591,20 @@
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
 
+			spi2_pins_a: spi2 at 0 {
+				allwinner,pins = "PE1", "PE2", "PE3";
+				allwinner,function = "spi2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			spi2_cs0_pins_a: spi2-cs0 at 0 {
+				allwinner,pins = "PE0";
+				allwinner,function = "spi2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			uart3_pins_a: uart3 at 0 {
 				allwinner,pins = "PG9", "PG10";
 				allwinner,function = "uart3";
-- 
git-series 0.8.10

[PATCH 5/6] ARM: sun5i: Add RGB 565 LCD pins

[Maxime Ripard]

Some boards use the LCD in RGB565. Enable the pin muxing option.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 245cee14cf1d..b4ccee8cfb02 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -574,6 +574,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			lcd_rgb565_pins: lcd_rgb565 at 0 {
+				allwinner,pins = "PD3", "PD4", "PD5", "PD6", "PD7",
+						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+						 "PD19", "PD20", "PD21", "PD22", "PD23",
+						 "PD24", "PD25", "PD26", "PD27";
+				allwinner,function = "lcd0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			mmc0_pins_a: mmc0 at 0 {
 				allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 						 "PF4", "PF5";
-- 
git-series 0.8.10

[PATCH 6/6] ARM: sun5i: chip: Add optional buses

[Maxime Ripard]

The I2C1 and SPI2 buses are exposed on the CHIP headers, and are not
explicitly dedicated to anything.

Add them to the DTS with the muxing already set, but keep them disabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/boot/dts/sun5i-r8-chip.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index 059d86865b73..c6da5ad37152 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -56,9 +56,11 @@
 
 	aliases {
 		i2c0 = &i2c0;
+		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		serial0 = &uart1;
 		serial1 = &uart3;
+		spi0 = &spi2;
 	};
 
 	chosen {
@@ -126,6 +128,12 @@
 
 #include "axp209.dtsi"
 
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins_a>;
+	status = "disabled";
+};
+
 &i2c2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c2_pins_a>;
@@ -257,6 +265,12 @@
 	status = "okay";
 };
 
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins_a>;
+	status = "disabled";
+};
+
 &tcon0 {
 	status = "okay";
 };
-- 
git-series 0.8.10

[PATCH 4/6] ARM: sun5i: Add SPI2 pins

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:49 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the
> DT.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 6/6] ARM: sun5i: chip: Add optional buses

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:49 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The I2C1 and SPI2 buses are exposed on the CHIP headers, and are not
> explicitly dedicated to anything.
>
> Add them to the DTS with the muxing already set, but keep them disabled.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

The CHIP docs don't mention SPI2 though.

[PATCH 3/6] ARM: sun5i: Rename A10s pins

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:49 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The SPI2 pins on the sun5i PB bank are only available on the A10s. Rename
> the A10s only bank so that it doesn't confuse people on the other SoCs
> whose indexing would start at b.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 1/6] ARM: sun5i: chip: Enable Wi-Fi SDIO chip

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:48 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The WiFi chip is powered through a GPIO and two regulators in parallel.
> Since that case is not supported yet, just set them as always on before we
> rework the regulator framework to deal with those.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 5/6] ARM: sun5i: Add RGB 565 LCD pins

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:49 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some boards use the LCD in RGB565. Enable the pin muxing option.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 2/6] ARM: sun5i: chip: add a node for the w1 gpio controller

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:48 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Antoine Tenart <antoine.tenart@free-electrons.com>
>
> The CHIP uses a 1-Wire bus to discover the DIPs. Enable the bus in the DT.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 0/6] ARM: sun5i: chip: Misc improvements

[Chen-Yu Tsai]

On Mon, Oct 17, 2016 at 7:48 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> This is a bunch of patches I gathered for the CHIP, that enables a few
> things, like the WiFi regulators (and its associated power sequence), a few
> optional buses, etc.

FYI this series makes more sense if you mention the Pocket CHIP DT overlays.

ChenYu

>
> Let me know what you think,
> Maxime
>
> Antoine Tenart (1):
>   ARM: sun5i: chip: add a node for the w1 gpio controller
>
> Maxime Ripard (5):
>   ARM: sun5i: chip: Enable Wi-Fi SDIO chip
>   ARM: sun5i: Rename A10s pins
>   ARM: sun5i: Add SPI2 pins
>   ARM: sun5i: Add RGB 565 LCD pins
>   ARM: sun5i: chip: Add optional buses
>
>  arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts |  4 +-
>  arch/arm/boot/dts/sun5i-a10s.dtsi                |  4 +-
>  arch/arm/boot/dts/sun5i-r8-chip.dts              | 69 +++++++++++++++++-
>  arch/arm/boot/dts/sun5i.dtsi                     | 24 ++++++-
>  4 files changed, 97 insertions(+), 4 deletions(-)
>
> --
> git-series 0.8.10

[PATCH 0/6] ARM: sun5i: chip: Misc improvements

[Maxime Ripard]

On Fri, Oct 21, 2016 at 11:02:23AM +0800, Chen-Yu Tsai wrote:
> On Mon, Oct 17, 2016 at 7:48 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > This is a bunch of patches I gathered for the CHIP, that enables a few
> > things, like the WiFi regulators (and its associated power sequence), a few
> > optional buses, etc.

Applied all with your Acked-by

> FYI this series makes more sense if you mention the Pocket CHIP DT overlays.

Not really, most of these patches are for the CHIP itself. The Pocket
CHIP, just like all the other DIPs so far, uses the LCD pins, but
that's pretty much the only DIP-specific patch there.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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