From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] irqchip/gic-v3: Convert arm64 GIC accessors to {read, write}_sysreg_s
Date: Fri, 28 Oct 2016 15:54:22 +0100 [thread overview]
Message-ID: <20161028145422.GJ5806@leverpostej> (raw)
In-Reply-To: <1477653838-21569-1-git-send-email-will.deacon@arm.com>
On Fri, Oct 28, 2016 at 12:23:57PM +0100, Will Deacon wrote:
> The GIC system registers are accessed using open-coded wrappers around
> the mrs_s/msr_s asm macros.
>
> This patch moves the code over to the {read,wrote}_sysreg_s accessors
> instead, reducing the amount of explicit asm blocks in the arch headers.
It's nice to see more of this going away!
[...]
> @@ -134,10 +124,12 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
>
> asm volatile(
> "nop;nop;nop;nop\n\t"
> - "nop;nop;nop;nop\n\t"
> - "mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
> - "nop;nop;nop;nop"
> - : "=r" (irqstat));
> + "nop;nop;nop;nop");
> +
> + irqstat = read_sysreg_s(ICC_IAR1_EL1);
> +
> + asm volatile(
> + "nop;nop;nop;nop");
This looks odd, but I see that it disappears in the next patch anyway,
and mirrors the above.
Otherwise, all the transformations look correct to me. FWIW:
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Thanks,
Mark.
prev parent reply other threads:[~2016-10-28 14:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-28 11:23 [PATCH 1/2] irqchip/gic-v3: Convert arm64 GIC accessors to {read, write}_sysreg_s Will Deacon
2016-10-28 11:23 ` [PATCH 2/2] irqchip/gic-v3: Use nops macro for Cavium ThunderX erratum 23154 Will Deacon
2016-10-28 15:10 ` Mark Rutland
2016-10-28 15:16 ` Marc Zyngier
2016-10-28 14:54 ` Mark Rutland [this message]
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