From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] arm/arm64: KVM: VGIC: limit ITARGETSR bits to number of VCPUs
Date: Wed, 16 Nov 2016 20:54:10 +0100 [thread overview]
Message-ID: <20161116195410.GH3811@cbox> (raw)
In-Reply-To: <20161116175716.31578-1-andre.przywara@arm.com>
On Wed, Nov 16, 2016 at 05:57:16PM +0000, Andre Przywara wrote:
> The GICv2 spec says in section 4.3.12 that a "CPU targets field bit that
> corresponds to an unimplemented CPU interface is RAZ/WI."
> Currently we allow the guest to write any value in there and it can
> read that back.
> Mask the written value with the proper CPU mask to be spec compliant.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
next prev parent reply other threads:[~2016-11-16 19:54 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-16 17:57 [PATCH v2] arm/arm64: KVM: VGIC: limit ITARGETSR bits to number of VCPUs Andre Przywara
2016-11-16 19:54 ` Christoffer Dall [this message]
2016-12-06 11:21 ` Marc Zyngier
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