* [PATCH v3 01/12] mmc: sdhci: Export sdhci_set_ios() from sdhci.c
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
@ 2016-12-09 10:29 ` Gregory CLEMENT
2016-12-09 10:29 ` [PATCH v3 02/12] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c Gregory CLEMENT
` (10 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Export sdhci_set_ios() in sdhci.c.
Thus vendor sdhci driver can implement its own set_ios() routine.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 71654b90227f..ea06faf8a437 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1563,7 +1563,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
}
EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
-static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1723,6 +1723,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_set_ios);
static int sdhci_get_cd(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 766df17fb7eb..37771de4cafa 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -688,6 +688,7 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
void sdhci_set_bus_width(struct sdhci_host *host, int width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
+void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 02/12] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
2016-12-09 10:29 ` [PATCH v3 01/12] mmc: sdhci: Export sdhci_set_ios() from sdhci.c Gregory CLEMENT
@ 2016-12-09 10:29 ` Gregory CLEMENT
2016-12-09 10:29 ` [PATCH v3 03/12] mmc: sdhci: Export sdhci_execute_tuning() " Gregory CLEMENT
` (9 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Export sdhci_start_signal_voltage_switch() from sdhci.c.
Thus vendor sdhci driver can implement its own signal voltage
switch routine.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 5 +++--
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ea06faf8a437..8e6e4e37e3b4 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1832,8 +1832,8 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
spin_unlock_irqrestore(&host->lock, flags);
}
-static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
- struct mmc_ios *ios)
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -1925,6 +1925,7 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
return 0;
}
}
+EXPORT_SYMBOL_GPL(sdhci_start_signal_voltage_switch);
static int sdhci_card_busy(struct mmc_host *mmc)
{
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 37771de4cafa..cd18b6f19c3b 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -689,6 +689,8 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width);
void sdhci_reset(struct sdhci_host *host, u8 mask);
void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
+int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 03/12] mmc: sdhci: Export sdhci_execute_tuning() in sdhci.c
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
2016-12-09 10:29 ` [PATCH v3 01/12] mmc: sdhci: Export sdhci_set_ios() from sdhci.c Gregory CLEMENT
2016-12-09 10:29 ` [PATCH v3 02/12] mmc: sdhci: Export sdhci_start_signal_voltage_switch() in sdhci.c Gregory CLEMENT
@ 2016-12-09 10:29 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 04/12] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c Gregory CLEMENT
` (8 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:29 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Export sdhci_execute_tuning() from sdhci.c.
Thus vendor sdhci driver can execute its own tuning process.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 8e6e4e37e3b4..e971abb1368f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1950,7 +1950,7 @@ static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
return 0;
}
-static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct sdhci_host *host = mmc_priv(mmc);
u16 ctrl;
@@ -2139,6 +2139,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
spin_unlock_irqrestore(&host->lock, flags);
return err;
}
+EXPORT_SYMBOL_GPL(sdhci_execute_tuning);
static int sdhci_select_drive_strength(struct mmc_card *card,
unsigned int max_dtr, int host_drv,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index cd18b6f19c3b..95beadc66849 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -691,6 +691,7 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios);
+int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 04/12] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (2 preceding siblings ...)
2016-12-09 10:29 ` [PATCH v3 03/12] mmc: sdhci: Export sdhci_execute_tuning() " Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 05/12] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers Gregory CLEMENT
` (7 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC
driver can implement its specific SDIO irq contorl.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index e971abb1368f..e174379ee019 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1817,7 +1817,7 @@ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
}
}
-static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct sdhci_host *host = mmc_priv(mmc);
unsigned long flags;
@@ -1831,6 +1831,7 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
sdhci_enable_sdio_irq_nolock(host, enable);
spin_unlock_irqrestore(&host->lock, flags);
}
+EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 95beadc66849..a3e8913452fc 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -692,6 +692,7 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios);
int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host);
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 05/12] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (3 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 04/12] mmc: sdhci: Export sdhci_enable_sdio_irq() from sdhci.c Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 06/12] dt: bindings: Add bindings for Marvell Xenon SD Host Controller Gregory CLEMENT
` (6 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host
Controller drivers.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c44795306342..1a5c4c30ea24 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7604,6 +7604,11 @@ M: Nicolas Pitre <nico@fluxnic.net>
S: Odd Fixes
F: drivers/mmc/host/mvsdio.*
+MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
+M: Ziji Hu <huziji@marvell.com>
+L: linux-mmc at vger.kernel.org
+S: Supported
+
MATROX FRAMEBUFFER DRIVER
L: linux-fbdev at vger.kernel.org
S: Orphan
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 06/12] dt: bindings: Add bindings for Marvell Xenon SD Host Controller
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (4 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 05/12] MAINTAINERS: add entry for Marvell Xenon MMC Host Controller drivers Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 07/12] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality Gregory CLEMENT
` (5 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Marvell Xenon SDHC can support eMMC/SD/SDIO.
Add Xenon-specific properties.
Also add properties for Xenon PHY setting.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt | 197 +++++++-
MAINTAINERS | 1 +-
2 files changed, 198 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
new file mode 100644
index 000000000000..c7589f8d4e3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
@@ -0,0 +1,197 @@
+Marvell Xenon SDHCI Controller device tree bindings
+This file documents differences between the core mmc properties
+described by mmc.txt and the properties used by the Xenon implementation.
+
+Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
+Each SDHC is independent and owns independent resources, such as register sets,
+clock and PHY.
+Each SDHC should have an independent device tree node.
+
+Required Properties:
+- compatible: should be one of the following
+ - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SOC.
+ Must provide a second register area and marvell,pad-type.
+ - "marvell,armada-7000-sdhci": For controllers on Armada 7K/8K SOC.
+
+- clocks:
+ Array of clocks required for SDHC.
+ Require at least input clock for Xenon IP core.
+
+- clock-names:
+ Array of names corresponding to clocks property.
+ The input clock for Xenon IP core should be named as "core".
+
+- reg:
+ * For "marvell,armada-3700-sdhci", two register areas.
+ The first one for Xenon IP register. The second one for the Armada 3700 SOC
+ PHY PAD Voltage Control register.
+ Please follow the examples with compatible "marvell,armada-3700-sdhci"
+ in below.
+ Please also check property marvell,pad-type in below.
+
+ * For other compatible strings, one register area for Xenon IP.
+
+Optional Properties:
+- mmc-card:
+ mmc-card child node must be provided when current SDHC is for eMMC.
+ Xenon SDHC often can support both SD and eMMC. This child node indicates that
+ current SDHC is for eMMC card. Thus Xenon eMMC specific configuration and
+ operations can be enabled prior to eMMC init sequence.
+ Please refer to Documentation/devicetree/bindings/mmc/mmc-card.txt.
+ This child node should not be set if current Xenon SDHC is for SD/SDIO.
+
+- bus-width:
+ When 8-bit data bus width is in use for eMMC, this property should be
+ explicitly provided and set as 8.
+ It is optional when data bus width is 4-bit or 1-bit.
+
+- mmc-ddr-1_8v:
+ Select this property when eMMC HS DDR is supported on SDHC side.
+
+- mmc-hs400-1_8v:
+ Select this property when eMMC HS400 is supported on SDHC side.
+
+- no-1-8-v:
+ Select this property when 1.8V signaling voltage supply is unavailable.
+ When this property is enabled, both mmc-ddr-1_8v and mmc-hs400-1_8v should be
+ cleared.
+
+- marvell,xenon-sdhc-id:
+ Indicate the corresponding bit index of current SDHC in
+ SDHC System Operation Control Register Bit[7:0].
+ Set/clear the corresponding bit to enable/disable current SDHC.
+ If Xenon IP contains only one SDHC, this property is optional.
+
+- marvell,xenon-phy-type:
+ Xenon support mutilple types of PHYs.
+ To select eMMC 5.1 PHY, set:
+ marvell,xenon-phy-type = "emmc 5.1 phy"
+ eMMC 5.1 PHY is the default choice if this property is not provided.
+ To select eMMC 5.0 PHY, set:
+ marvell,xenon-phy-type = "emmc 5.0 phy"
+
+ All those types of PHYs can support eMMC, SD and SDIO.
+ Please note that this property only presents the type of PHY.
+ It doesn't stand for the entire SDHC type or property.
+ For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only supports
+ eMMC 5.1.
+
+- marvell,xenon-phy-znr:
+ Set PHY ZNR value.
+ Only available for eMMC PHY 5.1 and eMMC PHY 5.0.
+ Valid range = [0:0x1F].
+ ZNR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-zpr:
+ Set PHY ZPR value.
+ Only available for eMMC PHY 5.1 and eMMC PHY 5.0.
+ Valid range = [0:0x1F].
+ ZPR is set as 0xF by default if this property is not provided.
+
+- marvell,xenon-phy-nr-success-tun:
+ Set the number of required consecutive successful sampling points used to
+ identify a valid sampling window, in tuning process.
+ Valid range = [1:7].
+ Set as 0x4 by default if this property is not provided.
+
+- marvell,xenon-phy-tun-step-divider:
+ Set the divider for calculating TUN_STEP.
+ Set as 64 by default if this property is not provided.
+
+- marvell,xenon-phy-slow-mode:
+ If this property is selected, transfers will bypass PHY.
+ Only available when bus frequency lower than 55MHz in SDR mde.
+ Disabled by default. Please only try this property if timing issues always
+ occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25, SD SDR50 mode.
+
+- marvell,xenon-tun-count:
+ Xenon SDHC SOC usually doesn't provide re-tuning counter in
+ Capabilities Register 3 Bit[11:8].
+ This property provides the re-tuning counter.
+ If this property is not set, default re-tuning counter will
+ be set as 0x9 in driver.
+
+- marvell,pad-type:
+ Type of Armada 3700 SOC PHY PAD Voltage Controller register.
+ Only valid when "marvell,armada-3700-sdhci" is selected.
+ Two types: "sd" and "fixed-1-8v".
+ If "sd" is slected, SOC PHY PAD is set as 3.3V at the beginning and is
+ switched to 1.8V when SD in UHS-I.
+ If "fixed-1-8v" is slected, SOC PHY PAD is fixed 1.8V, such as for eMMC.
+ Please follow the examples with compatible "marvell,armada-3700-sdhci"
+ in below.
+
+Example:
+- For eMMC:
+
+ sdhci at aa0000 {
+ compatible = "marvell,armada-7000-sdhci";
+ reg = <0xaa0000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+ clocks = <&emmc_clk>;
+ clock-names = "core";
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ marvell,xenon-sdhc-id = <0>;
+ marvell,xenon-phy-type = "emmc 5.1 phy";
+ marvell,xenon-tun-count = <11>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmccard: mmccard at 0 {
+ compatible = "mmc-card";
+ reg = <0>;
+ };
+ };
+
+- For SD/SDIO:
+
+ sdhci at ab0000 {
+ compatible = "marvell,armada-7000-sdhci";
+ reg = <0xab0000 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+ vqmmc-supply = <&sd_regulator>;
+ clocks = <&sdclk>;
+ clock-names = "core";
+ bus-width = <4>;
+ marvell,xenon-tun-count = <9>;
+ };
+
+- For eMMC with compatible "marvell,armada-3700-sdhci":
+
+ sdhci at aa0000 {
+ compatible = "marvell,armada-3700-sdhci";
+ reg = <0xaa0000 0x1000>,
+ <phy_addr 0x4>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
+ clocks = <&emmcclk>;
+ clock-names = "core";
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+
+ marvell,pad-type = "fixed-1-8v";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmccard: mmccard at 0 {
+ compatible = "mmc-card";
+ reg = <0>;
+ };
+ };
+
+- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
+
+ sdhci at ab0000 {
+ compatible = "marvell,armada-3700-sdhci";
+ reg = <0xab0000 0x1000>,
+ <phy_addr 0x4>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
+ vqmmc-supply = <&sd_regulator>;
+ clocks = <&sdclk>;
+ clock-names = "core";
+ bus-width = <4>;
+
+ marvell,pad-type = "sd";
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a5c4c30ea24..850a0afb0c8d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7608,6 +7608,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
M: Ziji Hu <huziji@marvell.com>
L: linux-mmc at vger.kernel.org
S: Supported
+F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
MATROX FRAMEBUFFER DRIVER
L: linux-fbdev at vger.kernel.org
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 07/12] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (5 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 06/12] dt: bindings: Add bindings for Marvell Xenon SD Host Controller Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 08/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC Gregory CLEMENT
` (4 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Add Xenon eMMC/SD/SDIO host controller core functionality.
Add Xenon specific intialization process.
Add Xenon specific mmc_host_ops APIs.
Add Xenon specific register definitions.
Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig.
Marvell Xenon SDHC conforms to SD Physical Layer Specification
Version 3.01 and is designed according to the guidelines provided
in the SD Host Controller Standard Specification Version 3.00.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
MAINTAINERS | 1 +-
drivers/mmc/host/Kconfig | 9 +-
drivers/mmc/host/Makefile | 3 +-
drivers/mmc/host/sdhci-xenon.c | 613 ++++++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-xenon.h | 70 ++++-
5 files changed, 696 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-xenon.c
create mode 100644 drivers/mmc/host/sdhci-xenon.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 850a0afb0c8d..bb33286aeb48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7608,6 +7608,7 @@ MARVELL XENON MMC/SD/SDIO HOST CONTROLLER DRIVER
M: Ziji Hu <huziji@marvell.com>
L: linux-mmc at vger.kernel.org
S: Supported
+F: drivers/mmc/host/sdhci-xenon*
F: Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
MATROX FRAMEBUFFER DRIVER
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5274f503a39a..85a53623526a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -798,3 +798,12 @@ config MMC_SDHCI_BRCMSTB
Broadcom STB SoCs.
If unsure, say Y.
+
+config MMC_SDHCI_XENON
+ tristate "Marvell Xenon eMMC/SD/SDIO SDHCI driver"
+ depends on MMC_SDHCI && MMC_SDHCI_PLTFM
+ help
+ This selects Marvell Xenon eMMC/SD/SDIO SDHCI.
+ If you have a machine with integrated Marvell Xenon SDHC IP,
+ say Y or M here.
+ If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index e2bdaaf43184..75eaf743486c 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -80,3 +80,6 @@ obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o
ifeq ($(CONFIG_CB710_DEBUG),y)
CFLAGS-cb710-mmc += -DDEBUG
endif
+
+obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
+sdhci-xenon-driver-y += sdhci-xenon.o
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
new file mode 100644
index 000000000000..0447eba2ca51
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -0,0 +1,613 @@
+/*
+ * Driver for Marvell Xenon SDHC as a platform device
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huziji@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * Inspired by Jisheng Zhang <jszhang@marvell.com>
+ * Special thanks to Video BG4 project team.
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+static int enable_xenon_internal_clk(struct sdhci_host *host)
+{
+ u32 reg;
+ u8 timeout;
+
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg |= SDHCI_CLOCK_INT_EN;
+ sdhci_writel(host, reg, SDHCI_CLOCK_CONTROL);
+ /* Wait max 20 ms */
+ timeout = 20;
+ while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ pr_err("%s: Internal clock never stabilised.\n",
+ mmc_hostname(host->mmc));
+ return -ETIMEDOUT;
+ }
+ timeout--;
+ mdelay(1);
+ }
+
+ return 0;
+}
+
+/* Set SDCLK-off-while-idle */
+static void xenon_set_sdclk_off_idle(struct sdhci_host *host,
+ unsigned char sdhc_id, bool enable)
+{
+ u32 reg;
+ u32 mask;
+
+ reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
+ /* Get the bit shift basing on the SDHC index */
+ mask = (0x1 << (SDHCI_SDCLK_IDLEOFF_ENABLE_SHIFT + sdhc_id));
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
+}
+
+/* Enable/Disable the Auto Clock Gating function */
+static void xenon_set_acg(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
+ if (enable)
+ reg &= ~SDHCI_AUTO_CLKGATE_DISABLE_MASK;
+ else
+ reg |= SDHCI_AUTO_CLKGATE_DISABLE_MASK;
+ sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
+}
+
+/* Enable this SDHC */
+static void xenon_enable_sdhc(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
+ reg |= (BIT(sdhc_id) << SDHCI_SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
+
+ /*
+ * Manually set the flag which all the card types require,
+ * including SD, eMMC, SDIO
+ */
+ host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+}
+
+/* Disable this SDHC */
+static void xenon_disable_sdhc(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHCI_SYS_OP_CTRL);
+ reg &= ~(BIT(sdhc_id) << SDHCI_SLOT_ENABLE_SHIFT);
+ sdhci_writel(host, reg, SDHCI_SYS_OP_CTRL);
+}
+
+/* Enable Parallel Transfer Mode */
+static void xenon_enable_sdhc_parallel_tran(struct sdhci_host *host,
+ unsigned char sdhc_id)
+{
+ u32 reg;
+
+ reg = sdhci_readl(host, SDHCI_SYS_EXT_OP_CTRL);
+ reg |= BIT(sdhc_id);
+ sdhci_writel(host, reg, SDHCI_SYS_EXT_OP_CTRL);
+}
+
+static void xenon_sdhc_tuning_setup(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+
+ /* Disable the Re-Tuning Request functionality */
+ reg = sdhci_readl(host, SDHCI_SLOT_RETUNING_REQ_CTRL);
+ reg &= ~SDHCI_RETUNING_COMPATIBLE;
+ sdhci_writel(host, reg, SDHCI_SLOT_RETUNING_REQ_CTRL);
+
+ /* Disable the Re-tuning Event Signal Enable */
+ reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE);
+ reg &= ~SDHCI_INT_RETUNE;
+ sdhci_writel(host, reg, SDHCI_SIGNAL_ENABLE);
+
+ /* Force to use Tuning Mode 1 */
+ host->tuning_mode = SDHCI_TUNING_MODE_1;
+ /* Set re-tuning period */
+ host->tuning_count = 1 << (priv->tuning_count - 1);
+}
+
+/*
+ * Operations inside struct sdhci_ops
+ */
+/* Recover the Register Setting cleared during SOFTWARE_RESET_ALL */
+static void sdhci_xenon_reset_exit(struct sdhci_host *host,
+ unsigned char sdhc_id, u8 mask)
+{
+ /* Only SOFTWARE RESET ALL will clear the register setting */
+ if (!(mask & SDHCI_RESET_ALL))
+ return;
+
+ /* Disable tuning request and auto-retuning again */
+ xenon_sdhc_tuning_setup(host);
+
+ xenon_set_acg(host, true);
+
+ xenon_set_sdclk_off_idle(host, sdhc_id, false);
+}
+
+static void sdhci_xenon_reset(struct sdhci_host *host, u8 mask)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ sdhci_reset(host, mask);
+ sdhci_xenon_reset_exit(host, priv->sdhc_id, mask);
+}
+
+/*
+ * Xenon defines different values for HS200 and HS400
+ * in Host_Control_2
+ */
+static void xenon_set_uhs_signaling(struct sdhci_host *host,
+ unsigned int timing)
+{
+ u16 ctrl_2;
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if (timing == MMC_TIMING_MMC_HS200)
+ ctrl_2 |= SDHCI_XENON_CTRL_HS200;
+ else if (timing == MMC_TIMING_UHS_SDR104)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+ else if (timing == MMC_TIMING_UHS_SDR12)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ else if (timing == MMC_TIMING_UHS_SDR25)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ else if (timing == MMC_TIMING_UHS_SDR50)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+ else if ((timing == MMC_TIMING_UHS_DDR50) ||
+ (timing == MMC_TIMING_MMC_DDR52))
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+ else if (timing == MMC_TIMING_MMC_HS400)
+ ctrl_2 |= SDHCI_XENON_CTRL_HS400;
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
+
+static const struct sdhci_ops sdhci_xenon_ops = {
+ .set_clock = sdhci_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .reset = sdhci_xenon_reset,
+ .set_uhs_signaling = xenon_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+};
+
+static const struct sdhci_pltfm_data sdhci_xenon_pdata = {
+ .ops = &sdhci_xenon_ops,
+ .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
+ SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+};
+
+/*
+ * Xenon Specific Operations in mmc_host_ops
+ */
+static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ unsigned long flags;
+ u32 reg;
+
+ /*
+ * HS400/HS200/eMMC HS doesn't have Preset Value register.
+ * However, sdhci_set_ios will read HS400/HS200 Preset register.
+ * Disable Preset Value register for HS400/HS200.
+ * eMMC HS with preset_enabled set will trigger a bug in
+ * get_preset_value().
+ */
+ spin_lock_irqsave(&host->lock, flags);
+ if ((ios->timing == MMC_TIMING_MMC_HS400) ||
+ (ios->timing == MMC_TIMING_MMC_HS200) ||
+ (ios->timing == MMC_TIMING_MMC_HS)) {
+ host->preset_enabled = false;
+ host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+
+ reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ reg &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+ sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
+ } else {
+ host->quirks2 &= ~SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ sdhci_set_ios(mmc, ios);
+
+ if (host->clock > SDHCI_DEFAULT_SDCLK_FREQ) {
+ spin_lock_irqsave(&host->lock, flags);
+ xenon_set_sdclk_off_idle(host, priv->sdhc_id, true);
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
+}
+
+static int xenon_emmc_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ unsigned char voltage = ios->signal_voltage;
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned char voltage_code;
+ u32 ctrl;
+
+ if ((voltage == MMC_SIGNAL_VOLTAGE_330) ||
+ (voltage == MMC_SIGNAL_VOLTAGE_180)) {
+ if (voltage == MMC_SIGNAL_VOLTAGE_330)
+ voltage_code = SDHCI_EMMC_VCCQ_3_3V;
+ else if (voltage == MMC_SIGNAL_VOLTAGE_180)
+ voltage_code = SDHCI_EMMC_VCCQ_1_8V;
+
+ /*
+ * This host is for eMMC, XENON self-defined
+ * eMMC control register should be accessed
+ * instead of Host Control 2
+ */
+ ctrl = sdhci_readl(host, SDHCI_SLOT_EMMC_CTRL);
+ ctrl &= ~SDHCI_EMMC_VCCQ_MASK;
+ ctrl |= voltage_code;
+ sdhci_writel(host, ctrl, SDHCI_SLOT_EMMC_CTRL);
+
+ /* There is no standard to determine this waiting period */
+ usleep_range(1000, 2000);
+
+ /* Check whether io voltage switch is done */
+ ctrl = sdhci_readl(host, SDHCI_SLOT_EMMC_CTRL);
+ ctrl &= SDHCI_EMMC_VCCQ_MASK;
+ /*
+ * This bit is set only when regulator feeds back
+ * the voltage switch results to Xenon SDHC.
+ * However, in actaul implementation, regulator might not
+ * provide this feedback.
+ * Thus we shall not rely on this bit to determine
+ * if switch failed.
+ * If the bit is not set, just throw a message.
+ * Besides, error code should not be returned.
+ */
+ if (ctrl != voltage_code)
+ dev_info(mmc_dev(mmc), "fail to detect eMMC signal voltage stable\n");
+ return 0;
+ }
+
+ dev_err(mmc_dev(mmc), "Unsupported signal voltage: %d\n", voltage);
+ return -EINVAL;
+}
+
+static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ /*
+ * Before SD/SDIO set signal voltage, SD bus clock should be
+ * disabled. However, sdhci_set_clock will also disable the Internal
+ * clock in mmc_set_signal_voltage().
+ * If Internal clock is disabled, the 3.3V/1.8V bit can not be updated.
+ * Thus here manually enable internal clock.
+ *
+ * After switch completes, it is unnecessary to disable internal clock,
+ * since keeping internal clock active obeys SD spec.
+ */
+ enable_xenon_internal_clk(host);
+
+ if (priv->init_card_type == MMC_TYPE_MMC)
+ return xenon_emmc_signal_voltage_switch(mmc, ios);
+
+ return sdhci_start_signal_voltage_switch(mmc, ios);
+}
+
+/*
+ * Update card type.
+ * priv->init_card_type will be used in PHY timing adjustment.
+ */
+static void xenon_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+
+ /* Update card type*/
+ priv->init_card_type = card->type;
+}
+
+static int xenon_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+
+ if (host->timing == MMC_TIMING_UHS_DDR50)
+ return 0;
+
+ return sdhci_execute_tuning(mmc, opcode);
+}
+
+static void xenon_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+ u8 sdhc_id = priv->sdhc_id;
+
+ sdhci_enable_sdio_irq(mmc, enable);
+
+ if (enable) {
+ /*
+ * Set SDIO Card Inserted indication
+ * to enable detecting SDIO async irq.
+ */
+ reg = sdhci_readl(host, SDHCI_SYS_CFG_INFO);
+ reg |= (1 << (sdhc_id + SDHCI_SLOT_TYPE_SDIO_SHIFT));
+ sdhci_writel(host, reg, SDHCI_SYS_CFG_INFO);
+ } else {
+ /* Clear SDIO Card Inserted indication */
+ reg = sdhci_readl(host, SDHCI_SYS_CFG_INFO);
+ reg &= ~(1 << (sdhc_id + SDHCI_SLOT_TYPE_SDIO_SHIFT));
+ sdhci_writel(host, reg, SDHCI_SYS_CFG_INFO);
+ }
+}
+
+static void xenon_replace_mmc_host_ops(struct sdhci_host *host)
+{
+ host->mmc_host_ops.set_ios = xenon_set_ios;
+ host->mmc_host_ops.start_signal_voltage_switch =
+ xenon_start_signal_voltage_switch;
+ host->mmc_host_ops.init_card = xenon_init_card;
+ host->mmc_host_ops.execute_tuning = xenon_execute_tuning;
+ host->mmc_host_ops.enable_sdio_irq = xenon_enable_sdio_irq;
+}
+
+/*
+ * Parse child node in Xenon DT.
+ * Search for the following item(s):
+ * - eMMC card type
+ */
+static int xenon_child_node_of_parse(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct mmc_host *mmc = host->mmc;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct device_node *child;
+ int nr_child;
+
+ priv->init_card_type = SDHCI_CARD_TYPE_UNKNOWN;
+
+ nr_child = of_get_child_count(np);
+ if (!nr_child)
+ return 0;
+
+ for_each_child_of_node(np, child) {
+ if (of_device_is_compatible(child, "mmc-card")) {
+ priv->init_card_type = MMC_TYPE_MMC;
+ mmc->caps |= MMC_CAP_NONREMOVABLE;
+
+ /*
+ * Force to clear BUS_TEST to
+ * skip bus_test_pre and bus_test_post
+ */
+ mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST;
+ mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ |
+ MMC_CAP2_PACKED_CMD |
+ MMC_CAP2_NO_SD |
+ MMC_CAP2_NO_SDIO;
+ }
+ of_node_put(child);
+ }
+
+ return 0;
+}
+
+static int xenon_probe_dt(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct mmc_host *mmc = host->mmc;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ int err;
+ u32 sdhc_id, nr_sdhc;
+ u32 tuning_count;
+
+ /* Standard MMC property */
+ err = mmc_of_parse(mmc);
+ if (err)
+ return err;
+
+ /* Standard SDHCI property */
+ sdhci_get_of_property(pdev);
+
+ /*
+ * Xenon Specific property:
+ * init_card_type: check whether this SDHC is for eMMC
+ * sdhc-id: the index of current SDHC.
+ * Refer to SDHCI_SYS_CFG_INFO register
+ * tun-count: the interval between re-tuning
+ */
+ /* Parse child node, including checking emmc type */
+ err = xenon_child_node_of_parse(pdev);
+ if (err)
+ return err;
+
+ priv->sdhc_id = 0x0;
+ if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) {
+ nr_sdhc = sdhci_readl(host, SDHCI_SYS_CFG_INFO);
+ nr_sdhc &= SDHCI_NR_SUPPORTED_SLOT_MASK;
+ if (unlikely(sdhc_id > nr_sdhc)) {
+ dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n",
+ sdhc_id, nr_sdhc);
+ return -EINVAL;
+ }
+ }
+
+ tuning_count = SDHCI_DEF_TUNING_COUNT;
+ if (!of_property_read_u32(np, "marvell,xenon-tun-count",
+ &tuning_count)) {
+ if (unlikely(tuning_count >= SDHCI_TMR_RETUN_NO_PRESENT)) {
+ dev_err(mmc_dev(mmc), "Wrong Re-tuning Count. Set default value %d\n",
+ SDHCI_DEF_TUNING_COUNT);
+ tuning_count = SDHCI_DEF_TUNING_COUNT;
+ }
+ }
+ priv->tuning_count = tuning_count;
+
+ return err;
+}
+
+static int xenon_sdhc_probe(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u8 sdhc_id = priv->sdhc_id;
+
+ /* Enable SDHC */
+ xenon_enable_sdhc(host, sdhc_id);
+
+ /* Enable ACG */
+ xenon_set_acg(host, true);
+
+ /* Enable Parallel Transfer Mode */
+ xenon_enable_sdhc_parallel_tran(host, sdhc_id);
+
+ /* Set tuning functionality of this SDHC */
+ xenon_sdhc_tuning_setup(host);
+
+ return 0;
+}
+
+static void xenon_sdhc_remove(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ u8 sdhc_id = priv->sdhc_id;
+
+ /* disable SDHC */
+ xenon_disable_sdhc(host, sdhc_id);
+}
+
+static int sdhci_xenon_probe(struct platform_device *pdev)
+{
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_host *host;
+ struct sdhci_xenon_priv *priv;
+ int err;
+
+ host = sdhci_pltfm_init(pdev, &sdhci_xenon_pdata,
+ sizeof(struct sdhci_xenon_priv));
+ if (IS_ERR(host))
+ return PTR_ERR(host);
+
+ pltfm_host = sdhci_priv(host);
+ priv = sdhci_pltfm_priv(pltfm_host);
+
+ xenon_set_acg(host, false);
+
+ /*
+ * Link Xenon specific mmc_host_ops function,
+ * to replace standard ones in sdhci_ops.
+ */
+ xenon_replace_mmc_host_ops(host);
+
+ pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pltfm_host->clk)) {
+ err = PTR_ERR(pltfm_host->clk);
+ dev_err(&pdev->dev, "Failed to setup input clk: %d\n", err);
+ goto free_pltfm;
+ }
+ err = clk_prepare_enable(pltfm_host->clk);
+ if (err)
+ goto free_pltfm;
+
+ err = xenon_probe_dt(pdev);
+ if (err)
+ goto err_clk;
+
+ err = xenon_sdhc_probe(host);
+ if (err)
+ goto err_clk;
+
+ err = sdhci_add_host(host);
+ if (err)
+ goto remove_sdhc;
+
+ return 0;
+
+remove_sdhc:
+ xenon_sdhc_remove(host);
+err_clk:
+ clk_disable_unprepare(pltfm_host->clk);
+free_pltfm:
+ sdhci_pltfm_free(pdev);
+ return err;
+}
+
+static int sdhci_xenon_remove(struct platform_device *pdev)
+{
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xFFFFFFFF);
+
+ xenon_sdhc_remove(host);
+
+ sdhci_remove_host(host, dead);
+
+ clk_disable_unprepare(pltfm_host->clk);
+
+ sdhci_pltfm_free(pdev);
+
+ return 0;
+}
+
+static const struct of_device_id sdhci_xenon_dt_ids[] = {
+ { .compatible = "marvell,armada-7000-sdhci",},
+ { .compatible = "marvell,armada-3700-sdhci",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids);
+
+static struct platform_driver sdhci_xenon_driver = {
+ .driver = {
+ .name = "xenon-sdhci",
+ .of_match_table = sdhci_xenon_dt_ids,
+ .pm = &sdhci_pltfm_pmops,
+ },
+ .probe = sdhci_xenon_probe,
+ .remove = sdhci_xenon_remove,
+};
+
+module_platform_driver(sdhci_xenon_driver);
+
+MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
+MODULE_AUTHOR("Hu Ziji <huziji@marvell.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
new file mode 100644
index 000000000000..d50cd663a265
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huziji@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+#ifndef SDHCI_XENON_H_
+#define SDHCI_XENON_H_
+
+
+/* Register Offset of Xenon SDHC self-defined register */
+#define SDHCI_SYS_CFG_INFO 0x0104
+#define SDHCI_SLOT_TYPE_SDIO_SHIFT 24
+#define SDHCI_NR_SUPPORTED_SLOT_MASK 0x7
+
+#define SDHCI_SYS_OP_CTRL 0x0108
+#define SDHCI_AUTO_CLKGATE_DISABLE_MASK BIT(20)
+#define SDHCI_SDCLK_IDLEOFF_ENABLE_SHIFT 8
+#define SDHCI_SLOT_ENABLE_SHIFT 0
+
+#define SDHCI_SYS_EXT_OP_CTRL 0x010C
+
+#define SDHCI_SLOT_EMMC_CTRL 0x0130
+#define SDHCI_EMMC_VCCQ_MASK 0x3
+#define SDHCI_EMMC_VCCQ_1_8V 0x1
+#define SDHCI_EMMC_VCCQ_3_3V 0x3
+
+#define SDHCI_SLOT_RETUNING_REQ_CTRL 0x0144
+/* retuning compatible */
+#define SDHCI_RETUNING_COMPATIBLE 0x1
+
+/* Tuning Parameter */
+#define SDHCI_TMR_RETUN_NO_PRESENT 0xF
+#define SDHCI_DEF_TUNING_COUNT 0x9
+
+#define SDHCI_DEFAULT_SDCLK_FREQ (400000)
+
+/* Xenon specific Mode Select value */
+#define SDHCI_XENON_CTRL_HS200 0x5
+#define SDHCI_XENON_CTRL_HS400 0x6
+
+/* Indicate Card Type is not clear yet */
+#define SDHCI_CARD_TYPE_UNKNOWN 0xF
+
+struct sdhci_xenon_priv {
+ unsigned char tuning_count;
+ /* idx of SDHC */
+ u8 sdhc_id;
+
+ /*
+ * eMMC/SD/SDIO require different PHY settings or
+ * voltage control. It's necessary for Xenon driver to
+ * recognize card type during, or even before initialization.
+ * However, mmc_host->card is not available yet at that time.
+ * This field records the card type during init.
+ * For eMMC, it is updated in dt parse. For SD/SDIO, it is
+ * updated in xenon_init_card().
+ *
+ * It is only valid during initialization after it is updated.
+ * Do not access this variable in normal transfers after
+ * initialization completes.
+ */
+ unsigned int init_card_type;
+};
+
+#endif
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 08/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC.
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (6 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 07/12] mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 18:27 ` kbuild test robot
2016-12-09 18:27 ` [PATCH] mmc: sdhci-xenon: fix boolreturn.cocci warnings kbuild test robot
2016-12-09 10:30 ` [PATCH v3 09/12] mmc: sdhci-xenon: Add SOC PHY PAD voltage control Gregory CLEMENT
` (3 subsequent siblings)
11 siblings, 2 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY.
Multiple types of PHYs are supported.
Add support to multiple types of PHYs init and configuration.
Add register definitions of PHYs.
Xenon PHY cannot fit in kernel common PHY framework.
Xenon SDHC PHY register is a part of Xenon SDHC register set.
Besides, MMC initialization has to call several PHY functions
to complete timing setting.
Those PHY setting functions have to access SDHC registers
and know current MMC setting, such as bus width, clock frequency
and speed mode.
As a result, implement Xenon PHY in MMC host directory.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/Makefile | 2 +-
drivers/mmc/host/sdhci-xenon-phy.c | 799 ++++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-xenon.c | 3 +-
drivers/mmc/host/sdhci-xenon.h | 39 +-
4 files changed, 841 insertions(+), 2 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-xenon-phy.c
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 75eaf743486c..4f2854556ff7 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -82,4 +82,4 @@ ifeq ($(CONFIG_CB710_DEBUG),y)
endif
obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
-sdhci-xenon-driver-y += sdhci-xenon.o
+sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
new file mode 100644
index 000000000000..209c522c5a4b
--- /dev/null
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -0,0 +1,799 @@
+/*
+ * PHY support for Xenon SDHC
+ *
+ * Copyright (C) 2016 Marvell, All Rights Reserved.
+ *
+ * Author: Hu Ziji <huziji@marvell.com>
+ * Date: 2016-8-24
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ */
+
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+
+#include "sdhci-pltfm.h"
+#include "sdhci-xenon.h"
+
+/* Register base for eMMC PHY 5.0 Version */
+#define SDHCI_EMMC_5_0_PHY_REG_BASE 0x0160
+/* Register base for eMMC PHY 5.1 Version */
+#define SDHCI_EMMC_PHY_REG_BASE 0x0170
+
+#define SDHCI_EMMC_PHY_TIMING_ADJUST SDHCI_EMMC_PHY_REG_BASE
+#define SDHCI_EMMC_5_0_PHY_TIMING_ADJUST SDHCI_EMMC_5_0_PHY_REG_BASE
+#define SDHCI_TIMING_ADJUST_SLOW_MODE BIT(29)
+#define SDHCI_TIMING_ADJUST_SDIO_MODE BIT(28)
+#define SDHCI_OUTPUT_QSN_PHASE_SELECT BIT(17)
+#define SDHCI_SAMPL_INV_QSP_PHASE_SELECT BIT(18)
+#define SDHCI_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
+#define SDHCI_PHY_INITIALIZAION BIT(31)
+#define SDHCI_WAIT_CYCLE_BEFORE_USING_MASK 0xF
+#define SDHCI_WAIT_CYCLE_BEFORE_USING_SHIFT 12
+#define SDHCI_FC_SYNC_EN_DURATION_MASK 0xF
+#define SDHCI_FC_SYNC_EN_DURATION_SHIFT 8
+#define SDHCI_FC_SYNC_RST_EN_DURATION_MASK 0xF
+#define SDHCI_FC_SYNC_RST_EN_DURATION_SHIFT 4
+#define SDHCI_FC_SYNC_RST_DURATION_MASK 0xF
+#define SDHCI_FC_SYNC_RST_DURATION_SHIFT 0
+
+#define SDHCI_EMMC_PHY_FUNC_CONTROL (SDHCI_EMMC_PHY_REG_BASE + 0x4)
+#define SDHCI_EMMC_5_0_PHY_FUNC_CONTROL \
+ (SDHCI_EMMC_5_0_PHY_REG_BASE + 0x4)
+#define SDHCI_ASYNC_DDRMODE_MASK BIT(23)
+#define SDHCI_ASYNC_DDRMODE_SHIFT 23
+#define SDHCI_CMD_DDR_MODE BIT(16)
+#define SDHCI_DQ_DDR_MODE_SHIFT 8
+#define SDHCI_DQ_DDR_MODE_MASK 0xFF
+#define SDHCI_DQ_ASYNC_MODE BIT(4)
+
+#define SDHCI_EMMC_PHY_PAD_CONTROL (SDHCI_EMMC_PHY_REG_BASE + 0x8)
+#define SDHCI_EMMC_5_0_PHY_PAD_CONTROL \
+ (SDHCI_EMMC_5_0_PHY_REG_BASE + 0x8)
+#define SDHCI_REC_EN_SHIFT 24
+#define SDHCI_REC_EN_MASK 0xF
+#define SDHCI_FC_DQ_RECEN BIT(24)
+#define SDHCI_FC_CMD_RECEN BIT(25)
+#define SDHCI_FC_QSP_RECEN BIT(26)
+#define SDHCI_FC_QSN_RECEN BIT(27)
+#define SDHCI_OEN_QSN BIT(28)
+#define SDHCI_AUTO_RECEN_CTRL BIT(30)
+#define SDHCI_FC_ALL_CMOS_RECEIVER 0xF000
+
+#define SDHCI_EMMC5_FC_QSP_PD BIT(18)
+#define SDHCI_EMMC5_FC_QSP_PU BIT(22)
+#define SDHCI_EMMC5_FC_CMD_PD BIT(17)
+#define SDHCI_EMMC5_FC_CMD_PU BIT(21)
+#define SDHCI_EMMC5_FC_DQ_PD BIT(16)
+#define SDHCI_EMMC5_FC_DQ_PU BIT(20)
+
+#define SDHCI_EMMC_PHY_PAD_CONTROL1 (SDHCI_EMMC_PHY_REG_BASE + 0xC)
+#define SDHCI_EMMC5_1_FC_QSP_PD BIT(9)
+#define SDHCI_EMMC5_1_FC_QSP_PU BIT(25)
+#define SDHCI_EMMC5_1_FC_CMD_PD BIT(8)
+#define SDHCI_EMMC5_1_FC_CMD_PU BIT(24)
+#define SDHCI_EMMC5_1_FC_DQ_PD 0xFF
+#define SDHCI_EMMC5_1_FC_DQ_PU (0xFF << 16)
+
+#define SDHCI_EMMC_PHY_PAD_CONTROL2 (SDHCI_EMMC_PHY_REG_BASE + 0x10)
+#define SDHCI_EMMC_5_0_PHY_PAD_CONTROL2 \
+ (SDHCI_EMMC_5_0_PHY_REG_BASE + 0xC)
+#define SDHCI_ZNR_MASK 0x1F
+#define SDHCI_ZNR_SHIFT 8
+#define SDHCI_ZPR_MASK 0x1F
+/* Perferred ZNR and ZPR value vary between different boards.
+ * The specific ZNR and ZPR value should be defined here
+ * according to board actual timing.
+ */
+#define SDHCI_ZNR_DEF_VALUE 0xF
+#define SDHCI_ZPR_DEF_VALUE 0xF
+
+#define SDHCI_EMMC_PHY_DLL_CONTROL (SDHCI_EMMC_PHY_REG_BASE + 0x14)
+#define SDHCI_EMMC_5_0_PHY_DLL_CONTROL \
+ (SDHCI_EMMC_5_0_PHY_REG_BASE + 0x10)
+#define SDHCI_DLL_ENABLE BIT(31)
+#define SDHCI_DLL_UPDATE_STROBE_5_0 BIT(30)
+#define SDHCI_DLL_REFCLK_SEL BIT(30)
+#define SDHCI_DLL_UPDATE BIT(23)
+#define SDHCI_DLL_PHSEL1_SHIFT 24
+#define SDHCI_DLL_PHSEL0_SHIFT 16
+#define SDHCI_DLL_PHASE_MASK 0x3F
+#define SDHCI_DLL_PHASE_90_DEGREE 0x1F
+#define SDHCI_DLL_FAST_LOCK BIT(5)
+#define SDHCI_DLL_GAIN2X BIT(3)
+#define SDHCI_DLL_BYPASS_EN BIT(0)
+
+#define SDHCI_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
+ (SDHCI_EMMC_5_0_PHY_REG_BASE + 0x14)
+#define SDHCI_EMMC_PHY_LOGIC_TIMING_ADJUST (SDHCI_EMMC_PHY_REG_BASE + 0x18)
+#define SDHCI_LOGIC_TIMING_VALUE 0x00AA8977
+
+enum soc_pad_ctrl_type {
+ SOC_PAD_SD,
+ SOC_PAD_FIXED_1_8V,
+};
+
+/*
+ * List offset of PHY registers and some special register values
+ * in eMMC PHY 5.0 or eMMC PHY 5.1
+ */
+struct xenon_emmc_phy_regs {
+ /* Offset of Timing Adjust register */
+ u16 timing_adj;
+ /* Offset of Func Control register */
+ u16 func_ctrl;
+ /* Offset of Pad Control register */
+ u16 pad_ctrl;
+ /* Offset of Pad Control register 2 */
+ u16 pad_ctrl2;
+ /* Offset of DLL Control register */
+ u16 dll_ctrl;
+ /* Offset of Logic Timing Adjust register */
+ u16 logic_timing_adj;
+ /* DLL Update Enable bit */
+ u32 dll_update;
+};
+
+static const char * const phy_types[] = {
+ "emmc 5.0 phy",
+ "emmc 5.1 phy"
+};
+
+enum phy_type_enum {
+ EMMC_5_0_PHY,
+ EMMC_5_1_PHY,
+ NR_PHY_TYPES
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
+ .timing_adj = SDHCI_EMMC_5_0_PHY_TIMING_ADJUST,
+ .func_ctrl = SDHCI_EMMC_5_0_PHY_FUNC_CONTROL,
+ .pad_ctrl = SDHCI_EMMC_5_0_PHY_PAD_CONTROL,
+ .pad_ctrl2 = SDHCI_EMMC_5_0_PHY_PAD_CONTROL2,
+ .dll_ctrl = SDHCI_EMMC_5_0_PHY_DLL_CONTROL,
+ .logic_timing_adj = SDHCI_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,
+ .dll_update = SDHCI_DLL_UPDATE_STROBE_5_0,
+};
+
+static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {
+ .timing_adj = SDHCI_EMMC_PHY_TIMING_ADJUST,
+ .func_ctrl = SDHCI_EMMC_PHY_FUNC_CONTROL,
+ .pad_ctrl = SDHCI_EMMC_PHY_PAD_CONTROL,
+ .pad_ctrl2 = SDHCI_EMMC_PHY_PAD_CONTROL2,
+ .dll_ctrl = SDHCI_EMMC_PHY_DLL_CONTROL,
+ .logic_timing_adj = SDHCI_EMMC_PHY_LOGIC_TIMING_ADJUST,
+ .dll_update = SDHCI_DLL_UPDATE,
+};
+
+/*
+ * eMMC PHY configuration and operations
+ */
+struct emmc_phy_params {
+ bool slow_mode;
+
+ u8 znr;
+ u8 zpr;
+
+ /* Nr of consecutive Sampling Points of a Valid Sampling Window */
+ u8 nr_tun_times;
+ /* Divider for calculating Tuning Step */
+ u8 tun_step_divider;
+};
+
+static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
+{
+ struct emmc_phy_params *params;
+
+ params = kzalloc(sizeof(*params), GFP_KERNEL);
+ if (!params)
+ return -ENOMEM;
+
+ priv->phy_params = params;
+ if (priv->phy_type == EMMC_5_0_PHY)
+ priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;
+ else
+ priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;
+
+ return 0;
+}
+
+/*
+ * eMMC 5.0/5.1 PHY init/re-init.
+ * eMMC PHY init should be executed after:
+ * 1. SDCLK frequecny changes.
+ * 2. SDCLK is stopped and re-enabled.
+ * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
+ * are changed
+ */
+static int emmc_phy_init(struct sdhci_host *host)
+{
+ u32 reg;
+ u32 wait, clock;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ reg |= SDHCI_PHY_INITIALIZAION;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+
+ /* Add duration of FC_SYNC_RST */
+ wait = ((reg >> SDHCI_FC_SYNC_RST_DURATION_SHIFT) &
+ SDHCI_FC_SYNC_RST_DURATION_MASK);
+ /* Add interval between FC_SYNC_EN and FC_SYNC_RST */
+ wait += ((reg >> SDHCI_FC_SYNC_RST_EN_DURATION_SHIFT) &
+ SDHCI_FC_SYNC_RST_EN_DURATION_MASK);
+ /* Add duration of asserting FC_SYNC_EN */
+ wait += ((reg >> SDHCI_FC_SYNC_EN_DURATION_SHIFT) &
+ SDHCI_FC_SYNC_EN_DURATION_MASK);
+ /* Add duration of waiting for PHY */
+ wait += ((reg >> SDHCI_WAIT_CYCLE_BEFORE_USING_SHIFT) &
+ SDHCI_WAIT_CYCLE_BEFORE_USING_MASK);
+ /* 4 addtional bus clock and 4 AXI bus clock are required */
+ wait += 8;
+ wait <<= 20;
+
+ clock = host->clock;
+ if (!clock)
+ /* Use the possibly slowest bus frequency value */
+ clock = SDHCI_LOWEST_SDCLK_FREQ;
+ /* get the wait time */
+ wait /= clock;
+ wait++;
+ /* wait for host eMMC PHY init completes */
+ udelay(wait);
+
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ reg &= SDHCI_PHY_INITIALIZAION;
+ if (reg) {
+ dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",
+ wait);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * Enable eMMC PHY HW DLL
+ * DLL should be enabled and stable before HS200/SDR104 tuning,
+ * and before HS400 data strobe setting.
+ */
+static int emmc_phy_enable_dll(struct sdhci_host *host)
+{
+ u32 reg;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+ u8 timeout;
+
+ if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
+ return -EINVAL;
+
+ reg = sdhci_readl(host, phy_regs->dll_ctrl);
+ if (reg & SDHCI_DLL_ENABLE)
+ return 0;
+
+ /* Enable DLL */
+ reg = sdhci_readl(host, phy_regs->dll_ctrl);
+ reg |= (SDHCI_DLL_ENABLE | SDHCI_DLL_FAST_LOCK);
+
+ /*
+ * Set Phase as 90 degree, which is most common value.
+ * Might set another value if necessary.
+ * The granularity is 1 degree.
+ */
+ reg &= ~((SDHCI_DLL_PHASE_MASK << SDHCI_DLL_PHSEL0_SHIFT) |
+ (SDHCI_DLL_PHASE_MASK << SDHCI_DLL_PHSEL1_SHIFT));
+ reg |= ((SDHCI_DLL_PHASE_90_DEGREE << SDHCI_DLL_PHSEL0_SHIFT) |
+ (SDHCI_DLL_PHASE_90_DEGREE << SDHCI_DLL_PHSEL1_SHIFT));
+
+ reg &= ~SDHCI_DLL_BYPASS_EN;
+ reg |= phy_regs->dll_update;
+ if (priv->phy_type == EMMC_5_1_PHY)
+ reg &= ~SDHCI_DLL_REFCLK_SEL;
+ sdhci_writel(host, reg, phy_regs->dll_ctrl);
+
+ /* Wait max 32 ms */
+ timeout = 32;
+ while (!(sdhci_readw(host, SDHCI_SLOT_EXT_PRESENT_STATE) &
+ SDHCI_DLL_LOCK_STATE)) {
+ if (!timeout) {
+ dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");
+ return -ETIMEDOUT;
+ }
+ timeout--;
+ mdelay(1);
+ }
+ return 0;
+}
+
+/*
+ * Config to eMMC PHY to prepare for tuning.
+ * Enable HW DLL and set the TUNING_STEP
+ */
+static int emmc_phy_config_tuning(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+ u32 reg, tuning_step;
+ int ret;
+ unsigned long flags;
+
+ if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))
+ return -EINVAL;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ ret = emmc_phy_enable_dll(host);
+ if (ret) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ return ret;
+ }
+
+ /* Achieve TUNGING_STEP with HW DLL help */
+ reg = sdhci_readl(host, SDHCI_SLOT_DLL_CUR_DLY_VAL);
+ tuning_step = reg / params->tun_step_divider;
+ if (unlikely(tuning_step > SDHCI_TUNING_STEP_MASK)) {
+ dev_warn(mmc_dev(host->mmc),
+ "HS200 TUNING_STEP %d is larger than MAX value\n",
+ tuning_step);
+ tuning_step = SDHCI_TUNING_STEP_MASK;
+ }
+
+ /* Set TUNING_STEP for later tuning */
+ reg = sdhci_readl(host, SDHCI_SLOT_OP_STATUS_CTRL);
+ reg &= ~(SDHCI_TUN_CONSECUTIVE_TIMES_MASK <<
+ SDHCI_TUN_CONSECUTIVE_TIMES_SHIFT);
+ reg |= (params->nr_tun_times << SDHCI_TUN_CONSECUTIVE_TIMES_SHIFT);
+ reg &= ~(SDHCI_TUNING_STEP_MASK << SDHCI_TUNING_STEP_SHIFT);
+ reg |= (tuning_step << SDHCI_TUNING_STEP_SHIFT);
+ sdhci_writel(host, reg, SDHCI_SLOT_OP_STATUS_CTRL);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+ return 0;
+}
+
+static void __emmc_phy_disable_data_strobe(struct sdhci_host *host)
+{
+ u32 reg;
+
+ /* Disable SDHC Data Strobe */
+ reg = sdhci_readl(host, SDHCI_SLOT_EMMC_CTRL);
+ reg &= ~SDHCI_ENABLE_DATA_STROBE;
+ sdhci_writel(host, reg, SDHCI_SLOT_EMMC_CTRL);
+}
+
+/* Set HS400 Data Strobe */
+static void emmc_phy_strobe_delay_adj(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ unsigned long flags;
+ u32 reg;
+
+ if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))
+ return;
+
+ if (host->clock <= MMC_HIGH_52_MAX_DTR)
+ return;
+
+ dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ emmc_phy_enable_dll(host);
+
+ /* Enable SDHC Data Strobe */
+ reg = sdhci_readl(host, SDHCI_SLOT_EMMC_CTRL);
+ reg |= SDHCI_ENABLE_DATA_STROBE;
+ sdhci_writel(host, reg, SDHCI_SLOT_EMMC_CTRL);
+
+ /* Set Data Strobe Pull down */
+ if (priv->phy_type == EMMC_5_0_PHY) {
+ reg = sdhci_readl(host, SDHCI_EMMC_5_0_PHY_PAD_CONTROL);
+ reg |= SDHCI_EMMC5_FC_QSP_PD;
+ reg &= ~SDHCI_EMMC5_FC_QSP_PU;
+ sdhci_writel(host, reg, SDHCI_EMMC_5_0_PHY_PAD_CONTROL);
+ } else {
+ reg = sdhci_readl(host, SDHCI_EMMC_PHY_PAD_CONTROL1);
+ reg |= SDHCI_EMMC5_1_FC_QSP_PD;
+ reg &= ~SDHCI_EMMC5_1_FC_QSP_PU;
+ sdhci_writel(host, reg, SDHCI_EMMC_PHY_PAD_CONTROL1);
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static inline bool temp_stage_hs200_to_hs400(struct sdhci_host *host,
+ struct sdhci_xenon_priv *priv)
+{
+ /*
+ * Tmep stages from HS200 to HS400
+ * from HS200 to HS in 200MHz
+ * from 200MHz to 52MHz
+ */
+ if (((priv->timing == MMC_TIMING_MMC_HS200) &&
+ (host->timing == MMC_TIMING_MMC_HS)) ||
+ ((host->timing == MMC_TIMING_MMC_HS) &&
+ (priv->clock > host->clock)))
+ return true;
+
+ return false;
+}
+
+static inline bool temp_stage_hs400_to_h200(struct sdhci_host *host,
+ struct sdhci_xenon_priv *priv)
+{
+ /*
+ * Temp stages from HS400 t0 HS200:
+ * from 200MHz to 52MHz in HS400
+ * from HS400 to HS DDR in 52MHz
+ * from HS DDR to HS in 52MHz
+ * from HS to HS200 in 52MHz
+ */
+ if (((priv->timing == MMC_TIMING_MMC_HS400) &&
+ ((host->clock == MMC_HIGH_52_MAX_DTR) ||
+ (host->timing == MMC_TIMING_MMC_DDR52))) ||
+ ((priv->timing == MMC_TIMING_MMC_DDR52) &&
+ (host->timing == MMC_TIMING_MMC_HS)) ||
+ ((host->timing == MMC_TIMING_MMC_HS200) &&
+ (host->clock == MMC_HIGH_52_MAX_DTR)))
+ return true;
+
+ return false;
+}
+
+/*
+ * If eMMC PHY Slow Mode is required in lower speed mode in SDR mode
+ * (SDLCK < 55MHz), enable Slow Mode to bypass eMMC PHY.
+ * SDIO slower SDR mode also requires Slow Mode.
+ *
+ * If Slow Mode is enabled, return true.
+ * Otherwise, return false.
+ */
+static bool emmc_phy_slow_mode(struct sdhci_host *host,
+ unsigned char timing)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+ u32 reg;
+
+ /* Skip temp stages from HS200 to HS400 */
+ if (temp_stage_hs200_to_hs400(host, priv))
+ return 0;
+
+ /* Skip temp stages from HS400 t0 HS200 */
+ if (temp_stage_hs400_to_h200(host, priv))
+ return 0;
+
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ /* Enable Slow Mode for SDIO in slower SDR mode */
+ if ((priv->init_card_type == MMC_TYPE_SDIO) &&
+ ((timing == MMC_TIMING_UHS_SDR25) ||
+ (timing == MMC_TIMING_UHS_SDR12) ||
+ (timing == MMC_TIMING_SD_HS) ||
+ (timing == MMC_TIMING_LEGACY))) {
+ reg |= SDHCI_TIMING_ADJUST_SLOW_MODE;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+ return true;
+ }
+
+ /* Check if Slow Mode is required in lower speed mode in SDR mode */
+ if (((timing == MMC_TIMING_UHS_SDR50) ||
+ (timing == MMC_TIMING_UHS_SDR25) ||
+ (timing == MMC_TIMING_UHS_SDR12) ||
+ (timing == MMC_TIMING_SD_HS) ||
+ (timing == MMC_TIMING_MMC_HS) ||
+ (timing == MMC_TIMING_LEGACY)) && params->slow_mode) {
+ reg |= SDHCI_TIMING_ADJUST_SLOW_MODE;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+ return true;
+ }
+
+ reg &= ~SDHCI_TIMING_ADJUST_SLOW_MODE;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+ return false;
+}
+
+/*
+ * Set-up eMMC 5.0/5.1 PHY.
+ * Specific onfiguration depends on the current speed mode in use.
+ */
+static void emmc_phy_set(struct sdhci_host *host,
+ unsigned char timing)
+{
+ u32 reg;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+ struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;
+ unsigned long flags;
+
+ dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ reg = sdhci_readl(host, SDHCI_SYS_EXT_OP_CTRL);
+ reg |= SDHCI_MASK_CMD_CONFLICT_ERROR;
+ sdhci_writel(host, reg, SDHCI_SYS_EXT_OP_CTRL);
+
+ /* Setup pad, set bit[28] and bits[26:24] */
+ reg = sdhci_readl(host, phy_regs->pad_ctrl);
+ reg |= (SDHCI_FC_DQ_RECEN | SDHCI_FC_CMD_RECEN |
+ SDHCI_FC_QSP_RECEN | SDHCI_OEN_QSN);
+ /* All FC_XX_RECEIVCE should be set as CMOS Type */
+ reg |= SDHCI_FC_ALL_CMOS_RECEIVER;
+ sdhci_writel(host, reg, phy_regs->pad_ctrl);
+
+ /* Set CMD and DQ Pull Up */
+ if (priv->phy_type == EMMC_5_0_PHY) {
+ reg = sdhci_readl(host, SDHCI_EMMC_5_0_PHY_PAD_CONTROL);
+ reg |= (SDHCI_EMMC5_FC_CMD_PU | SDHCI_EMMC5_FC_DQ_PU);
+ reg &= ~(SDHCI_EMMC5_FC_CMD_PD | SDHCI_EMMC5_FC_DQ_PD);
+ sdhci_writel(host, reg, SDHCI_EMMC_5_0_PHY_PAD_CONTROL);
+ } else {
+ reg = sdhci_readl(host, SDHCI_EMMC_PHY_PAD_CONTROL1);
+ reg |= (SDHCI_EMMC5_1_FC_CMD_PU | SDHCI_EMMC5_1_FC_DQ_PU);
+ reg &= ~(SDHCI_EMMC5_1_FC_CMD_PD | SDHCI_EMMC5_1_FC_DQ_PD);
+ sdhci_writel(host, reg, SDHCI_EMMC_PHY_PAD_CONTROL1);
+ }
+
+ if (timing == MMC_TIMING_LEGACY)
+ goto phy_init;
+
+ /*
+ * FIXME: should depends on the specific board timing.
+ */
+ if ((timing == MMC_TIMING_MMC_HS400) ||
+ (timing == MMC_TIMING_MMC_HS200) ||
+ (timing == MMC_TIMING_UHS_SDR50) ||
+ (timing == MMC_TIMING_UHS_SDR104) ||
+ (timing == MMC_TIMING_UHS_DDR50) ||
+ (timing == MMC_TIMING_UHS_SDR25) ||
+ (timing == MMC_TIMING_MMC_DDR52)) {
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ reg &= ~SDHCI_OUTPUT_QSN_PHASE_SELECT;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+ }
+
+ /*
+ * If SDIO card, set SDIO Mode
+ * Otherwise, clear SDIO Mode
+ */
+ reg = sdhci_readl(host, phy_regs->timing_adj);
+ if (priv->init_card_type == MMC_TYPE_SDIO)
+ reg |= SDHCI_TIMING_ADJUST_SDIO_MODE;
+ else
+ reg &= ~SDHCI_TIMING_ADJUST_SDIO_MODE;
+ sdhci_writel(host, reg, phy_regs->timing_adj);
+
+ if (emmc_phy_slow_mode(host, timing))
+ goto phy_init;
+
+ /*
+ * Set preferred ZNR and ZPR value
+ * The ZNR and ZPR value vary between different boards.
+ * Define them both in sdhci-xenon-emmc-phy.h.
+ */
+ reg = sdhci_readl(host, phy_regs->pad_ctrl2);
+ reg &= ~((SDHCI_ZNR_MASK << SDHCI_ZNR_SHIFT) | SDHCI_ZPR_MASK);
+ reg |= ((params->znr << SDHCI_ZNR_SHIFT) | params->zpr);
+ sdhci_writel(host, reg, phy_regs->pad_ctrl2);
+
+ /*
+ * When setting EMMC_PHY_FUNC_CONTROL register,
+ * SD clock should be disabled
+ */
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+ reg = sdhci_readl(host, phy_regs->func_ctrl);
+ if ((timing == MMC_TIMING_UHS_DDR50) ||
+ (timing == MMC_TIMING_MMC_HS400) ||
+ (timing == MMC_TIMING_MMC_DDR52))
+ reg |= (SDHCI_DQ_DDR_MODE_MASK << SDHCI_DQ_DDR_MODE_SHIFT) |
+ SDHCI_CMD_DDR_MODE;
+ else
+ reg &= ~((SDHCI_DQ_DDR_MODE_MASK << SDHCI_DQ_DDR_MODE_SHIFT) |
+ SDHCI_CMD_DDR_MODE);
+
+ if (timing == MMC_TIMING_MMC_HS400)
+ reg &= ~SDHCI_DQ_ASYNC_MODE;
+ else
+ reg |= SDHCI_DQ_ASYNC_MODE;
+ sdhci_writel(host, reg, phy_regs->func_ctrl);
+
+ /* Enable bus clock */
+ reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+ reg |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
+
+ if (timing == MMC_TIMING_MMC_HS400)
+ /* Hardware team recommend a value for HS400 */
+ sdhci_writel(host, SDHCI_LOGIC_TIMING_VALUE,
+ phy_regs->logic_timing_adj);
+ else
+ __emmc_phy_disable_data_strobe(host);
+
+phy_init:
+ emmc_phy_init(host);
+
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
+}
+
+static int emmc_phy_parse_param_dt(struct sdhci_host *host,
+ struct device_node *np,
+ struct emmc_phy_params *params)
+{
+ u32 value;
+
+ if (of_property_read_bool(np, "marvell,xenon-phy-slow-mode"))
+ params->slow_mode = true;
+ else
+ params->slow_mode = false;
+
+ if (!of_property_read_u32(np, "marvell,xenon-phy-znr", &value))
+ params->znr = value & SDHCI_ZNR_MASK;
+ else
+ params->znr = SDHCI_ZNR_DEF_VALUE;
+
+ if (!of_property_read_u32(np, "marvell,xenon-phy-zpr", &value))
+ params->zpr = value & SDHCI_ZPR_MASK;
+ else
+ params->zpr = SDHCI_ZPR_DEF_VALUE;
+
+ if (!of_property_read_u32(np, "marvell,xenon-phy-nr-success-tun",
+ &value))
+ params->nr_tun_times = value & SDHCI_TUN_CONSECUTIVE_TIMES_MASK;
+ else
+ params->nr_tun_times = SDHCI_TUN_CONSECUTIVE_TIMES;
+
+ if (!of_property_read_u32(np, "marvell,xenon-phy-tun-step-divider",
+ &value))
+ params->tun_step_divider = value & 0xFF;
+ else
+ params->tun_step_divider = SDHCI_TUNING_STEP_DIVIDER;
+
+ return 0;
+}
+
+/*
+ * Setting PHY when card is working in High Speed Mode.
+ * HS400 set data strobe line.
+ * HS200/SDR104 set tuning config to prepare for tuning.
+ */
+static int xenon_hs_delay_adj(struct sdhci_host *host)
+{
+ int ret = 0;
+
+ if (WARN_ON(host->clock <= SDHCI_DEFAULT_SDCLK_FREQ))
+ return -EINVAL;
+
+ if (host->timing == MMC_TIMING_MMC_HS400) {
+ emmc_phy_strobe_delay_adj(host);
+ return 0;
+ }
+
+ if ((host->timing == MMC_TIMING_MMC_HS200) ||
+ (host->timing == MMC_TIMING_UHS_SDR104)) {
+ ret = emmc_phy_config_tuning(host);
+ if (!ret)
+ return 0;
+ }
+
+ /*
+ * DDR Mode requires driver to scan Sampling Fixed Delay Line,
+ * to find out a perfect operation sampling point.
+ * It is hard to implement such a scan in host driver since initiating
+ * commands by host driver is not safe.
+ * Thus so far just keep PHY Sampling Fixed Delay in default value
+ * in DDR mode.
+ *
+ * If any timing issue occrus in DDR mode on Marvell products,
+ * please contact maintainer to ask for internal support in Marvell.
+ */
+ if ((host->timing == MMC_TIMING_MMC_DDR52) ||
+ (host->timing == MMC_TIMING_UHS_DDR50))
+ dev_warn(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");
+ return ret;
+}
+
+/*
+ * Adjust PHY setting.
+ * PHY setting should be adjusted when SDCLK frequency, Bus Width
+ * or Speed Mode is changed.
+ * Addtional config are required when card is working in High Speed mode,
+ * after leaving Legacy Mode.
+ */
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ int ret = 0;
+
+ if (!host->clock) {
+ priv->clock = 0;
+ return 0;
+ }
+
+ /*
+ * The timing, frequency or bus width is changed,
+ * better to set eMMC PHY based on current setting
+ * and adjust Xenon SDHC delay.
+ */
+ if ((host->clock == priv->clock) &&
+ (ios->bus_width == priv->bus_width) &&
+ (ios->timing == priv->timing))
+ return 0;
+
+ emmc_phy_set(host, ios->timing);
+
+ /* Update the record */
+ priv->bus_width = ios->bus_width;
+
+ /* Skip temp stages from HS200 to HS400 */
+ if (temp_stage_hs200_to_hs400(host, priv))
+ return 0;
+
+ /* Skip temp stages from HS400 t0 HS200 */
+ if (temp_stage_hs400_to_h200(host, priv))
+ return 0;
+
+ priv->timing = ios->timing;
+ priv->clock = host->clock;
+
+ /* Legacy mode is a special case */
+ if (ios->timing == MMC_TIMING_LEGACY)
+ return 0;
+
+ if (host->clock > SDHCI_DEFAULT_SDCLK_FREQ)
+ ret = xenon_hs_delay_adj(host);
+ return ret;
+}
+
+static int add_xenon_phy(struct device_node *np, struct sdhci_host *host,
+ const char *phy_name)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ int i, ret;
+
+ for (i = 0; i < NR_PHY_TYPES; i++) {
+ if (!strcmp(phy_name, phy_types[i])) {
+ priv->phy_type = i;
+ break;
+ }
+ }
+ if (i == NR_PHY_TYPES) {
+ dev_err(mmc_dev(host->mmc),
+ "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
+ phy_name);
+ priv->phy_type = EMMC_5_1_PHY;
+ }
+
+ ret = alloc_emmc_phy(priv);
+ if (ret)
+ return ret;
+
+ return emmc_phy_parse_param_dt(host, np, priv->phy_params);
+}
+
+int xenon_phy_parse_dt(struct device_node *np, struct sdhci_host *host)
+{
+ const char *phy_type = NULL;
+
+ if (!of_property_read_string(np, "marvell,xenon-phy-type", &phy_type))
+ return add_xenon_phy(np, host, phy_type);
+
+ dev_info(mmc_dev(host->mmc), "Fail to get Xenon PHY type. Use default eMMC 5.1 PHY\n");
+ return add_xenon_phy(np, host, "emmc 5.1 phy");
+}
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index 0447eba2ca51..2e47fef490be 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -244,6 +244,7 @@ static void xenon_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
spin_unlock_irqrestore(&host->lock, flags);
sdhci_set_ios(mmc, ios);
+ xenon_phy_adj(host, ios);
if (host->clock > SDHCI_DEFAULT_SDCLK_FREQ) {
spin_lock_irqsave(&host->lock, flags);
@@ -482,7 +483,7 @@ static int xenon_probe_dt(struct platform_device *pdev)
}
priv->tuning_count = tuning_count;
- return err;
+ return xenon_phy_parse_dt(np, host);
}
static int xenon_sdhc_probe(struct sdhci_host *host)
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index d50cd663a265..86b5d2b1f1aa 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -23,8 +23,19 @@
#define SDHCI_SLOT_ENABLE_SHIFT 0
#define SDHCI_SYS_EXT_OP_CTRL 0x010C
+#define SDHCI_MASK_CMD_CONFLICT_ERROR BIT(8)
+
+#define SDHCI_SLOT_OP_STATUS_CTRL 0x0128
+
+#define SDHCI_TUN_CONSECUTIVE_TIMES_SHIFT 16
+#define SDHCI_TUN_CONSECUTIVE_TIMES_MASK 0x7
+#define SDHCI_TUN_CONSECUTIVE_TIMES 0x4
+#define SDHCI_TUNING_STEP_SHIFT 12
+#define SDHCI_TUNING_STEP_MASK 0xF
+#define SDHCI_TUNING_STEP_DIVIDER BIT(6)
#define SDHCI_SLOT_EMMC_CTRL 0x0130
+#define SDHCI_ENABLE_DATA_STROBE BIT(24)
#define SDHCI_EMMC_VCCQ_MASK 0x3
#define SDHCI_EMMC_VCCQ_1_8V 0x1
#define SDHCI_EMMC_VCCQ_3_3V 0x3
@@ -33,11 +44,17 @@
/* retuning compatible */
#define SDHCI_RETUNING_COMPATIBLE 0x1
+#define SDHCI_SLOT_EXT_PRESENT_STATE 0x014C
+#define SDHCI_DLL_LOCK_STATE 0x1
+
+#define SDHCI_SLOT_DLL_CUR_DLY_VAL 0x0150
+
/* Tuning Parameter */
#define SDHCI_TMR_RETUN_NO_PRESENT 0xF
#define SDHCI_DEF_TUNING_COUNT 0x9
#define SDHCI_DEFAULT_SDCLK_FREQ (400000)
+#define SDHCI_LOWEST_SDCLK_FREQ (100000)
/* Xenon specific Mode Select value */
#define SDHCI_XENON_CTRL_HS200 0x5
@@ -65,6 +82,28 @@ struct sdhci_xenon_priv {
* initialization completes.
*/
unsigned int init_card_type;
+
+ /*
+ * The bus_width, timing, and clock fields in below
+ * record the current ios setting of Xenon SDHC.
+ * Driver will adjust PHY setting if any change to
+ * ios affects PHY timing.
+ */
+ unsigned char bus_width;
+ unsigned char timing;
+ unsigned int clock;
+
+ int phy_type;
+ /*
+ * Contains board-specific PHY parameters
+ * passed from device tree.
+ */
+ void *phy_params;
+ struct xenon_emmc_phy_regs *emmc_phy_regs;
};
+
+int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
+int xenon_phy_parse_dt(struct device_node *np,
+ struct sdhci_host *host);
#endif
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 08/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC.
2016-12-09 10:30 ` [PATCH v3 08/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC Gregory CLEMENT
@ 2016-12-09 18:27 ` kbuild test robot
2016-12-09 18:27 ` [PATCH] mmc: sdhci-xenon: fix boolreturn.cocci warnings kbuild test robot
1 sibling, 0 replies; 20+ messages in thread
From: kbuild test robot @ 2016-12-09 18:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi Hu,
[auto build test WARNING on ]
url: https://github.com/0day-ci/linux/commits/Gregory-CLEMENT/mmc-Add-support-to-Marvell-Xenon-SD-Host-Controller/20161210-002602
base:
coccinelle warnings: (new ones prefixed by >>)
>> drivers/mmc/host/sdhci-xenon-phy.c:469:9-10: WARNING: return of 0/1 in function 'emmc_phy_slow_mode' with return type bool
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH] mmc: sdhci-xenon: fix boolreturn.cocci warnings
2016-12-09 10:30 ` [PATCH v3 08/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC Gregory CLEMENT
2016-12-09 18:27 ` kbuild test robot
@ 2016-12-09 18:27 ` kbuild test robot
1 sibling, 0 replies; 20+ messages in thread
From: kbuild test robot @ 2016-12-09 18:27 UTC (permalink / raw)
To: linux-arm-kernel
drivers/mmc/host/sdhci-xenon-phy.c:469:9-10: WARNING: return of 0/1 in function 'emmc_phy_slow_mode' with return type bool
Return statements in functions returning bool should use
true/false instead of 1/0.
Generated by: scripts/coccinelle/misc/boolreturn.cocci
CC: Hu Ziji <huziji@marvell.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
sdhci-xenon-phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -466,11 +466,11 @@ static bool emmc_phy_slow_mode(struct sd
/* Skip temp stages from HS200 to HS400 */
if (temp_stage_hs200_to_hs400(host, priv))
- return 0;
+ return false;
/* Skip temp stages from HS400 t0 HS200 */
if (temp_stage_hs400_to_h200(host, priv))
- return 0;
+ return false;
reg = sdhci_readl(host, phy_regs->timing_adj);
/* Enable Slow Mode for SDIO in slower SDR mode */
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 09/12] mmc: sdhci-xenon: Add SOC PHY PAD voltage control
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (7 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 08/12] mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 10/12] arm64: dts: marvell: add eMMC support for Armada 37xx Gregory CLEMENT
` (2 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
From: Hu Ziji <huziji@marvell.com>
Some SOCs have PHY PAD outside Xenon IP.
PHY PAD voltage should match signalling voltage in use.
Add generic SOC PHY PAD voltage control interface.
Implement Aramda-3700 SOC PHY PAD voltage control.
Signed-off-by: Hu Ziji <huziji@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/mmc/host/sdhci-xenon-phy.c | 111 +++++++++++++++++++++++++++++-
drivers/mmc/host/sdhci-xenon.c | 2 +-
drivers/mmc/host/sdhci-xenon.h | 2 +-
3 files changed, 114 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c
index 209c522c5a4b..21b3f834f1d1 100644
--- a/drivers/mmc/host/sdhci-xenon-phy.c
+++ b/drivers/mmc/host/sdhci-xenon-phy.c
@@ -148,6 +148,22 @@ enum phy_type_enum {
NR_PHY_TYPES
};
+struct soc_pad_ctrl_table {
+ const char *soc;
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
+struct soc_pad_ctrl {
+ /* Register address of SOC PHY PAD ctrl */
+ void __iomem *reg;
+ /* SOC PHY PAD ctrl type */
+ enum soc_pad_ctrl_type pad_type;
+ /* SOC specific operation to set SOC PHY PAD */
+ void (*set_soc_pad)(struct sdhci_host *host,
+ unsigned char signal_voltage);
+};
+
static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {
.timing_adj = SDHCI_EMMC_5_0_PHY_TIMING_ADJUST,
.func_ctrl = SDHCI_EMMC_5_0_PHY_FUNC_CONTROL,
@@ -181,6 +197,8 @@ struct emmc_phy_params {
u8 nr_tun_times;
/* Divider for calculating Tuning Step */
u8 tun_step_divider;
+
+ struct soc_pad_ctrl pad_ctrl;
};
static int alloc_emmc_phy(struct sdhci_xenon_priv *priv)
@@ -257,6 +275,45 @@ static int emmc_phy_init(struct sdhci_host *host)
return 0;
}
+#define ARMADA_3700_SOC_PAD_1_8V 0x1
+#define ARMADA_3700_SOC_PAD_3_3V 0x0
+
+static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,
+ unsigned char signal_voltage)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+
+ if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {
+ writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+ } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {
+ if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);
+ else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
+ writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);
+ }
+}
+
+/*
+ * Set SOC PHY voltage PAD control register,
+ * according to the operation voltage on PAD.
+ * The detailed operation depends on SOC implementaion.
+ */
+static void emmc_phy_set_soc_pad(struct sdhci_host *host,
+ unsigned char signal_voltage)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);
+ struct emmc_phy_params *params = priv->phy_params;
+
+ if (!params->pad_ctrl.reg)
+ return;
+
+ if (params->pad_ctrl.set_soc_pad)
+ params->pad_ctrl.set_soc_pad(host, signal_voltage);
+}
+
/*
* Enable eMMC PHY HW DLL
* DLL should be enabled and stable before HS200/SDR104 tuning,
@@ -630,6 +687,51 @@ static void emmc_phy_set(struct sdhci_host *host,
dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");
}
+static int get_dt_pad_ctrl_data(struct sdhci_host *host,
+ struct device_node *np,
+ struct emmc_phy_params *params)
+{
+ int ret = 0;
+ const char *name;
+ struct resource iomem;
+
+ if (of_device_is_compatible(np, "marvell,armada-3700-sdhci"))
+ params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;
+ else
+ return 0;
+
+ if (of_address_to_resource(np, 1, &iomem)) {
+ dev_err(mmc_dev(host->mmc), "Unable to find SOC PAD ctrl register address for %s\n",
+ np->name);
+ return -EINVAL;
+ }
+
+ params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),
+ &iomem);
+ if (IS_ERR(params->pad_ctrl.reg)) {
+ dev_err(mmc_dev(host->mmc), "Unable to get SOC PHY PAD ctrl regiser for %s\n",
+ np->name);
+ return PTR_ERR(params->pad_ctrl.reg);
+ }
+
+ ret = of_property_read_string(np, "marvell,pad-type", &name);
+ if (ret) {
+ dev_err(mmc_dev(host->mmc), "Unable to determine SOC PHY PAD ctrl type\n");
+ return ret;
+ }
+ if (!strcmp(name, "sd")) {
+ params->pad_ctrl.pad_type = SOC_PAD_SD;
+ } else if (!strcmp(name, "fixed-1-8v")) {
+ params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;
+ } else {
+ dev_err(mmc_dev(host->mmc), "Unsupported SOC PHY PAD ctrl type %s\n",
+ name);
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
static int emmc_phy_parse_param_dt(struct sdhci_host *host,
struct device_node *np,
struct emmc_phy_params *params)
@@ -663,7 +765,14 @@ static int emmc_phy_parse_param_dt(struct sdhci_host *host,
else
params->tun_step_divider = SDHCI_TUNING_STEP_DIVIDER;
- return 0;
+ return get_dt_pad_ctrl_data(host, np, params);
+}
+
+/* Set SOC PHY Voltage PAD */
+void xenon_soc_pad_ctrl(struct sdhci_host *host,
+ unsigned char signal_voltage)
+{
+ emmc_phy_set_soc_pad(host, signal_voltage);
}
/*
diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c
index 2e47fef490be..21abacf2e9b8 100644
--- a/drivers/mmc/host/sdhci-xenon.c
+++ b/drivers/mmc/host/sdhci-xenon.c
@@ -322,6 +322,8 @@ static int xenon_start_signal_voltage_switch(struct mmc_host *mmc,
*/
enable_xenon_internal_clk(host);
+ xenon_soc_pad_ctrl(host, ios->signal_voltage);
+
if (priv->init_card_type == MMC_TYPE_MMC)
return xenon_emmc_signal_voltage_switch(mmc, ios);
diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h
index 86b5d2b1f1aa..a8312e36a03c 100644
--- a/drivers/mmc/host/sdhci-xenon.h
+++ b/drivers/mmc/host/sdhci-xenon.h
@@ -106,4 +106,6 @@ struct sdhci_xenon_priv {
int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);
int xenon_phy_parse_dt(struct device_node *np,
struct sdhci_host *host);
+void xenon_soc_pad_ctrl(struct sdhci_host *host,
+ unsigned char signal_voltage);
#endif
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 10/12] arm64: dts: marvell: add eMMC support for Armada 37xx
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (8 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 09/12] mmc: sdhci-xenon: Add SOC PHY PAD voltage control Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K Gregory CLEMENT
2016-12-09 10:30 ` [PATCH v3 12/12] arm64: configs: enable SDHCI driver for Xenon Gregory CLEMENT
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720
DB board.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 17 +++++++++++++++++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 11 +++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6aaa4..707625031e29 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -72,6 +72,23 @@
status = "okay";
};
+&sdhci0 {
+ non-removable;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ marvell,xenon-emmc;
+ marvell,pad-type = "fixed-1-8v";
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mmccard: mmccard at 0 {
+ compatible = "mmc-card";
+ reg = <0>;
+ };
+};
+
/* CON31 */
&usb3 {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c4762538ec01..0c4cafe92e66 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -161,6 +161,17 @@
};
};
+ sdhci0: sdhci at d8000 {
+ compatible = "marvell,armada-3700-sdhci",
+ "marvell,sdhci-xenon";
+ reg = <0xd8000 0x300
+ 0x17808 0x4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&nb_perih_clk 0>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
sata: sata at e0000 {
compatible = "marvell,armada-3700-ahci";
reg = <0xe0000 0x2000>;
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (9 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 10/12] arm64: dts: marvell: add eMMC support for Armada 37xx Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
2016-12-09 20:07 ` Russell King - ARM Linux
2016-12-09 10:30 ` [PATCH v3 12/12] arm64: configs: enable SDHCI driver for Xenon Gregory CLEMENT
11 siblings, 1 reply; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Also enable it on the Armada 7040 DB board
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 7 +++++++
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 9 +++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 070b589680c5..f7f978a12a49 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -146,3 +146,10 @@
&cpm_usb3_1 {
status = "okay";
};
+
+&sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index 7b6136182ad0..e812fb59fb80 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -229,6 +229,15 @@
};
+ sdhci0: sdhci at 6e0000 {
+ compatible = "marvell,armada-7000-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&cpm_syscon0 1 4>;
+ status = "disabled";
+ };
+
ap_syscon: system-controller at 6f4000 {
compatible = "marvell,ap806-system-controller",
"syscon";
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
2016-12-09 10:30 ` [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K Gregory CLEMENT
@ 2016-12-09 20:07 ` Russell King - ARM Linux
2016-12-12 16:37 ` Gregory CLEMENT
0 siblings, 1 reply; 20+ messages in thread
From: Russell King - ARM Linux @ 2016-12-09 20:07 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Dec 09, 2016 at 11:30:07AM +0100, Gregory CLEMENT wrote:
> Also enable it on the Armada 7040 DB board
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Hi,
Can this also be added to the cp110 on the 7k/8k SoCs as well, or does
it rely on other unmerged support?
Thanks.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
2016-12-09 20:07 ` Russell King - ARM Linux
@ 2016-12-12 16:37 ` Gregory CLEMENT
2016-12-12 19:16 ` Russell King - ARM Linux
0 siblings, 1 reply; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-12 16:37 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell King,
On ven., d?c. 09 2016, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:
> On Fri, Dec 09, 2016 at 11:30:07AM +0100, Gregory CLEMENT wrote:
>> Also enable it on the Armada 7040 DB board
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> Hi,
>
> Can this also be added to the cp110 on the 7k/8k SoCs as well, or does
> it rely on other unmerged support?
I did not add this one because until now I had not the hardware setup
available to test it.
But at least I can add the ressources in the device tree and now I can
test it partially.
Gregory
>
> Thanks.
>
> --
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
> according to speedtest.net.
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
2016-12-12 16:37 ` Gregory CLEMENT
@ 2016-12-12 19:16 ` Russell King - ARM Linux
2016-12-12 20:18 ` Thomas Petazzoni
2016-12-12 21:18 ` Marcin Wojtas
0 siblings, 2 replies; 20+ messages in thread
From: Russell King - ARM Linux @ 2016-12-12 19:16 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Dec 12, 2016 at 05:37:56PM +0100, Gregory CLEMENT wrote:
> Hi Russell King,
>
> On ven., d?c. 09 2016, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:
>
> > On Fri, Dec 09, 2016 at 11:30:07AM +0100, Gregory CLEMENT wrote:
> >> Also enable it on the Armada 7040 DB board
> >>
> >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> >
> > Hi,
> >
> > Can this also be added to the cp110 on the 7k/8k SoCs as well, or does
> > it rely on other unmerged support?
>
> I did not add this one because until now I had not the hardware setup
> available to test it.
>
> But at least I can add the ressources in the device tree and now I can
> test it partially.
There's another option: add the DT resources in a separate patch, send
it out for someone else to test. When it comes back with a tested-by,
then it can be included along with the rest of the patch set.
I'd send something, but I don't know what the GIC interrupt number
would be without using the CP110's ICU (which isn't supported in
mainline yet.) I've already tested your previous patch set (along with
ICU support + needed DT bits) on the SR Macchiatobin board... it seems
to work fine.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
2016-12-12 19:16 ` Russell King - ARM Linux
@ 2016-12-12 20:18 ` Thomas Petazzoni
2016-12-12 21:18 ` Marcin Wojtas
1 sibling, 0 replies; 20+ messages in thread
From: Thomas Petazzoni @ 2016-12-12 20:18 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Mon, 12 Dec 2016 19:16:51 +0000, Russell King - ARM Linux wrote:
> I'd send something, but I don't know what the GIC interrupt number
> would be without using the CP110's ICU (which isn't supported in
> mainline yet.)
For now, mainline relies on a static mapping of CP interrupts to GIC
interrupts, via an ICU configuration done in ATF. It's pretty
straightforward to figure out the CP interrupts to GIC interrupt
mapping if you have access to the ATF source code. If you don't, I can
provide the necessary details.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K
2016-12-12 19:16 ` Russell King - ARM Linux
2016-12-12 20:18 ` Thomas Petazzoni
@ 2016-12-12 21:18 ` Marcin Wojtas
1 sibling, 0 replies; 20+ messages in thread
From: Marcin Wojtas @ 2016-12-12 21:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi Gregory,
2016-12-12 20:16 GMT+01:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
> On Mon, Dec 12, 2016 at 05:37:56PM +0100, Gregory CLEMENT wrote:
>> Hi Russell King,
>>
>> On ven., d?c. 09 2016, Russell King - ARM Linux <linux@armlinux.org.uk> wrote:
>>
>> > On Fri, Dec 09, 2016 at 11:30:07AM +0100, Gregory CLEMENT wrote:
>> >> Also enable it on the Armada 7040 DB board
>> >>
>> >> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> >
>> > Hi,
>> >
>> > Can this also be added to the cp110 on the 7k/8k SoCs as well, or does
>> > it rely on other unmerged support?
>>
>> I did not add this one because until now I had not the hardware setup
>> available to test it.
>>
>> But at least I can add the ressources in the device tree and now I can
>> test it partially.
>
> There's another option: add the DT resources in a separate patch, send
> it out for someone else to test. When it comes back with a tested-by,
> then it can be included along with the rest of the patch set.
I work on A7040-DB with SD slot from AP and CP eMMC. If you have the
board, you can use eMMC module from A3720-DB and plug it to CON11.
Some small soldering may be required. Anyway, you can also just let me
test it:)
Best regards,
Marcin
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 12/12] arm64: configs: enable SDHCI driver for Xenon
2016-12-09 10:29 [PATCH v3 00/12] mmc: Add support to Marvell Xenon SD Host Controller Gregory CLEMENT
` (10 preceding siblings ...)
2016-12-09 10:30 ` [PATCH v3 11/12] arm64: dts: marvell: add sdhci support for Armada 7K/8K Gregory CLEMENT
@ 2016-12-09 10:30 ` Gregory CLEMENT
11 siblings, 0 replies; 20+ messages in thread
From: Gregory CLEMENT @ 2016-12-09 10:30 UTC (permalink / raw)
To: linux-arm-kernel
This patch enables the driver for the SDHCI controller found on the
Marvell Armada 3700 and 7K/8K ARM64 SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dab2cb0c1f1c..2d1f5ee62b18 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -353,6 +353,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_EXYNOS=y
CONFIG_MMC_DW_K3=y
CONFIG_MMC_SUNXI=y
+CONFIG_MMC_SDHCI_XENON=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
git-series 0.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread