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From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [Question] A question about arm64 pte
Date: Mon, 16 Jan 2017 14:39:18 +0000	[thread overview]
Message-ID: <20170116143918.GC6832@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <20170116143601.GB6832@e104818-lin.cambridge.arm.com>

On Mon, Jan 16, 2017 at 02:36:02PM +0000, Catalin Marinas wrote:
> On Mon, Jan 16, 2017 at 08:39:56PM +0800, Yisheng Xie wrote:
> > On 2017/1/16 19:56, Catalin Marinas wrote:
> > > On Mon, Jan 16, 2017 at 06:08:47PM +0800, Yisheng Xie wrote:
> > >> I have question about arm64 pte.
> > > 
> > > I assume the context is ARMv8.0 (without hardware DBM support).
> > 
> > Yes.
> > > 
> > >> For arm64, PTE_WRITE?== PTE_DBM? is to mark whether the page is writable,
> > >> and PTE_DIRTY is to mark whether the page is dirty.
> > >> However, PTE_RDONLY is only cleared when both PTE_WRITE and PTE_DIRTY are set.
> > > 
> > > That's what set_pte_at() does.
> > > 
> > 
> > So if we mmap a memory region use /dev/mem like:
> >    fildes = open("/dev/mem", O_RDWR | O_CREAT, 0777);
> >    addr = mmap(NULL, LEN, PROT_READ | PROT_WRITE, MAP_SHARED, fildes, offset);
> > 
> > The PTE_RDONLY will be set? Right ?
> 
> Possibly, I haven't checked mmap_mem(). However, that's what you would
> get with an anonymous mmap() as well.

A correction on anonymous mmap(): the original page links to a zeroed
page, so when dirtying it you also get a new copy, so slightly different
code path from handle_pte_fault().

-- 
Catalin

  reply	other threads:[~2017-01-16 14:39 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-16 10:08 [Question] A question about arm64 pte Yisheng Xie
2017-01-16 11:56 ` Catalin Marinas
2017-01-16 12:39   ` Yisheng Xie
2017-01-16 12:57     ` Steve Capper
2017-01-17  1:04       ` Yisheng Xie
2017-01-16 14:36     ` Catalin Marinas
2017-01-16 14:39       ` Catalin Marinas [this message]
2017-01-17  1:02       ` Yisheng Xie
2017-01-17  3:53       ` Yisheng Xie
2017-01-17 11:45         ` Catalin Marinas
2017-01-17 12:02           ` Yisheng Xie

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