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From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [Question] A question about arm64 pte
Date: Tue, 17 Jan 2017 11:45:19 +0000	[thread overview]
Message-ID: <20170117114518.GF18923@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <ecf2bd9f-9f96-0e6d-564d-93cff5bbf0cb@huawei.com>

On Tue, Jan 17, 2017 at 11:53:43AM +0800, Yisheng Xie wrote:
> On 2017/1/16 22:36, Catalin Marinas wrote:
> > On Mon, Jan 16, 2017 at 08:39:56PM +0800, Yisheng Xie wrote:
> >> On 2017/1/16 19:56, Catalin Marinas wrote:
> >>> On Mon, Jan 16, 2017 at 06:08:47PM +0800, Yisheng Xie wrote:
> >>>
> >> However?when use memset to write the region it still works well, and
> >> the bit PTE_RDONLY is also cleared. Is there anywhere clear the
> >> PTE_RDONLY before write that page ?
> > 
> > See handle_pte_fault(). On the first access to a writable+clean page
> > (PTE_WRITE set, PTE_RDONLY set, PTE_DIRTY cleared), the kernel traps it
> > and, if pte_write() is true (your case), it calls pte_mkdirty(). The
> > subsequently called ptep_set_access_flags() function would clear
> > PTE_RDONLY, giving you a writable mapping.
> 
> Sorry to disturb, but why page fault will happened here, for pte already
> present with AF bit set?
> 
> Here is what I get when mmap a reserved memory region 0x39ef 0000~0x3a00 0000
> use /dev/mem:
> [  442.704228] pgd = ffff802785f14000
> [  442.707641] [ffff86e4b000] *pgd=000000279080c003, *pud=0000002785f01003, *pmd=0000002783f5b003, *pte=0168000039ef0fd3

The pte seems to have bit 7 set: PTE_RDONLY. So you would get a fault on
write (but not read). Since PTE_WRITE is also set, handle_pte_fault()
will mark the entry as dirty (bit 55, cleared above) and clear
PTE_RDONLY before restarting the access instruction. User space wouldn't
notice, just a slight delay on the first access.

-- 
Catalin

  reply	other threads:[~2017-01-17 11:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-16 10:08 [Question] A question about arm64 pte Yisheng Xie
2017-01-16 11:56 ` Catalin Marinas
2017-01-16 12:39   ` Yisheng Xie
2017-01-16 12:57     ` Steve Capper
2017-01-17  1:04       ` Yisheng Xie
2017-01-16 14:36     ` Catalin Marinas
2017-01-16 14:39       ` Catalin Marinas
2017-01-17  1:02       ` Yisheng Xie
2017-01-17  3:53       ` Yisheng Xie
2017-01-17 11:45         ` Catalin Marinas [this message]
2017-01-17 12:02           ` Yisheng Xie

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