[PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them

[sboyd@codeaurora.org (Stephen Boyd)]

On 01/19, Martin Blumenstingl wrote:
> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
> - a mux clock to choose between different ADC reference clocks (this is
>   2-bit wide, but the datasheet only lists the parents for the first
>   bit)
> - a divider for the input/reference clock
> - a gate which enables the ADC clock
> 
> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
> there is no documentation for this - we just mimic what the vendor
> driver does).
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

This should go through arm-soc along with the other patch to dts.

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