[PATCH 0/4] Updates for Marvell Switch SoCs

[PATCH 0/4] Updates for Marvell Switch SoCs

[Chris Packham]

Shortly after I posted my last series I got access to a more recent
Marvell SDK which had some device tree support for the switch SoCs I'd
been wanting. It was still based on an older kernel but it was a huge
improvement over what came before.

Patch 1/4 is a bit of a cleanup. I did initially struggle with how to
access individual parts of the DFX block as well as retaining a handle on
the entire thing for the switch driver to use.

Patch 2/4 is a re-jig of the dtsi files which is needed by 4/4. This is
required because I need to use the coreclk label on a different node. It
also means I don't have to disable nodes for blocks that only exist on
the Armada-XP.

Patch 3/4 and 4/4 are ported from the Marvell Linux kernel. I've tested
them on the hardware I have access to and things look pretty good.

Chris Packham (4):
  ARM: dts: armada-xp-98dx3236: combine dfx server nodes
  ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
  ARM: mvebu: Add mv98dx3236-soc-id
  clk: mvebu: Expand mv98dx3236-core-clock support

 .../bindings/arm/marvell/mv98dx3236-soc-id.txt     |  14 ++
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
 .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
 .../devicetree/bindings/net/marvell,prestera.txt   |  13 +-
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          | 211 ++++++++++++++++-----
 arch/arm/mach-mvebu/mvebu-soc-id.c                 |  43 ++++-
 drivers/clk/mvebu/Makefile                         |   2 +-
 drivers/clk/mvebu/armada-xp.c                      |  13 --
 drivers/clk/mvebu/mv98dx3236.c                     | 144 ++++++++++++++
 9 files changed, 382 insertions(+), 76 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
 create mode 100644 drivers/clk/mvebu/mv98dx3236.c

-- 
2.11.0.24.ge6920cf

[PATCH 1/4] ARM: dts: armada-xp-98dx3236: combine dfx server nodes

[Chris Packham]

Rather than having a separate node for the dfx server add a reg property
to the parent node. This give somes compatibility with the Marvell
supplied SDK.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 Documentation/devicetree/bindings/net/marvell,prestera.txt | 13 +++++--------
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi                  |  8 ++------
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
index 5fbab29718e8..c329608fa887 100644
--- a/Documentation/devicetree/bindings/net/marvell,prestera.txt
+++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
@@ -32,19 +32,16 @@ DFX Server bindings
 -------------------
 
 Required properties:
-- compatible: must be "marvell,dfx-server"
+- compatible: must be "marvell,dfx-server", "simple-bus"
+- ranges: describes the address mapping of a memory-mapped bus.
 - reg: address and length of the register set for the device.
 
 Example:
 
-dfx-registers {
-	compatible = "simple-bus";
+dfx-server {
+	compatible = "marvell,dfx-server", "simple-bus";
 	#address-cells = <1>;
 	#size-cells = <1>;
 	ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
-
-	dfx: dfx at 0 {
-		compatible = "marvell,dfx-server";
-		reg = <0 0x100000>;
-	};
+	reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 };
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index f6a03dcee5ef..bd8261fdec81 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -195,11 +195,12 @@
 			};
 		};
 
-		dfxr: dfx-registers at ac000000 {
+		dfx: dfx-server at ac000000 {
 			compatible = "simple-bus";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
+			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 
 			dfx_coredivclk: corediv-clock at f8268 {
 				compatible = "marvell,mv98dx3236-corediv-clock";
@@ -208,11 +209,6 @@
 				clocks = <&mainpll>;
 				clock-output-names = "nand";
 			};
-
-			dfx: dfx at 0 {
-				compatible = "marvell,dfx-server";
-				reg = <0 0x100000>;
-			};
 		};
 
 		switch: switch at a8000000 {
-- 
2.11.0.24.ge6920cf

[PATCH 2/4] ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236

[Chris Packham]

The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 194 +++++++++++++++++++++++-------
 1 file changed, 151 insertions(+), 43 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index bd8261fdec81..cbf5cd0c6429 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -45,11 +45,14 @@
  * common to all Armada XP SoCs.
  */
 
-#include "armada-xp.dtsi"
+#include "armada-370-xp.dtsi"
 
 / {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
 	model = "Marvell 98DX3236 SoC";
-	compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
+	compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
 
 	aliases {
 		gpio0 = &gpio0;
@@ -72,12 +75,19 @@
 	};
 
 	soc {
+		compatible = "marvell,armadaxp-mbus", "simple-bus";
+
 		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
 			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
 			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
 			  MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
 			  MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
 
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+		};
+
 		/*
 		 * 98DX3236 has 1 x1 PCIe unit Gen2.0
 		 */
@@ -117,31 +127,92 @@
 		};
 
 		internal-regs {
+			sdramc at 1400 {
+				compatible = "marvell,armada-xp-sdram-controller";
+				reg = <0x1400 0x500>;
+			};
+
+			L2: l2-cache at 8000 {
+				compatible = "marvell,aurora-system-cache";
+				reg = <0x08000 0x1000>;
+				cache-id-part = <0x100>;
+				cache-level = <2>;
+				cache-unified;
+				wt-override;
+			};
+
+			gpio0: gpio at 18100 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18100 0x40>;
+				ngpios = <32>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <82>, <83>, <84>, <85>;
+			};
+
+			/* does not exist */
+			gpio1: gpio at 18140 {
+				compatible = "marvell,orion-gpio";
+				reg = <0x18140 0x40>;
+				status = "disabled";
+			};
+
+			gpio2: gpio at 18180 { /* rework some properties */
+				compatible = "marvell,orion-gpio";
+				reg = <0x18180 0x40>;
+				ngpios = <1>; /* only gpio #32 */
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <87>;
+			};
+
+			systemc: system-controller at 18200 {
+				compatible = "marvell,armada-370-xp-system-controller";
+				reg = <0x18200 0x500>;
+			};
+
+			gateclk: clock-gating-control at 18220 {
+				compatible = "marvell,armada-xp-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
 			coreclk: mvebu-sar at 18230 {
 				compatible = "marvell,mv98dx3236-core-clock";
+				reg = <0x18230 0x08>;
+				#clock-cells = <1>;
 			};
 
 			cpuclk: clock-complex at 18700 {
+				#clock-cells = <1>;
 				compatible = "marvell,mv98dx3236-cpu-clock";
+				reg = <0x18700 0x24>, <0x1c054 0x10>;
+				clocks = <&coreclk 1>;
 			};
 
 			corediv-clock at 18740 {
 				status = "disabled";
 			};
 
-			xor at 60900 {
-				status = "disabled";
+			cpu-config at 21000 {
+				compatible = "marvell,armada-xp-cpu-config";
+				reg = <0x21000 0x8>;
 			};
 
-			crypto at 90000 {
-				status = "disabled";
+			ethernet at 70000 {
+				compatible = "marvell,armada-xp-neta";
 			};
 
-			xor at f0900 {
-				status = "disabled";
+			ethernet at 74000 {
+				compatible = "marvell,armada-xp-neta";
 			};
 
-			xor at f0800 {
+			xor1: xor at f0800 {
 				compatible = "marvell,orion-xor";
 				reg = <0xf0800 0x100
 				       0xf0a00 0x100>;
@@ -161,37 +232,28 @@
 				};
 			};
 
-			gpio0: gpio at 18100 {
-				compatible = "marvell,orion-gpio";
-				reg = <0x18100 0x40>;
-				ngpios = <32>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <82>, <83>, <84>, <85>;
-			};
-
-			/* does not exist */
-			gpio1: gpio at 18140 {
-				compatible = "marvell,orion-gpio";
-				reg = <0x18140 0x40>;
-				status = "disabled";
+			nand: nand at d0000 {
+				clocks = <&dfx_coredivclk 0>;
 			};
 
-			gpio2: gpio at 18180 { /* rework some properties */
-				compatible = "marvell,orion-gpio";
-				reg = <0x18180 0x40>;
-				ngpios = <1>; /* only gpio #32 */
-				gpio-controller;
-				#gpio-cells = <2>;
-				interrupt-controller;
-				#interrupt-cells = <2>;
-				interrupts = <87>;
-			};
+			xor0: xor at f0900 {
+				compatible = "marvell,orion-xor";
+				reg = <0xF0900 0x100
+				       0xF0B00 0x100>;
+				clocks = <&gateclk 28>;
+				status = "okay";
 
-			nand: nand at d0000 {
-				clocks = <&dfx_coredivclk 0>;
+				xor00 {
+					interrupts = <94>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <95>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
 			};
 		};
 
@@ -225,6 +287,53 @@
 			};
 		};
 	};
+
+	clocks {
+		/* 25 MHz reference crystal */
+		refclk: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <25000000>;
+		};
+	};
+};
+
+&i2c0 {
+	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+	reg = <0x11000 0x100>;
+};
+
+&i2c1 {
+	compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+	reg = <0x11100 0x100>;
+};
+
+&mpic {
+	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+};
+
+&timer {
+	compatible = "marvell,armada-xp-timer";
+	clocks = <&coreclk 2>, <&refclk>;
+	clock-names = "nbclk", "fixed";
+};
+
+&watchdog {
+	compatible = "marvell,armada-xp-wdt";
+	clocks = <&coreclk 2>, <&refclk>;
+	clock-names = "nbclk", "fixed";
+};
+
+&cpurst {
+	reg = <0x20800 0x20>;
+};
+
+&usb0 {
+	clocks = <&gateclk 18>;
+};
+
+&usb1 {
+	clocks = <&gateclk 19>;
 };
 
 &pinctrl {
@@ -237,14 +346,13 @@
 	};
 };
 
-&sdio {
-	status = "disabled";
+&spi0 {
+	compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
 };
 
-&crypto_sram0 {
+&sdio {
 	status = "disabled";
 };
 
-&crypto_sram1 {
-	status = "disabled";
-};
-- 
2.11.0.24.ge6920cf

[PATCH 3/4] ARM: mvebu: Add mv98dx3236-soc-id

[Chris Packham]

The DFX server on the 98dx3236 and compatible SoCs has an ID register
that provides revision information that the PCI based ID register
doesn't have. Use this if it's available.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 .../bindings/arm/marvell/mv98dx3236-soc-id.txt     | 14 +++++++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  5 +++
 arch/arm/mach-mvebu/mvebu-soc-id.c                 | 43 ++++++++++++++++++++--
 3 files changed, 59 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt b/Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
new file mode 100644
index 000000000000..ed08cb126a83
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
@@ -0,0 +1,14 @@
+Marvell 98dx3236 SoC ID
+---------------------------------------------------------------
+
+Required properties:
+
+- compatible: Should be "marvell,mv98dx3236-soc-id".
+
+- reg: should be the register base and length as documented in the
+  datasheet for the Device ID Status
+
+soc-id at f8244 {
+	compatible = "marvell,mv98dx3236-soc-id";
+	reg = <0xf8244 0x4>;
+};
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index cbf5cd0c6429..e4baa97836e7 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -264,6 +264,11 @@
 			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 
+			soc-id at f8244 {
+				compatible = "marvell,mv98dx3236-soc-id";
+				reg = <0xf8244 0x4>;
+			};
+
 			dfx_coredivclk: corediv-clock at f8268 {
 				compatible = "marvell,mv98dx3236-corediv-clock";
 				reg = <0xf8268 0xc>;
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index a99434bcee84..b4c94a57f358 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -34,6 +34,9 @@
 #define SOC_ID_MASK	    0xFFFF0000
 #define SOC_REV_MASK	    0xFF
 
+#define MV98DX3236_DEV_ID_MASK	0xFF00
+#define MV98DX3236_REV_MASK	0xF
+
 static u32 soc_dev_id;
 static u32 soc_rev;
 static bool is_id_valid;
@@ -45,6 +48,11 @@ static const struct of_device_id mvebu_pcie_of_match_table[] = {
 	{},
 };
 
+static const struct of_device_id mvebu_mv98dx3236_of_match_table[] = {
+	{ .compatible = "marvell,mv98dx3236-soc-id", },
+	{},
+};
+
 int mvebu_get_soc_id(u32 *dev, u32 *rev)
 {
 	if (is_id_valid) {
@@ -131,15 +139,44 @@ static int __init get_soc_id_by_pci(void)
 	return ret;
 }
 
+static int __init mvebu_dfx_get_soc_id(u32 *dev, u32 *rev)
+{
+	struct device_node *np;
+	void __iomem *base;
+
+	np = of_find_matching_node(NULL, mvebu_mv98dx3236_of_match_table);
+	if (!np)
+		return -ENODEV;
+
+	base = of_iomap(np, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	/* SoC ID */
+	*dev = (readl(base) >> 12) & MV98DX3236_DEV_ID_MASK;
+	/* SoC revision */
+	*rev = (readl(base) >> 28) & MV98DX3236_REV_MASK;
+
+	iounmap(base);
+	of_node_put(np);
+
+	return 0;
+}
+
 static int __init mvebu_soc_id_init(void)
 {
 
 	/*
-	 * First try to get the ID and the revision by the system
-	 * register and use PCI registers only if it is not possible
+	 * First try to get the ID and the revision by from system controller
+	 * register, then try the DFX register (if applicable), finally read it
+	 * from PCI registers.
 	 */
-	if (!mvebu_system_controller_get_soc_id(&soc_dev_id, &soc_rev)) {
+	if (!mvebu_system_controller_get_soc_id(&soc_dev_id, &soc_rev))
+		is_id_valid = true;
+	else if (!mvebu_dfx_get_soc_id(&soc_dev_id, &soc_rev))
 		is_id_valid = true;
+
+	if (is_id_valid) {
 		pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
 		return 0;
 	}
-- 
2.11.0.24.ge6920cf

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Chris Packham]

The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
 .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
 arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
 drivers/clk/mvebu/Makefile                         |   2 +-
 drivers/clk/mvebu/armada-xp.c                      |  13 --
 drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++
 6 files changed, 170 insertions(+), 21 deletions(-)
 create mode 100644 drivers/clk/mvebu/mv98dx3236.c

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index eb985a633d59..796c260c183d 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -31,6 +31,12 @@ The following is a list of provided IDs and clock names on Armada 39x:
  4 = dclk    (SDRAM Interface Clock)
  5 = refclk  (Reference Clock)
 
+The following is a list of provided IDs and clock names on 98dx3236:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = ddrclk   (DDR clock)
+ 3 = mpll    (MPLL Clock)
+
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  0 = tclk   (Internal Bus clock)
  1 = cpuclk (CPU0 clock)
@@ -49,6 +55,7 @@ Required properties:
 	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
 	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
 	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
+	"marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
 	"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 5142efc8099d..de562da2ae77 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -119,6 +119,16 @@ ID	Clock	Peripheral
 29	sata1lnk
 30	sata1	SATA Host 1
 
+The following is a list of provided IDs for 98dx3236:
+ID	Clock	Peripheral
+-----------------------------------
+3	ge1	Gigabit Ethernet 1
+4	ge0	Gigabit Ethernet 0
+5	pex0	PCIe Cntrl 0
+17	sdio	SDHCI Host
+18	usb0	USB Host 0
+22	xor0	XOR DMA 0
+
 The following is a list of provided IDs for Dove:
 ID	Clock	Peripheral
 -----------------------------------
@@ -169,6 +179,7 @@ Required properties:
 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
 	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
+	"marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
 	"marvell,dove-gating-clock" - for Dove SoC clock gating
 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
 - reg : shall be the register address of the Clock Gating Control register
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
index e4baa97836e7..e80a5ee835e5 100644
--- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
+++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi
@@ -176,18 +176,12 @@
 			};
 
 			gateclk: clock-gating-control at 18220 {
-				compatible = "marvell,armada-xp-gating-clock";
+				compatible = "marvell,mv98dx3236-gating-clock";
 				reg = <0x18220 0x4>;
 				clocks = <&coreclk 0>;
 				#clock-cells = <1>;
 			};
 
-			coreclk: mvebu-sar at 18230 {
-				compatible = "marvell,mv98dx3236-core-clock";
-				reg = <0x18230 0x08>;
-				#clock-cells = <1>;
-			};
-
 			cpuclk: clock-complex at 18700 {
 				#clock-cells = <1>;
 				compatible = "marvell,mv98dx3236-cpu-clock";
@@ -264,6 +258,12 @@
 			ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 			reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 
+			coreclk: mvebu-sar at f8204 {
+				compatible = "marvell,mv98dx3236-core-clock";
+				reg = <0xf8204 0x4>;
+				#clock-cells = <1>;
+			};
+
 			soc-id at f8244 {
 				compatible = "marvell,mv98dx3236-soc-id";
 				reg = <0xf8244 0x4>;
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index d9ae97fb43c4..d71c7fd5da16 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK)	+= armada-39x.o
 obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-xtal.o
 obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-tbg.o
 obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-periph.o
-obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
+obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o mv98dx3236.o
 obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
 obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o dove-divider.o
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index 890a863ae0d0..0ec44ae9a2a2 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -232,16 +232,3 @@ static void __init axp_clk_init(struct device_node *np)
 		mvebu_clk_gating_setup(cgnp, axp_gating_desc);
 }
 CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
-
-static void __init mv98dx3236_clk_init(struct device_node *np)
-{
-	struct device_node *cgnp =
-		of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
-
-	mvebu_coreclk_setup(np, &mv98dx3236_coreclks);
-
-	if (cgnp)
-		mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
-}
-CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock",
-	       mv98dx3236_clk_init);
diff --git a/drivers/clk/mvebu/mv98dx3236.c b/drivers/clk/mvebu/mv98dx3236.c
new file mode 100644
index 000000000000..b3948c96bb0a
--- /dev/null
+++ b/drivers/clk/mvebu/mv98dx3236.c
@@ -0,0 +1,144 @@
+/*
+ * Marvell MV98DX3236 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+
+/* For 98DX3236 Sample At Reset the CPU, DDR and Main PLL clocks are all
+ * defined at the same time
+ *
+ * SAR1[20:18]   : CPU frequency    DDR frequency   MPLL frequency
+ *		 1  =  667 MHz	    667 MHz	    2000 MHz
+ *		 2  =  400 MHz	    400 MHz	    400 MHz
+ *		 3  =  800 MHz	    800 MHz	    800 MHz
+ *		 5  =  800 MHz	    400 MHz	    800 MHz
+ *		 others reserved.
+ */
+
+#define	SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT		18
+#define	SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK	0x7
+
+static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
+{
+	/* Tclk = 200MHz, no SaR dependency */
+	return 200000000;
+}
+
+static const u32 mv98dx3236_cpu_frequencies[] __initconst = {
+	0,
+	667000000,
+	400000000,
+	800000000,
+	0,
+	800000000,
+	0, 0,
+};
+
+static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
+{
+	u32 cpu_freq = 0;
+	u8 cpu_freq_select = 0;
+
+	cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
+			   SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK);
+
+	if (of_machine_is_compatible("marvell,armadaxp-98dx3236"))
+		cpu_freq = mv98dx3236_cpu_frequencies[cpu_freq_select];
+
+	if (!cpu_freq)
+		pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+
+	return cpu_freq;
+}
+
+enum {
+	MV98DX3236_CPU_TO_DDR,
+	MV98DX3236_CPU_TO_MPLL
+};
+
+static const struct coreclk_ratio mv98dx3236_core_ratios[] __initconst = {
+	{ .id = MV98DX3236_CPU_TO_DDR, .name = "ddrclk" },
+	{ .id = MV98DX3236_CPU_TO_MPLL, .name = "mpll" },
+};
+
+static const int __initconst mv98dx3236_cpu_mpll_ratios[8][2] = {
+	{0, 1}, {3, 1}, {1, 1}, {1, 1},
+	{0, 1}, {1, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst mv98dx3236_cpu_ddr_ratios[8][2] = {
+	{0, 1}, {1, 1}, {1, 1}, {1, 1},
+	{0, 1}, {1, 2}, {0, 1}, {0, 1},
+};
+
+static void __init mv98dx3236_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) &
+		SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT_MASK);
+
+	switch (id) {
+	case MV98DX3236_CPU_TO_DDR:
+		if (of_machine_is_compatible("marvell,armadaxp-98dx3236")) {
+			*mult = mv98dx3236_cpu_ddr_ratios[opt][0];
+			*div = mv98dx3236_cpu_ddr_ratios[opt][1];
+		}
+		break;
+	case MV98DX3236_CPU_TO_MPLL:
+		if (of_machine_is_compatible("marvell,armadaxp-98dx3236")) {
+			*mult = mv98dx3236_cpu_mpll_ratios[opt][0];
+			*div = mv98dx3236_cpu_mpll_ratios[opt][1];
+		}
+		break;
+	}
+}
+
+static const struct coreclk_soc_desc mv98dx3236_core_clocks = {
+	.get_tclk_freq = mv98dx3236_get_tclk_freq,
+	.get_cpu_freq = mv98dx3236_get_cpu_freq,
+	.get_clk_ratio = mv98dx3236_get_clk_ratio,
+	.ratios = mv98dx3236_core_ratios,
+	.num_ratios = ARRAY_SIZE(mv98dx3236_core_ratios),
+};
+
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
+	{ "ge1", NULL, 3, 0 },
+	{ "ge0", NULL, 4, 0 },
+	{ "pex00", NULL, 5, 0 },
+	{ "sdio", NULL, 17, 0 },
+	{ "usb0", NULL, 18, 0 },
+	{ "xor0", NULL, 22, 0 },
+	{ }
+};
+
+static void __init mv98dx3236_clk_init(struct device_node *np)
+{
+	struct device_node *cgnp =
+		of_find_compatible_node(NULL, NULL, "marvell,mv98dx3236-gating-clock");
+
+	mvebu_coreclk_setup(np, &mv98dx3236_core_clocks);
+
+	if (cgnp)
+		mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc);
+}
+CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", mv98dx3236_clk_init);
-- 
2.11.0.24.ge6920cf

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Stephen Boyd]

On 02/03, Chris Packham wrote:
> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
> Port code from the Marvell supplied Linux kernel to support different
> PLL frequencies and provide clock gating support.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
>  drivers/clk/mvebu/Makefile                         |   2 +-
>  drivers/clk/mvebu/armada-xp.c                      |  13 --
>  drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++

This mixes dts and clk driver changes. Any chance it can be split
up and just have the clk part go through clk tree? Otherwise, I
can ack this if you want to take it all through arm-soc?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Chris Packham]

On 07/02/17 12:14, Stephen Boyd wrote:
> On 02/03, Chris Packham wrote:
>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
>> Port code from the Marvell supplied Linux kernel to support different
>> PLL frequencies and provide clock gating support.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> ---
>>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
>>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
>>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
>>  drivers/clk/mvebu/Makefile                         |   2 +-
>>  drivers/clk/mvebu/armada-xp.c                      |  13 --
>>  drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++
>
> This mixes dts and clk driver changes. Any chance it can be split
> up and just have the clk part go through clk tree? Otherwise, I
> can ack this if you want to take it all through arm-soc?

I'm happy to split it if it will make life easier.

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Stephen Boyd]

On 02/06, Chris Packham wrote:
> On 07/02/17 12:14, Stephen Boyd wrote:
> > On 02/03, Chris Packham wrote:
> >> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
> >> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
> >> Port code from the Marvell supplied Linux kernel to support different
> >> PLL frequencies and provide clock gating support.
> >>
> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> >> ---
> >>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
> >>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
> >>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
> >>  drivers/clk/mvebu/Makefile                         |   2 +-
> >>  drivers/clk/mvebu/armada-xp.c                      |  13 --
> >>  drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++
> >
> > This mixes dts and clk driver changes. Any chance it can be split
> > up and just have the clk part go through clk tree? Otherwise, I
> > can ack this if you want to take it all through arm-soc?
> 
> I'm happy to split it if it will make life easier.
> 

Well do things keep booting if the clk driver parts merge without
the associated dts changes? It's nice to maintain backwards
compatibility even for a short time to make the merge path
easier.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Chris Packham]

On 07/02/17 14:03, Stephen Boyd wrote:
> On 02/06, Chris Packham wrote:
>> On 07/02/17 12:14, Stephen Boyd wrote:
>>> On 02/03, Chris Packham wrote:
>>>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>>>> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
>>>> Port code from the Marvell supplied Linux kernel to support different
>>>> PLL frequencies and provide clock gating support.
>>>>
>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>> ---
>>>>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
>>>>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
>>>>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
>>>>  drivers/clk/mvebu/Makefile                         |   2 +-
>>>>  drivers/clk/mvebu/armada-xp.c                      |  13 --
>>>>  drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++
>>>
>>> This mixes dts and clk driver changes. Any chance it can be split
>>> up and just have the clk part go through clk tree? Otherwise, I
>>> can ack this if you want to take it all through arm-soc?
>>
>> I'm happy to split it if it will make life easier.
>>
>
> Well do things keep booting if the clk driver parts merge without
> the associated dts changes? It's nice to maintain backwards
> compatibility even for a short time to make the merge path
> easier.
>

Unfortunately not. I could put the clk changes first (then I'd just have 
checkpatch.pl complaining about new compatible strings). But if the clk 
patches don't land before the dts changes the boards won't boot. However 
that affects 1 person that we know of (me).

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Chris Packham]

On 07/02/17 14:13, Chris Packham wrote:
> On 07/02/17 14:03, Stephen Boyd wrote:
>> On 02/06, Chris Packham wrote:
>>> On 07/02/17 12:14, Stephen Boyd wrote:
>>>> On 02/03, Chris Packham wrote:
>>>>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>>>>> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
>>>>> Port code from the Marvell supplied Linux kernel to support different
>>>>> PLL frequencies and provide clock gating support.
>>>>>
>>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>>> ---
>>>>>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
>>>>>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
>>>>>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
>>>>>  drivers/clk/mvebu/Makefile                         |   2 +-
>>>>>  drivers/clk/mvebu/armada-xp.c                      |  13 --
>>>>>  drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++
>>>>
>>>> This mixes dts and clk driver changes. Any chance it can be split
>>>> up and just have the clk part go through clk tree? Otherwise, I
>>>> can ack this if you want to take it all through arm-soc?
>>>
>>> I'm happy to split it if it will make life easier.
>>>
>>
>> Well do things keep booting if the clk driver parts merge without
>> the associated dts changes? It's nice to maintain backwards
>> compatibility even for a short time to make the merge path
>> easier.
>>
>
> Unfortunately not. I could put the clk changes first (then I'd just have
> checkpatch.pl complaining about new compatible strings). But if the clk
> patches don't land before the dts changes the boards won't boot. However
> that affects 1 person that we know of (me).
>

Actually I wonder if I can try a bit harder to keep a system booting. 
The following might work
1) add the compatible strings to the existing armada clock drivers.
2) update the dts to use the new compatible strings.
3) add the new driver and remove the compatible strings from the armada 
drivers.

#1 would still upset checkpatch.pl because the documentation would only 
arrive in #2.

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Chris Packham]

On 07/02/17 14:25, Chris Packham wrote:
> On 07/02/17 14:13, Chris Packham wrote:
>> On 07/02/17 14:03, Stephen Boyd wrote:
>>> On 02/06, Chris Packham wrote:
>>>> On 07/02/17 12:14, Stephen Boyd wrote:
>>>>> On 02/03, Chris Packham wrote:
>>>>>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>>>>>> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
>>>>>> Port code from the Marvell supplied Linux kernel to support different
>>>>>> PLL frequencies and provide clock gating support.
>>>>>>
>>>>>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>>>>>> ---
>>>>>>  .../devicetree/bindings/clock/mvebu-core-clock.txt |   7 +
>>>>>>  .../bindings/clock/mvebu-gated-clock.txt           |  11 ++
>>>>>>  arch/arm/boot/dts/armada-xp-98dx3236.dtsi          |  14 +-
>>>>>>  drivers/clk/mvebu/Makefile                         |   2 +-
>>>>>>  drivers/clk/mvebu/armada-xp.c                      |  13 --
>>>>>>  drivers/clk/mvebu/mv98dx3236.c                     | 144 +++++++++++++++++++++
>>>>>
>>>>> This mixes dts and clk driver changes. Any chance it can be split
>>>>> up and just have the clk part go through clk tree? Otherwise, I
>>>>> can ack this if you want to take it all through arm-soc?
>>>>
>>>> I'm happy to split it if it will make life easier.
>>>>
>>>
>>> Well do things keep booting if the clk driver parts merge without
>>> the associated dts changes? It's nice to maintain backwards
>>> compatibility even for a short time to make the merge path
>>> easier.
>>>
>>
>> Unfortunately not. I could put the clk changes first (then I'd just have
>> checkpatch.pl complaining about new compatible strings). But if the clk
>> patches don't land before the dts changes the boards won't boot. However
>> that affects 1 person that we know of (me).
>>
>
> Actually I wonder if I can try a bit harder to keep a system booting.
> The following might work
> 1) add the compatible strings to the existing armada clock drivers.
> 2) update the dts to use the new compatible strings.
> 3) add the new driver and remove the compatible strings from the armada
> drivers.
>
> #1 would still upset checkpatch.pl because the documentation would only
> arrive in #2.

Actually upon testing #1 is unnecessary. I lose some of the gated clocks 
but nothing that prevents booting.

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Arnd Bergmann]

On Tuesday, February 7, 2017 3:07:37 AM CET Chris Packham wrote:
> >
> > Actually I wonder if I can try a bit harder to keep a system booting.
> > The following might work
> > 1) add the compatible strings to the existing armada clock drivers.
> > 2) update the dts to use the new compatible strings.
> > 3) add the new driver and remove the compatible strings from the armada
> > drivers.
> >
> > #1 would still upset checkpatch.pl because the documentation would only
> > arrive in #2.
> 
> Actually upon testing #1 is unnecessary. I lose some of the gated clocks 
> but nothing that prevents booting.

Just to be sure: this means we can merge 2) and 3) independently and
having just one of them will not cause regressions over what we have
today?

	Arnd

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Chris Packham]

On 08/02/17 23:53, Arnd Bergmann wrote:
> On Tuesday, February 7, 2017 3:07:37 AM CET Chris Packham wrote:
>>>
>>> Actually I wonder if I can try a bit harder to keep a system booting.
>>> The following might work
>>> 1) add the compatible strings to the existing armada clock drivers.
>>> 2) update the dts to use the new compatible strings.
>>> 3) add the new driver and remove the compatible strings from the armada
>>> drivers.
>>>
>>> #1 would still upset checkpatch.pl because the documentation would only
>>> arrive in #2.
>>
>> Actually upon testing #1 is unnecessary. I lose some of the gated clocks
>> but nothing that prevents booting.
>
> Just to be sure: this means we can merge 2) and 3) independently and
> having just one of them will not cause regressions over what we have
> today?
>

Correct. And that's what I sent out as v2.

http://lists.infradead.org/pipermail/linux-arm-kernel/2017-February/486467.html
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-February/486471.html

[PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support

[Stephen Boyd]

On 02/08, Chris Packham wrote:
> On 08/02/17 23:53, Arnd Bergmann wrote:
> > On Tuesday, February 7, 2017 3:07:37 AM CET Chris Packham wrote:
> >>>
> >>> Actually I wonder if I can try a bit harder to keep a system booting.
> >>> The following might work
> >>> 1) add the compatible strings to the existing armada clock drivers.
> >>> 2) update the dts to use the new compatible strings.
> >>> 3) add the new driver and remove the compatible strings from the armada
> >>> drivers.
> >>>
> >>> #1 would still upset checkpatch.pl because the documentation would only
> >>> arrive in #2.
> >>
> >> Actually upon testing #1 is unnecessary. I lose some of the gated clocks
> >> but nothing that prevents booting.
> >
> > Just to be sure: this means we can merge 2) and 3) independently and
> > having just one of them will not cause regressions over what we have
> > today?
> >
> 
> Correct. And that's what I sent out as v2.
> 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-February/486467.html
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-February/486471.html
> 

Ok... so I'll apply the 6/6 patch now to the clk tree.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project